MICROCONTROLLER

4. Timers
 What is timer?
Timer is used to set time for a job
Time remain? How long is a tick?

Time remain = time for a tick x number of ticks 2

 Timer in microcontroller
• Timer is a peripheral module
• Each timer module has:
 A reload register: hold the time limit (number of ticks)
 A counter register: hold the number of ticks which has been count
 Selectable clock sources
 A prescaler: divides system clock by some value before feeding it
to the timer
period of 1 tick = system clock period x prescaler

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 Timing functions
• Periodically interrupt CPU to perform tasks
- Sample sensor readings (temperature, pressure, etc.)
- Generate control signals

• Provide accurate time delays

- Instead of software loops
• Generate pulses or periodic waveforms
- PWM signal for motor control
- Strobe pulse for an external device
• Measure duration of an external event
- Tachometer signal period to measure motor speed
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 Cortex-M Timers
There are 4 types of timers in Cortex-M
• System timer (SysTick): simple 24-bit down counter
- standard hardware component built into ARM Cortex-M.
• Basic Timers
- designed to measure time intervals, generate one shot or generate repetitive
interrupts
- completely independent, and do not share any resources
• General-purpose Timers
- Input capture, output compare, PWM, one pulse mode, Encoder interface
- Interrupt generation with events
• Advanced Timers
- Input capture, output compare, PWM, one pulse mode
- Complementary Outputs with programmable dead-time insertion, support 3-
phase motor control
- More interrupt events 5
Systick Timer

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 System Timer (SysTick)
Systick timer is a standard hardware component built into ARM Cortex-M.

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Diagram of SysTick
SysTick reload value register
(SysTick_LOAD)

SysTick current value register

(SysTick_VAL)

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SysTick interrupt

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Calculating Reload Value

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 Implementing SysTick
Systick Registers address and Config function are defined in core_cm4.h and <device>.h

<device>.h

core_cm4.h

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 Implementing SysTick

Implementing
Delay(msex) Function

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Basic Fucntion Timer

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 Basic Timer
Basic timer (TIM6/TIM7)
• 16-bit auto-reload upcounter APB1 clock
• 16-bit programmable
prescaler TIMx_CRy
• Synchronization circuit to trigger TIMx_ARR
the DAC
• Interrupt generation on the
update event: counter overflow
• Can operate in 2 modes: TIMx_PSC TIMx_CNT

- Repetitive mode
- One shot mode

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 Basic Timer Clock Source
can be R/W on the fly
AHB APB1 Prescaler Timer Prescaler
Counter
Clock (/ 1,2,4,8,16) x1 or x2 (/ 1 to 65535 )
RCC_CFGR TIMx_PSC Enable by
bit [10:8] bit [15:0] TIMx_CR1
bit [0]

Example:
Note:
Given HCLK= 32 MHz For STM32L4xx, there are two cases:
1. If the APB prescaler equals 1, the
APB1 prescaler = 1/8 and Timer prescaler = 1/4 timer clock frequencies are set to the
same frequency as that of the APB
We have ftimer = 32/8/4 x 2 = 2 MHz and domain.
2. Otherwise, they are set to twice (×2)
Teach count = 0.5 µs the frequency of the APB domain.
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 Basic Timer Operation

0xFFFF

ARR

CNT

Need to enable
timer interrupt UIF
(TIMx_DIER bit 0)

CEN

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Basic Timer Operation

ARR

CNT

UIF

CEN

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 Basic Timer Interrupt
Occur when counter overflow
• UIF is set to 1 by hardware, need to be cleared by software in the interrupt function
• If UIE = 1, the processor will be interrupted and call the interrupt function
Interrupt function
• Interrupt function name is predefined in startup_<device>.s
TIM6_DAC_IRQHandler and TIM7_IRQHandler
• Template of the interrupt function
void TIM6_DAC_IRQHandler (void)
{
/* clear the interrupt flag */
TIM6->SR = 0;

/* Your code */

}
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 Basic Timer Control Registers
Basic timer registers are defined in <device.h>
• TIMx_CR1: enable counter, select operation mode
• TIMx_CR2: select trigger output source
• TIMx_DIER: enable/disable Timer interrupt
• TIMx_SR: status of interrupt flag -> clear this register in interrupt
function
• TIMx_CNT: counter value
• TIMx_PSC: prescaler value
• TIMx_ARR: auro reload value

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 Basic Timer Initialization

1. Turn on BFTM clock in APB1 Clock enable register – APB1ENR (bit[5:4)

- APB1ENR bits 4-5 enable clock for TIM6-TIM7, respectively
RCC->APB1ENR |= (1<<4); //enable TIM6 clock
2. Set APB1 clock prescaler in RCC_CFGR bit [10:8] and Timer prescaler
RCC->CFGR |= (5<<8); // APB1 prescaler 1/4
TIM6->PSC = 20; // timer prescaler 1/20
3. Select operation mode, enable update interrupt (optional)
TIM6->CR1 &= ~(1<<3); // one shot mode
TIM6->DIER |= (1<<0); // enable interrupt
4. Set reload value and reset counter value
TIM6->ARR = 0x32000;
TIM6->CNT = 0;
5. Enable timer counter
TIM6->CR1 |= (1<<0);
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 Interrupt and
Exception Handling

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 How CPU processes the Interrupt

1. Finish processing current 2. Run interrupt service 3. Resume main

instruction. Save program routine. Restore Program program
counter and flags to stack counter and flags from stack

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http://learn.mikroe.com/ebooks/piccprogramming/chapter/pic16f887-basic-features/
 Interrupt Service Routine (ISR)

• Subroutines used to service an interrupt are call IRQHandler

e.g. ADC_IRQHandler, UART_IRQHandler
• Each interrupt has an IRQHandler which has an address listed in Interrupt
Vector Table
• Interrupts and exceptions are divided into multiple levels of priority  Nested
Interrupt
• Nested Vectored Interrupt Controller (NVIC): A programmable hardware
unit inside the Cortex-M processors to handle the management of interrupts and
exception requests

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 Interrupt Signal Flow
Each potential interrupt source has a separate enable bit
• Set for devices from which interrupts are to be accepted
• Clear to prevent the peripheral from interrupting the CPU

Each potential interrupt source has a separate flag bit

• hardware sets the flag when an “event” occurs
• Interrupt request = (flag & enable)
• ISR software must clear the flag to acknowledge the request
• test flags in software if interrupts not desired

Nested Vectored Interrupt Controller (NVIC)

• Receives all interrupt requests
• Each has an enable bit and a priority within the VIC
• Highest priority enabled interrupt sent to the CPU

Within the CPU:

• Global interrupt enable bit in PRIMASK register
• Interrupt if priority of IRQ < that of current thread
• Access interrupt vector table with IRQ# 24
 Prioritized Interrupts Mask
Register (PRIMASK)

Use CMSIS functions to clear/set PRIMASK

__enable_irq(); //enable interrupts (set PRIMASK=0)
__disable_irq(); //disable interrupts (set PRIMASK=1)
(double-underscore at beginning)
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Cortex-M NVIC

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 Cortex-M NVIC

• NVIC manages and prioritizes

external interrupts in Cortex-M
• NVIC interrupts CPU with IRQ#
of highest-priority IRQ signal
• CPU uses IRQ# to access the
vector table & get intr. handler
start address

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Cortex-M CPU and peripheral
exceptions

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 Interrupt Vector table

• 32-bit vector contain handler’s address

• Declare in startup_<device>.s

• Peripherals use positive IRQ #s

• CPU exceptions use negative IRQ #s
• IRQ # used in CMSIS function calls

• Cortex-M4 allows up to 240 IRQs (90 in

STM32L4xx)

• IRQ priority is programmable

- up to 256 priority levels (16 in STM32L4) 29

Interrupt priority levels

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Interrupt priority levels

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 Interrupt Priority Registers

The NVIC_IPRx registers provide an 8-bit priority field for each interrupt.

STM32L4xx uses upper 4 bits [7:4] of

each priority byte  16 levels
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NVIC Registers

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Accessing the NVIC registers
using CMSIS

IRQn: Interrupt number

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 Accessing the NVIC registers
using CMSIS
Enable/disable interrupts

The number for each IRQn are defined in <device>.h

Example:
EXTI0_IRQn = 6 ; //External interrupt EXTI0 is IRQ #6
TIM2_IRQn = 28 ; //Timer TIM2 interrupt is IRQ #28
Usage:
NVIC_EnableIRQ(EXTI0_IRQn); //enable external interrupt EXTI0
NVIC_DisableIRQ(TIM2_IRQn); //disable interrupt from timer TIM2
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 Accessing the NVIC registers
using CMSIS
Interrupts pending
NVIC interrupt pending flag for each IRQ
• NVIC sets pending flag when it detects IRQn request
- IRQn status changes to “pending”
- IRQn status changes to “active” when its interrupt handler is entered
• NVIC clears pending flag when handler exited
- IRQn status changes to “inactive”
CMSIS functions to set/clear/get IRQn pending status
• Write 1 to NVIC_ICPRx to clear IRQn from pending state
NVIC_ClearPendingIRQ(IRQn);
• Write 1 to NVIC_ISPRx to force IRQn into pending state
NVIC_SetPendingIRQ(IRQn); //simulates IRQn request
• Read 1 from ISPR if IRQn in pending state
NVIC_GetPendingIRQ(IRQn); 36
 Accessing the NVIC registers
using CMSIS
Set interrupts priorites
• NVIC selects highest-priority pending IRQ to send to CPU
- Lower priority# = higher priority (default value = 0)
+ If equal priorities, lower IRQ# selected
- Higher priority IRQ can interrupt lower priority one
- Lower priority IRQ not sent to CPU until higher priority IRQ service
completed
• Set IRQn priority via CMSIS function: NVIC_SetPriority(IRQn, priority);
Ex:
//set ext. intr. EXTI0 priority = 1
NVIC_SetPriority(EXTI0_IRQn, 1);
• Get IRQn priority via CMSIS function: NVIC_GetPriority(IRQn_Type IRQn)
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Example

int main (void){

…
/* Enable interrupt */
__enable_irq();
/* Set Priority */
NVIC_SetPriority(EXTI0_IRQn,0);
/* Clear the pending bit */
NVIC_ClearPendingIRQ(EXTI0_IRQn);
/* Enable EXTI0 interrupt*/
NVIC_EnableIRQ(EXTI0_IRQn);
…
}
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