Abhi
Abhi
Abhi
1.When both J and K are 0, the flip-flop retains its current state
regardless of the clock signal.
2.When J is 0 and K is 1, the flip-flop resets to 0, regardless of the
clock signal.
3.When J is 1 and K is 0, the flip-flop sets to 1, regardless of the
clock signal.
4.When both J and K are 1, the flip-flop toggles its state (Q(t+1) is
the complement of Q(t)), regardless of the clock signal.
ADVANTAGE OF MASTER SLAVE JK….
1 . A sequential circuit with a level-triggered flip flop is challenging to
design, but edge triggered flip flop is easy to design.