Scribd Logo
Upload

Welcome to Scribd!

  • 192 views

    Practical 11: AIM: To Study JK Flip Flop Circuit. Theory

    Uploaded by

    yagnesh
    This document describes the JK flip flop circuit. It explains that a JK flip flop can be used to build a counter that counts the positive or negative clock edges at its clock input. The circuit diagram and truth table of the JK flip flop are provided. The truth table shows the output for different combinations of inputs J and K on the positive clock edge. It also explains the functioning of the JK flip flop for each case in the truth table.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Practical 11: AIM: To Study JK Flip Flop Circuit. Theory

    Uploaded by

    yagnesh
    192 views2 pages
    This document describes the JK flip flop circuit. It explains that a JK flip flop can be used to build a counter that counts the positive or negative clock edges at its clock input. The circuit diagram and truth table of the JK flip flop are provided. The truth table shows the output for different combinations of inputs J and K on the positive clock edge. It also explains the functioning of the JK flip flop for each case in the truth table.

    Original Title

    pr11-JK flip-flop

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document describes the JK flip flop circuit. It explains that a JK flip flop can be used to build a counter that counts the positive or negative clock edges at its clock input. The circuit diagram and truth table of the JK flip flop are provided. The truth table shows the output for different combinations of inputs J and K on the positive clock edge. It also explains the functioning of the JK flip flop for each case in the truth table.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    192 views2 pages

    Practical 11: AIM: To Study JK Flip Flop Circuit. Theory

    Uploaded by

    yagnesh
    This document describes the JK flip flop circuit. It explains that a JK flip flop can be used to build a counter that counts the positive or negative clock edges at its clock input. The circuit diagram and truth table of the JK flip flop are provided. The truth table shows the output for different combinations of inputs J and K on the positive clock edge. It also explains the functioning of the JK flip flop for each case in the truth table.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 2

    2CE302: Digital Electronics

    Practical 11
    AIM: To study JK Flip flop circuit.

    THEORY:

    JK flip-flop can be used to build a counter that counts the number of positive or negative
    clock edges driving its clock input. For the purpose of counting, the JK flip-flop is the ideal
    element to use. The fig. shows circuit diagram of JK flip-flop. The truth table is as under.

    CLK J K Q n+1
    X 0 0 On (Last state)
    ↑ 0 1 0 (Reset)
    ↑ 1 0 1(Set)
    ↑ 1 1 On’(toggle)

    When J & K both are at low state, both AND gate are disabled and so clock pulse has no
    effect i.e. Q retains its last value. When J=0 & K=1 upper gate is disable so there is no way to
    set the flip-flop. The only possibility is RESET. When Q is high, the power gate passes a
    RESET triggers as soon as the next positive clock edge arrives. This forces Q to become low.
    When J=1 & K=0, lower gate is disable so it is impossible to RESET the flip-flop. We can
    SET the flip-flop. When Q is low Q bar is high. Therefore the upper gate passes a SET trigger
    on the next positive clock edge. This drives Q into high state i.e. Q=1.When J=1 & K=1 then
    there is a forbidden state with RS flip flop i.e. it is impossible to SET or RESET the flip flop.
    If Q is high, the lower gate passes a RESET trigger on the next positive clock edge. On the
    other hand when Q is low the upper gate passes a SET trigger on the next positive clock edge.
    Either way Q changes to the complement of the last state. Therefore J=1 & K=1 means the
    flip flop will toggle on the next positive clock edge. The toggle means to switch to the
    opposite state. Thus by addition of clock and getting propagation delay, racing problem can
    be eliminated in JK flip flop.

    1
    2CE302: Digital Electronics

    PROCEDURE:
    1. Connect circuit as per the circuit diagram and give 5V DC power supply to input
    terminals.
    2. Switch ON the power supply.
    3. Change the state of J & K as per truth-table and note down the status of output at
    every stage as per truth-table.
    4. Closely watch the output.

    CONCLUSION:

    You might also like