Lecture-4 Computer Organization & Assembly Language Programming

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Assembly Language Programming

Lecture-4
Computer Organization & Assembly
Language Programming
SEGMENTED MEMORY MODEL

• In earlier processors like 8080 and 8085 the linear memory model
was used to access memory.
• In linear memory model the whole memory appears like a single
array of data. 8080 and 8085 could access a total memory of 64K
using the 16 lines of their address bus.
• When designing iAPX88 the Intel designers wanted to remain
compatible with 8080 and 8085 however 64K was too small to
continue with, for their new processor.
SEGMENTED MEMORY MODEL

• We have two logical parts of our program, the code and the data,
and actually there is a third part called the program stack as well,
but higher-level languages make this invisible to us.
• These three logical parts of a program should appear as three
distinct units in memory, but making this division is not possible in
the linear memory model. The segmented memory model does
allow this distinction.
Mechanism

• The segmented memory model allows multiple functional windows


into the main memory, a code window, a data window etc.
• The processor sees code from the code window and data from the
data window. The size of one window is restricted to 64K. 8085
software fits in just one such window. It sees code, data, and stack
from this one window, so downward compatibility is attained.
• However, the maximum memory iAPX88 can access is 1MB which
can be accessed with 20 bits. Compare this with the 64K of 8085
that were accessed using 16 bits.
• The idea is that the 64K window just discussed can be moved
anywhere in the whole 1MB. The four segment registers discussed
in the Intel register architecture are used for this purpose.
Mechanism

• The window is of a fixed size of 64KB. Baseband offset are the two
key variables in a segmented address. Segment tells the base while
offset is added into it.
• The registers IP, SP, BP, SI, DI, and Ball can contain a 16bit offset
in them and access memory relative to a segment base. The IP
register cannot work alone.
• It needs the CS register to open a 64Kwindow in the 1MB memory
and then IP works to select code from this window as offsets. IP
works only inside this window and cannot go outside of this 64K in
any case.
• If the window is moved i.e. the CS register is changed will change
its behavior accordingly and start selecting from the new window.
Physical Address Calculation

• Now for the whole megabyte we need 20 bits while CS and IP are
both16bit registers.
• We need a mechanism to make a 20bit number out of the two16bit
numbers. Consider that the segment value is stored as a 20-bit
number with the lower four bits zero and the offset value is stored
as another 20-bit number with the upper four bits zeroed.
• The two are added to produce a20bit absolute address. A carry if
generated is dropped without being stored anywhere and the
phenomenon is called address wraparound
Physical Address Calculation
16-bit segment 16-bit offset

0000 0000
20-bit segment
+ 20-bit offset

20-bit Physical Address


Address Calculation

1 D D D 0
+ 0 0 1 0 0
1 D E D 0

20 –Bit Physical Address Calculation


Segment Base

16 – Bit Segment Register Value


0 0 0 0

0 0 0 0 0
20 – Bit Segment = 0 Decimal
Segment Base

16 – Bit Segment Register Value


0 0 0 1

0 0 0 1 0
20 – Bit Physical Address = 16 Decimal

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