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    Familia 68 K

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    Panos Brinias
    Motorola's 68K processor family includes the 68000, 68020, 68030 and 68040 processors. The 68000 was Motorola's first 32-bit processor and introduced the 68K architecture. It has 19 registers including 8 general data registers and 7 general address registers. The 68020 added more registers and features like on-chip caches. The 68030 added virtual memory support with an on-chip MMU. The 68040 combined the features of the 68030 with an on-chip FPU.

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    Familia 68 K

    Uploaded by

    Panos Brinias
    27 views3 pages
    Motorola's 68K processor family includes the 68000, 68020, 68030 and 68040 processors. The 68000 was Motorola's first 32-bit processor and introduced the 68K architecture. It has 19 registers including 8 general data registers and 7 general address registers. The 68020 added more registers and features like on-chip caches. The 68030 added virtual memory support with an on-chip MMU. The 68040 combined the features of the 68030 with an on-chip FPU.

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    Μοτορολα 68Κ

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    Familia 68 k

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    Motorola's 68K processor family includes the 68000, 68020, 68030 and 68040 processors. The 68000 was Motorola's first 32-bit processor and introduced the 68K architecture. It has 19 registers including 8 general data registers and 7 general address registers. The 68020 added more registers and features like on-chip caches. The 68030 added virtual memory support with an on-chip MMU. The 68040 combined the features of the 68030 with an on-chip FPU.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    27 views3 pages

    Familia 68 K

    Uploaded by

    Panos Brinias
    Motorola's 68K processor family includes the 68000, 68020, 68030 and 68040 processors. The 68000 was Motorola's first 32-bit processor and introduced the 68K architecture. It has 19 registers including 8 general data registers and 7 general address registers. The 68020 added more registers and features like on-chip caches. The 68030 added virtual memory support with an on-chip MMU. The 68040 combined the features of the 68030 with an on-chip FPU.

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    of 3

    Motorola's 68K Processor Family

    68000 Processor Software Model


    We have already said that the software model of a processor is used to give programmer
    some understanding of the operation, resources and structure of the processor. Motorola's
    68K family differs from x86 in many aspects. The most important difference is in the way
    memory is accessed. 68000 is also an internal 32-bit machine which means the registers
    are 32-bits instead of 16-bits. 68000 has a Program Counter (PC) and it is used to address
    the memory space linearly (instead of adding the segment base address with an offset to
    obtain the final address).
    There are 19 registers in a 68000. 8 of them are general data registers (D0-D7). It has 7
    general address registers. It has two stack pointers - one for user and one for the system
    (USP and SSP respectively). There is also a processor status word which is 16-bit and a
    program counter (32-bit). The 68000 is a general purpose register-based machine and
    every data register can be used as an accumulator or as a temp register. 68000 arranges
    the data bytes with least-significant byte at the higher address. This approach is called the
    big ending approach.
    msb
    lsb
    +---------- +
    |B0
    |B1
    |
    +---------- +
    |B2
    |B3
    |
    +---------- +
    |
    |
    |
    +---------- +
    |
    |
    |
    +---------- +
    +---------| Word 0
    +---------| Word 1
    +---------| Word 2
    +---------| Word 3
    +----------

    +
    |
    +
    |
    +
    |
    +
    |
    +

    +---------- +
    |LongWord0 H|
    +---------- +
    |LongWord0 L|
    +---------- +
    |LongWord1 H|
    +---------- +
    |LongWord1 L|
    +---------- +

    Addressing Modes
    68000 is a CISC machine and has many addressing modes (14 to be exact). These
    addressing modes can be categorized into 6 groups.
    Address generation
    Assembler Syntax
    --------------------------------------------------------------------

    (1)Register Direct
    Data Register Direct
    Address register direct
    (2)Address Register Indirect
    Register Indirect

    Dn
    An
    (An)

    Dn
    An
    (An)

    Postincrement Reg Indirect


    Predecrement Reg Indirect
    Reg. Indirect with offset
    Indexed Reg. Indirect with offset
    (3)Absolute Data Register
    Absolute Short
    Absolute Long
    (4)Program Counter Relative
    Relative with Offset
    Relative with Index and Offset
    (5)Immediate Data
    Immediate
    Quick Immediate
    (6)Immplied Addressing
    Implied Register

    (An); An<-An+N
    (An)+
    An<-An-N; (An)
    -(An)
    (An)+ disp16
    d(An)
    (An)+ (Ri) + disp8 d(An)
    (Next Word)
    (Next two Word)
    (PC)+disp16
    (PC)+ (Ri) + disp8

    xxxx
    xxxxxxxx
    d
    d(Ri)

    DATA = Next Word(s) #xxxx


    inherent data
    #xx
    SR, USP, SSP, PC

    68000 Memory
    68000 uses linear address to access the memory. Even though it has a 32-bit PC, only the
    lower 24 bits are used. With 24-bit address it can directly access up to 16 MB of memory.
    68000 Stacks
    68000 supports stacks and queues with the address register indirect postinrement and
    predecrement addressing modes. That is, with register indirect addressing mode all of the
    seven address registers can be used as stack pointers. Subroutine calls, trap and
    interrupts use the dedicated stack pointers - USP and SSP. Stacks from high to low
    memory are implemented with predecrement mode for PUSH and postincrement mode for
    POP. On the other hand, stacks from low to high use postinrement for PUSH and
    predecrement for POP. (Note: when address registers is used only 24 bits are valid.)
    68020
    68020 is a true 32-bit processor and it is object code compatible with 68000. It has many
    more registers. Besides the 8-data registers, 7-address registers, 1-PC and 1-SR, there
    are 3 SPs instead of 2. There are also 1 16-bit Vector-Based Register (VBR), 2 3-bit
    function code registers, 1 32-bit Cache address register (CAAR) and 1 32-bit Cache
    COntrol Register (CACR). There is an on-chip instruction cache of size 128 words (16-bit).
    The PC is a true 32-bit registers and can address up to 4GB of memory space. There are
    new instructions as well as new addressing modes. The new addressing modes are
    related to Memory Indirect and Memory INdirect with PC.
    68030
    68030 is a virtual memory processor based on 68020. That is 68030 has on-chip memory
    management unit which performs the paged data memory management. There are four
    new instructions for the MMU part of the processor. It also has an on-chip data cache of
    size 128 words besides the instruction cache.
    68040
    68040 is a better implemented 68030. It has larger on-chip data and instruction caches. It
    also has an on-chip floating point unit.
    Example Assembly Programs for 8086 and 68000
    The following two programs implements the summation of multiplying two set of numbers.
    This process is described as SUM Xi*Yi for i=1 to 100. In a pseudo language this
    calculation is described as:
    sum <- 0
    for i<- 1 to 100 do

    endfor

    sum <- sum + X(i) * Y(i)

    In 68000 assembly code


    ; both Xs and Ys are16-bits and the result is 32-bit.

    LOOP:

    MOVEQ.L #99, D0
    ; DO is the index i
    LEA
    P, A0
    ; Array X starts at P
    LEA
    Q, A1
    ; Array Y starts at Q
    CLR.L D1
    ;
    MOVE (A0)+, D2 ; get X(i)
    MULS (A1)+, D2 ; get Y(i) and dose the multiply X(i)*Y(i)
    ADD.L
    D2, D1
    ; sum <- sum + X(i)*Y(i)
    DBF
    D0, LOOP ; test for zero; decrement and loop

    In 8086 assembly code


    ; this is 8-bit by 8-bit multiply only. TO do 16-bit by 16-bit the code
    ; will be more complicated.
    MOV
    MOV
    MOV
    LEA
    LEA
    MOV
    LOOPA: MOV
    IMUL
    ADD
    INC
    INC
    LOOP

    AX, 2000H ; Setup the data segment register


    DS, AX
    ; load the data segment base
    CX, 100
    ; index i
    BX, P
    ; load X address
    SI, Q
    ; Load Y address
    DX, 0000H ; sum <- 0
    AL, [BX] ; get X(i)
    [SI]
    ; X(i)*Y(i)
    DX, AX
    ; sum <- sum + X(i)*Y(i)
    BX
    ; next X
    SI
    ; next Y
    LOOPA

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