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William Stallings
Computer Organization
and Architecture
9th Edition
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Chapter 14
Processor Structure and Function
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14.1 Processor Organization
Processor Requirements:
 Fetch instruction
 The processor reads an instruction from memory (register, cache, main memory)

 Interpret instruction
 The instruction is decoded to determine what action is required

 Fetch data
 The execution of an instruction may require reading data from memory or an I/O module

 Process data
 The execution of an instruction may require performing some arithmetic or logical operation
on data

 Write data
 The results of an execution may require writing data to memory or an I/O module

 In order to do these things the processor needs to store some data temporarily and
therefore needs a small internal memory
CPU With the System Bus
CPU Internal Structure
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14.2 Register Organization
 Within the processor there is a set of registers that function as a level of
memory above main memory and cache in the hierarchy

 The registers in the processor perform two roles:

User-Visible Registers Control and Status Registers

 Enable the machine or assembly  Used by the control unit to control
language programmer to minimize the operation of the processor and
main memory references by by privileged operating system
optimizing use of registers programs to control the execution
of programs
User-Visible Registers

Categories:

Referenced by means of the • General purpose

machine language that the • Can be assigned to a variety of functions by the
programmer
processor executes • Data
• May be used only to hold data and cannot be
employed in the calculation of an operand
address
• Address
• May be somewhat general purpose or may be
devoted to a particular addressing mode
• Examples: segment pointers, index registers,
stack pointer
• Condition codes
• Also referred to as flags
• Bits set by the processor hardware as the result
of operations
 Table 14.1
Condition Codes
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Control and Status Registers
Four registers are essential to instruction execution:

 Program counter (PC)

 Contains the address of an instruction to be fetched

 Instruction register (IR)

 Contains the instruction most recently fetched

 Memory address register (MAR)

 Contains the address of a location in memory

 Memory buffer register (MBR)

 Contains a word of data to be written to memory or the word most recently
read
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Program Status Word (PSW)

Register or set of registers that contain

status information

Common fields or flags include:

• Sign
• Zero
• Carry
• Equal
• Overflow
• Interrupt Enable/Disable
• Supervisor
 Example
Microprocessor
Register Organizations
14.3 Instruction Cycle

Includes the following

stages:

Fetch Execute Interrupt

If interrupts are enabled

Read the next instruction Interpret the opcode and and an interrupt has
from memory into the perform the indicated occurred, save the
processor operation current process state and
service the interrupt
Instruction Cycle
Instruction Cycle State Diagram
Data Flow, Fetch Cycle
Data Flow, Indirect Cycle
Data Flow, Interrupt Cycle
14.4 Instruction Pipelining

Pipelining Strategy
To apply this concept to
instruction execution we
Similar to the use of an must recognize that an
assembly line in a instruction has a number
manufacturing plant of stages

New inputs are accepted

at one end before
previously accepted
inputs appear as outputs
at the other end
Two-Stage Instruction Pipeline
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Additional Stages
 Fetch instruction (FI)
 Fetch operands (FO)
 Read the next expected
instruction into a buffer  Fetch each operand from
memory
 Decode instruction (DI)  Operands in registers need not
 Determine the opcode and the be fetched
operand specifiers
 Execute instruction (EI)
 Calculate operands (CO)  Perform the indicated operation
 Calculate the effective address and store the result, if any, in the
of each source operand specified destination operand
 This may involve displacement, location
register indirect, indirect, or
 Write operand (WO)
other forms of address
calculation  Store the result in memory
Timing Diagram for Instruction Pipeline
Operation
The Effect of a Conditional Branch on
Instruction Pipeline Operation
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Six Stage
Instruction Pipeline
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Alternative Pipeline
Depiction
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Speedup Factors
with Instruction
Pipelining
 Pipeline Hazards
Occur when the
pipeline, or some
portion of the pipeline, There are three types of
must stall because hazards:
conditions do not • Resource
permit continued • Data
execution • Control

Also referred to as a
pipeline bubble
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Resource
Hazards

A resource hazard occurs when two or

more instructions that are already in the
pipeline need the same resource

The result is that the instructions must be

executed in serial rather than parallel for a
portion of the pipeline

A resource hazard is sometimes referred to

as a structural hazard
 RAW

Hazard

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Data Hazards
A data hazard occurs when there is a conflict in the access of an
operand location
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Types of Data Hazard
 Read after write (RAW), or true dependency
 An instruction modifies a register or memory location
 Succeeding instruction reads data in memory or register location
 Hazard occurs if the read takes place before write operation is complete

 Write after read (WAR), or antidependency

 An instruction reads a register or memory location
 Succeeding instruction writes to the location
 Hazard occurs if the write operation completes before the read operation takes place

 Write after write (WAW), or output dependency

 Two instructions both write to the same location
 Hazard occurs if the write operations take place in the reverse order of the intended
sequence
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Control Hazard

 Also known as a branch hazard

 Occurs when the pipeline makes the wrong decision on a branch

prediction

 Brings instructions into the pipeline that must subsequently be discarded

 Dealing with Branches:

 Multiple streams
 Prefetch branch target
 Loop buffer
 Branch prediction
 Delayed branch
 Multiple Streams

A simple pipeline suffers a penalty for a branch instruction

because it must choose one of two instructions to fetch next and
may make the wrong choice

A brute-force approach is to replicate the initial portions of the

pipeline and allow the pipeline to fetch both instructions, making
use of two streams

Drawbacks:
• With multiple pipelines there are contention delays for access to the registers and
to memory
• Additional branch instructions may enter the pipeline before the original branch
decision is resolved
Prefetch Branch Target

 When a conditional branch is recognized, the target

of the branch is prefetched, in addition to the
instruction following the branch

 Target is then saved until the branch instruction is

executed

 If the branch is taken, the target has already been

prefetched

 IBM 360/91 uses this approach

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Loop Buffer
 Small, very-high speed memory maintained by the instruction fetch
stage of the pipeline and containing the n most recently fetched
instructions, in sequence

 Benefits:
 Instructions fetched in sequence will be available without the usual memory
access time
 If a branch occurs to a target just a few locations ahead of the address of the
branch instruction, the target will already be in the buffer
 This strategy is particularly well suited to dealing with loops

 Similar in principle to a cache dedicated to instructions

 Differences:
 The loop buffer only retains instructions in sequence
 Is much smaller in size and hence lower in cost
Loop Buffer
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Branch Prediction

 Various techniques can be used to predict whether a branch will be

taken:

1. Predict never taken

 These approaches are static
2. Predict always taken
 They do not depend on the execution
history up to the time of the conditional
3. Predict by opcode branch instruction

4. Taken/not taken switch  These approaches are dynamic

5. Branch history table  They depend on the execution history
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Branch Prediction
Flow Chart
Branch Prediction State Diagram
+ Summary Processor Structure and
Function
Chapter 14
 Instruction pipelining
 Processor organization
 Pipelining strategy
 Register organization  Pipeline performance
 User-visible registers  Pipeline hazards
 Control and status registers  Dealing with branches
 Intel 80486 pipelining
 Instruction cycle
 The indirect cycle  The Arm processor
 Data flow  Processor organization
 Processor modes
 The x86 processor family
 Register organization
 Register organization
 Interrupt processing
 Interrupt processing
+ Key terms Chapter 14

 flag
 condition code
 branch prediction
 instruction cycle
 instruction pipeline
 instruction prefetch
 program status word (PSW)
+ Homework
 14.1 2 3 4 7 8 9 10 11 13 16