Integrated Circuit
Integrated Circuit
Integrated Circuit
Ic 7473:
This device contains two independent positive pulse triggered J-K flip-flops with
complementary outputs. The J and K data is processed by the flip-flops after a complete clock
pulse. While the clock is LOW the slave is isolated from the master. On the positive
transition of the clock, the data from the J and K inputs is transferred to the master. While the
clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the
data from the master is transferred to the slave. The logic states of the J and K inputs must not
be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling
edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless
of the logic states of the other.
PIN LAYOUT:
FEATURES:
a) Two J-K Master/Slave Flip Flops in a 14-Pin DIP Package
b) Outputs Directly Interface to CMOS, NMOS and TTL
c) Large Operating Voltage Range
d) Wide Operating Conditions
e) Not Recommended for New Designs Use 74LS73
PIN DESCRIPTION:
Pin Number Description
1 Clock 1
2 Clear 1
3 K1 Input
5 Clock 2
6 Clear 2
7 J2 Input
8 Complement Q2 Output
9 Q2 Output
10 K2 Input
11 Ground
12 Q1 Output
13 Complement Q1 Output
14 J1 Input
DIMENSIONAL DRAWING:
TECHNICAL DATA:
ELECTRICAL CHARACTERISTICS:
SWITCHING CHARACTERISTICS:
at Vcc=5V,Ta=25oC