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    Cmos Circuit and Layout

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    Jayanth bemesetty
    Static CMOS circuits use complementary nMOS and pMOS transistor networks. They require 2n transistors for an n-input circuit. Power is only consumed during input transitions. Common gates include the inverter, NAND and NOR. More complex structures use AOI/OAI configurations with compact pull-up/down networks. Stick diagrams provide simplified layout representations, while actual layouts arrange transistors and wires on a grid.

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    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd

    Cmos Circuit and Layout

    Uploaded by

    Jayanth bemesetty
    70 views25 pages
    Static CMOS circuits use complementary nMOS and pMOS transistor networks. They require 2n transistors for an n-input circuit. Power is only consumed during input transitions. Common gates include the inverter, NAND and NOR. More complex structures use AOI/OAI configurations with compact pull-up/down networks. Stick diagrams provide simplified layout representations, while actual layouts arrange transistors and wires on a grid.

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    Static CMOS circuits use complementary nMOS and pMOS transistor networks. They require 2n transistors for an n-input circuit. Power is only consumed during input transitions. Common gates include the inverter, NAND and NOR. More complex structures use AOI/OAI configurations with compact pull-up/down networks. Stick diagrams provide simplified layout representations, while actual layouts arrange transistors and wires on a grid.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    70 views25 pages

    Cmos Circuit and Layout

    Uploaded by

    Jayanth bemesetty
    Static CMOS circuits use complementary nMOS and pMOS transistor networks. They require 2n transistors for an n-input circuit. Power is only consumed during input transitions. Common gates include the inverter, NAND and NOR. More complex structures use AOI/OAI configurations with compact pull-up/down networks. Stick diagrams provide simplified layout representations, while actual layouts arrange transistors and wires on a grid.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 25

    Static CMOS Circuits

    1
    Static CMOS Circuits

     In Static CMOS circuits with n inputs, 2n transistors


    are needed.
     nMOS block is a dual of the pMOS block.
     What ever is in series in nMOS, appears in parallel

    in pMOS and vice versa.


     CMOS gates consume power only during the
    transition of inputs.

    Ankur Agarwal 2
    Static complementary gate structure

    Pull-up and pull-down networks


    VDD

    pull-up
    network
    inputs out
    Pull-down
    network
    VSS

    Ankur Agarwal 3
    Pull-up/pull-down network design

     Pull-up and pull-down networks are duals.

     To design one gate, first design one network, then


    compute dual to get other network.

    Ankur Agarwal 4
    Static CMOS Circuits

     Static CMOS Logic Structure


     Logic Gates – Inverter, NAND and NOR
     Complex Structures
     AOI/OAI Structures
     Stick Diagrams
     Layouts

    Ankur Agarwal 5
    Inverter

    Ankur Agarwal 6
    NAND Gate

    Va Vb Vout
    0 0
    0 1
    1 0
    1 1

    Ankur Agarwal 7
    NOR2 Gate

    Va Vb Vout
    0 0
    0 1
    1 0
    1 1

    Ankur Agarwal 8
    Static CMOS Circuits

     Static CMOS Logic Structure


     Logic Gates – Inverter, NAND and NOR
     Complex Structures
     AOI/OAI Structures
     Stick Diagrams
     Layouts

    Ankur Agarwal 9
    Complex CMOS Structures

    Ankur Agarwal 10
    Xor gate

    Ankur Agarwal 11
    Static CMOS Circuits

     Static CMOS Logic Structure


     Logic Gates – Inverter, NAND and NOR
     Complex Structures
     AOI/OAI Structures
     Stick Diagrams
     Layouts

    Ankur Agarwal 12
    AOI/OAI gates

     AOI = and/or/invert; OAI = or/and/invert.


     Implement larger functions.
     Pull-up and pull-down networks are compact: smaller
    area, higher speed than NAND/NOR network
    equivalents.

    Ankur Agarwal 13
    AOI example

    invert

    or

    and

    Ankur Agarwal 14
    Problems

    A C

    B D
    Y
    A B

    C D

    Ankur Agarwal 15
    Problems

     Design a CMOS circuit to implement the logic


    Y = A'B' + B'C + C'A
     Make a 2 input CMOS XOR gate to implement
    Y = A  B.
     CMOS XOR and XNOR gates are similar. Just one of the
    input pairs (A and A' are reversed).

    Ankur Agarwal 16
    Static CMOS Circuits

     Static CMOS Logic Structure


     Logic Gates – Inverter, NAND and NOR
     Complex Structures
     AOI/OAI Structures
     Stick Diagrams
     Layouts

    Ankur Agarwal 17
    Stick diagrams

     A stick diagram is a cartoon of a layout.


     Does show all components/vias (except possibly tub
    ties), relative placement.
     Does not show exact placement, transistor sizes, wire
    lengths, wire widths, tub boundaries.

    Ankur Agarwal 18
    Stick Diagram of NOR gate

    Ankur Agarwal 19
    Dynamic latch

    Stores charge on inverter gate


    capacitance:

    Ankur Agarwal 20
    Dynamic latch stick diagram

    VDD

    in
    out

    VSS
    phi’ phi
    Ankur Agarwal 21
    Static CMOS Circuits

     Static CMOS Logic Structure


     Logic Gates – Inverter, NAND and NOR
     Complex Structures
     AOI/OAI Structures
     Stick Diagrams
     Layouts

    Ankur Agarwal 22
    Layout

    VDD

    D Q’

    VSS
     ’
    Ankur Agarwal 23
    Layout of NOR Gate

    Ankur Agarwal 24
    Stick Diagram of NAND gate

    Ankur Agarwal 25

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