Computer Organization and

Architecture
Chapter Four

BASIC COMPUTER ORGANIZATION AND DESIGN

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 Introduction
 In this chapter we introduce a basic computer and show how its operations can
be specified with RTL statements.
Every different processor type has its own design (different registers, buses,
micro operations, machine instructions, etc)
We will introduce processor organization and the relationship of the RTL
Instruction Codes
Computer Registers
Computer Instructions
Instruction Cycle
Design of Basic Computer
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4.1 Instruction Codes
Program: A set of instructions that specifies operation, operands,
and sequence of processing that has to occur, S/W = Program + Data
 The instructions of a program, along with any needed data are
stored in memory.
 The CPU reads the next instruction from memory.
 It is placed in an Instruction Register(IR)
 Control circuitry in control unit then translates the instruction
into the sequence of micro-operations necessary to implement it.

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Computer Instruction: A binary code that specifies a sequence of micro-
operations for the computer. Every computer has its own unique instruction code.
Instruction code: is a group of bits instructing the computer to perform a specific
operation. It is divided into parts, each with particular meaning.
I. Operation code(Opcode): the most important part of instruction code
 A group of bits that specify the “macro” operation to be performed by the
instruction. Example: add, subtract, multiply, shift, and complement.
 that specifies the operation for that instruction.
II. Operand(address): that specifies the registers or locations in memory to
use for that operation

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 The Basic Computer has two components, a processor and memory
 The operand part of the instruction has several different formats
depending on the number and type of operands.

In the Basic Computer, bit 15 of the instruction specifies

the addressing mode(0: direct addressing, 1: indirect
addressing)
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Number of Operands
• The number of operands per instruction is a basic design decision.
– Fewer operands per instruction result in simpler instructions
requiring a simpler CPU.
– It also results in instructions of shorter length.

– However, programs would contain more instructions. This

usually means longer execution time and larger more complex
programs.
• Most modern computers use a mix of two and three operand
instructions.

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 3-Operand Instructions

• Three operand instructions are not common because they require

large instruction formats.
– Instead, one of the operands plays the role of source and
destination at the same time.
ADD R1, R2, R3
R1 = R2 + R3

2-Operand Instructions
• Two operand instructions are the most common.
ADD R1, R2
R1 = R1 + R2

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1-Operand Instructions
• Single operand instructions are mainly used in
microprocessors where one of the source operands (and
the destination) is implicit.
• These computers use an “accumulator” as part of every
instruction.
ADD B => AC = AC + B

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Addressing modes:
• There are several types of operands that can be used with the
different instructions. These translate into the different addressing
modes.
• Immediate address :when the second part of the instruction code
specifies an operand.

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 Indirect address:
• when the second part specifies an address in a memory where we can find
the true address of the operand.

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 Effective Address

• The effective address is the real address where the input

data for the instruction resides.
• In a direct addressing mode instruction, the effective
address is the same as the address given in the operands
section of the instruction.
• In indirect addressing mode instructions, the effective
address needs to be calculated from the information given
in the instruction.

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Computer Registers
A processor has many registers
 to hold instructions after it has been fetched from memory,
 addresses of operands need to be accessed data manipulated with
accumulator,
 general purpose register, and others.

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There are four registers that are common to most CPUs:
Program Counter (PC)
- holds the memory address of the next instruction
- Always points to the next instruction.
- It is incremented after each instruction fetch.
- A call instruction causes the new address to be loaded into the PC.

Instruction Register (IR)

- Each fetched instruction goes into the IR.
- Then its opcode and operands are decoded to decide which operations are
to be executed.
- The instruction decoder connects to the IR.

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CPU With Systems Bus

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Address Register (AR):
- the processor needs to keep track of what locations in memory it is
addressing
- Connects directly to the CPU’s address bus.
- Addresses for memory references are placed in AR before the memory
reference is executed.

Memory Data Register (DR)

- DR holds memory operands
- Connects directly to the CPU’s data bus.
- Data to be sent to memory during a memory write operation is first
transferred into DR before the operation is executed.
- Data read during a memory read operation comes into DR, then it is
transferred to the internal general purpose register specified in the
instruction.

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Accumulator Register (AC):
 it is the general purpose processor register
 It holds one of the address of operand
 in Single-Address CPU to contain one of the
operand before operation and the result after
operation.

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Data transfer instructions

- Moves data from one place to another, without changing the data
contents. The most common transfer are between memory and
processor registers, between processor registers and IO, and between
processor register themselves.

- Load instruction is used to transfer data from memory to processor

register(s) (Accumulator).

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- Store instruction transfers data from register(s),(Accumulator) to
memory.

- Exchange instruction swaps data between 2 registers or between 2

memory locations.

- Input-Output instructions transfer data between processors and IO

device

- Push-Pop instructions transfer data between stack and registers

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 General Register Organization
- Intermediate data are needed to be stored like pointers, counters, return
address, temp results, and partial products during multiplications.
- Cannot save them in main memory because their access is time
consuming.
- It is more efficient and faster to be stored inside processor.
- So the solution is designing multiple registers inside processor and
connects them through a common bus.
- In Basic Computer, there is only one general purpose register, the
Accumulator (AC) but in modern CPUs, there are many general
purpose registers.
- It is advantageous to have many registers
- Transfer between registers within the processor are relatively fast
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Stack Organization
- Stack is a storage device that stores information in a way that
the item is stored last is the first to be retrieved (LIFO).
- Stack in computers is actually a memory unit with address
register (stack pointer SP) that can count only.
- SP value always points at top item in stack.
- The two operations done on stack are
• PUSH (Push Down), operation of insertion of items into
stack
• POP (Pop Up), operation of deletion item from stack
Those operation are simulated by INC and DEC stack register (SP).

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The next example shows 64- word register stack or location
stack unit with SP that stores address of the word that is
currently on the top of stack.

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Note that 3 items are placed in the stack A, B, and C.
Item C is in top of stack so that SP holds 3 which the address of
item C.

- To remove top item from stack (popping stack) we start

by reading content of address 3 and decrementing the
content of SP.

- Item B is now in top of stack holding address 2.

- To insert new item (pushing the stack) we start by

incrementing SP then writing a new word where SP
now points to (top of stack).
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Reverse Polish Notation

- Very useful notation to utilize stacks to evaluate arithmetic

expressions.

- the common mathematical method of writing arithmetic

expression imposes difficulties when evaluated by a
computer.

- The 3 notations to evaluate expressions

1. A + B Infix notation
2. +AB Prefix notation (Polish notation)
3. AB+ Postfix notation (reverse Polish notation)
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Reverse Polish Notation is in a form suitable for stack manipulation.
Starts by scanning expression from left to right.

- When operator is found then perform operation with 2 operands in

left of operator and replace result place of 2 operands and operator.

- Then you can continue this until you reach final answer.
Example
Expression A*B + C*D is written in RPN as AB*CD*+. And will
computed as
(A*B) CD *+
(A*B)(C*D)+

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Example
Convert infix notation expression (A + B)*(C * (D + E) + F) to
RPN?
AB+ DE+ C * F+ *.
Will be computed as (A+B) (D+E) C * F + *

Convert (3*4)+(5*6) to RPN

34*56*+

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 Implementation of Instruction Format

Zero address instruction:

Stack is used. Arithmetic operation pops two operands from the stack and pushes
the result.
One address instructions:
AC and memory. Since the accumulator always provides one operand, only one
memory address needs to be specified.
Two address instructions:
Two address registers or two memory locations are specified, one for the final result.

Three address instructions: Three address registers or memory locations are

specified, one for the final result.
It is also called general address organization.

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Zero address instructions

Instruction: ADD
Push and pop operations need to specify one address involved
in data transfer.

Stack-organized computer does not use an address field for the

instructions ADD, and MUL

Instruction: POP X
Evaluate X = ( A + B ) * ( C + D )

PUSH, and POP instructions need an address field to specify

the operand

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PUSH A TOS  A
PUSH B TOS  B
ADD TOS  ( A  B )
PUSH C TOS  C
PUSH D TOS  D
ADD TOS  (C  D )
MUL TOS  (C  D )  ( A  B )
POP X X  TOS

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One address instructions

One address can be a register name or memory address.

single accumulator organization
Since the accumulator always provides one operands, only
one memory address needs to be specified.
Instruction: ADD X
Micro operation: AC  AC + M[X]

LOAD A AC  M [ A ]
AC  AC  M [ B ]
ADD B
M [ T ]  AC
STORE T
All operations are done between the AC register and memory operand
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 Two address instructions
Assumes that the destination address is the same as that of
the first operand. Can be a memory address or a register
name.
Instruction: ADD R1, R2
MOV R1, A R1  M [ A]
Micro operation: R1  R1 + R2
MOV R2, B R 2  M [B ]
ADDR1, R2 R1  R1  R 2
M [ x]  R1
MOV X, R1

Each address fields specify either a processor register or a memory

operand

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 Three address organization

general register organization

Three address instructions: Memory addresses for the two operands
and one destination need to be specified.
Instruction: ADD R1, R2, R3
Micro operation: R1  R2 + R3

ADD R1, R2, R3 R1  R2  R3

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 Example: Show how can the following operation be performed using:

a. three address instruction

b. two address instruction
c. one address instruction
d. zero address instruction X = (A + B) * (C + D)

c.
b. LOAD A
a. MOV R1, A AC M[A]
ADD R1, A, B R1  M[A] ADD B
R1  M[A] + M[B] ADD R1, B AC  AC + M[B]
ADD R2, C, D R1  R1 + M[B] STORE T
R2  M[C] + M[D] MOV R2, C M[T ] AC
MUL X, R1, R2 R2  M[C] LOAD C
ADD R2, D AC  M[C]
M[X]  R1 * R2 R2  R2 + M[D] ADD D
MOV X, R2 AC  AC + M[D]
M[X] R2 MUL T
MUL X, R1 AC  AC * M[T ]
M[X]  R1 * M[X] STORE X
M[X]  AC Store
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d. Zero-address instructions
(stack organization)
Push value
Else If operator is encountered: Pop, pop, operation, push
Pop operand pop another operand then perform an operation and push the
result back into the stack.
PUSH A TOS  A Push
PUSH B TOS  B Pop, pop, operation, push
ADD TOS  (A+B)
PUSH C TOS  C
PUSH D TOS  D Pop, pop, operation, push
ADD TOS  (C+D)
MUL TOS  (C+D)*(A+B)
POP X M[X]  TOS
(*TOS stands for top of stack).

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INSTRUCTION CYCLE:

• In Basic Computer, a machine instruction is executed in the following cycle:

1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the instruction has an
indirect address
4. Execute the instruction
• After an instruction is executed, the cycle starts again at step 1, for the next
instruction
NB: Every different processor has its own (different) instruction cycle

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Example: Instruction cycle

• Add operation
ADD A, B
– Fetch the ADD instruction
– Decode the instruction
– Read content of memory location A into the processor
– Read content of memory location B into the processor
– Add the two values
– Write the result from processor to memory location A

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 Fetching the instruction

• Only AR is connected to the Address pins

– The instruction address (in PC) must be moved to
AR at the beginning of each fetch cycle.
• A memory read operation is then executed, and the PC is
incremented at the same time.
• The micro-operations that make up the fetch cycle are:
T0:MAR  PC
T1:IR  M[MAR], PC  PC + 1

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 Decoding the Instruction

• When cycle T1 is over, the instruction code read from memory is in IR.
– It needs to be decoded to determine what operations are to be done
next.
– Bits 12 – 14 of the instruction contain the instruction code.
– Bit 15 is the Direct/Indirect bit
– Bits 0 – 11 May carry the effective address or the operation
depending on the type of instruction.
– In Micro-operation form, this can be written as:
– T2: D0, …, D7  Decode IR(14-12), AR  IR(11-0), I 
IR(15)

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Input Output & Interrupts
– Computer must communicate with external device to receive and send
data with it.
– Instructions and data must come to computer from external input device.

– Computational result must be transmitted to user through an output

device.
– Input Output Configuration

– The terminal sends and receives 8 bit data converted to serial information
and receives serial information and convert it back to parallel 8 bits.

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– The serial info from the keyboard is received serially and
shifted into INPR.
– The serial info for the printer is stored in the OUTR and
converted to serial and sends to the printer.
Interrupt Initiated IO and Interrupt
– For slow device transfer it can be considered wasting a lot
of time (different data transfer rate between IO and
processor).
– The solution will be the device can interrupt and tell
processor when it wants to be served.
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Design of Basic Computer
 Hardware Components of Basic Computer should contain:
 A memory unit:
 Registers:
 Decoders:
 Common bus:
 Control logic gates:
 Adder and Logic circuit: Connected to AC

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 D!!
E N

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