UNIT – 3

BASIC COMPUTER
ORGANIZATION AND DESIGN
 Computer Registers
 Registers are a type of computer memory used to quickly accept,
store, and transfer data and instructions that are being used
immediately by the CPU.
 The registers used by the CPU are often termed Processor registers.
A processor register may hold an instruction, a storage address, or
any data (such as bit sequence or individual characters).
 The computer needs processor registers for manipulating data and a
register for holding a memory address.
 The register holding the memory location is used to calculate the
address of the next instruction after the execution of the current
instruction is completed.
Some of the commonly used registers are:
 AC ( accumulator )
 DR ( Data registers )
 AR ( Address registers )
 PC ( Program counter )
 MDR ( Memory data registers )
 IR ( index registers )
 MBR ( Memory buffer registers )
 Following is the list of some of the most common registers used in a basic
computer:
Register Symbol Number of Function
bits
Data register DR 16 Holds memory operand
Address register AR 12 Holds address for the memory
Accumulator AC 16 Processor register
Instruction register IR 16 Holds instruction code
Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character
Output register OUTR 8 Carries output character
BUS SYSTEM

A digital system composed of many registers, and paths must

be provided to transfer information from one register to
another.
 The bus is a communication channel.
 The characteristic of the bus is shared transmission media.
 The limitation of a bus is only one transmission at a time.
A bus that is used to provide communication between the
major components of a computer is called a System bus.
The system bus contains 3 categories of lines used to
provide the communication between the CPU, memory,
and IO named as:

1. Address lines (AL)

2. Data lines (DL)
3. Control lines (CL)
The following block
diagram shows a Bus
system for four
registers. It is
constructed with the
help of four 4 * 1
Multiplexers each
having four data
inputs (0 through 3)
and two selection
inputs (S1 and S2).
The following function table shows the register that is
selected by the bus for each of the four possible binary
values of the Selection lines.
 Computer can be instructed about the specific sequence of
operations it must perform.

 User controls this process by means of a Program.

 Program: a set of instructions that specify the operations,

operands, and the sequence by which processing has to occur.

 Instruction: a binary code that specifies a sequence of micro-

operations for the computer.
• The computer reads each instruction from memory and
places it in a control register.

• The control then interprets the binary code of the instruction

and proceeds to execute it by issuing a sequence of micro-
operations. – Instruction Cycle
INSTRUCTION CYCLE
A program residing in the memory unit of a computer consists of a
sequence of instructions.
 These instructions are executed by the processor by going through a
cycle for each instruction.
 In a basic computer, each instruction cycle consists of the following
phases:
 Fetch instructions from memory.
 Decode the instruction.
 Read the effective address from memory/It can read the effective
address from memory if the instruction has an indirect address.
 Execute the instruction.
INSTRUCTION CYCLE
• Instruction Code: a group of bits that instruct the
computer to perform a specific operation.

• Instruction code is usually divided into two parts: Opcode

and address(operand)
Operation Code (opcode):

 Group of bits that define the operation

 Eg: add, subtract, multiply, shift, complement.

 No. of bits required for opcode depends on no. of operations

available in the computer.
ADDRESS (OPERAND):

 Specifies the location of operands (registers or memory

words)

 Memory words are specified by their address

STORED PROGRAM ORGANIZATION:
 Theability to store and execute instructions is the most
important property of a general-purpose computer.
 Thattype of stored program concept is called stored program
organization.
 The simplest way to organize a computer is to have one
processor register and an instruction code format with two
parts.
 Thefirst part specifies the operation to be performed and the
second specifies an address.
THE BELOW FIGURE SHOWS THE STORED PROGRAM
ORGANIZATION
4096 = 212
• 12 bits to specify memory
• 4 bits for opcode
Accumulator (AC):
• Computers that have a single-
processor register usually
assign to it the name
accumulator and label it AC.
• The operation is performed
with the memory operand and
the content of AC.
Addressing of Operand:
• Sometimes convenient to use the address bits of an instruction
code not as an address but as the actual operand.
• When the second part of an instruction code specifies an
operand, the instruction is said to have an immediate operand.
• When the second part specifies the address of an operand, the
instruction is said to have a direct address.
 When the second part of the instruction designates an address of a memory
word in which the address of the operand is found such instruction has an
indirect address.
 One bit of the instruction code can be used to distinguish between a direct
and an indirect address.
 The instruction code format is shown in Fig. 5-2(a).
 It consists of a 3-bit operation code, a 12-bit address, and an indirect
address mode bit designated by I.
 The mode bit is 0 for a direct address and 1 for an indirect address.
ADDRESSING
OF OPERAND
• A direct address instruction is shown in Fig. 5-2(b).
• It is placed in address 22 in memory.
• The I bit is 0, so the instruction is recognized as a direct address
instruction.
• The opcode specifies an ADD instruction, and the address part is
the binary equivalent of 457.
• The control finds the operand in memory at address 457 and
adds it to the content of AC.
• The instruction in address 35 shown in Fig. 5-2(c), has a mode
bit I = 1.
• Therefore, it is recognized as an indirect address instruction.
• The address part is the binary equivalent of 300.
 Thecontrol goes to address 300 to find the address of the
operand.
 The address of the operand in this case is 1350.
 Theoperand found in address 1350 is then added to the content
of AC.
 Theeffective address is to be the address of the operand in a
computation-type instruction or the target address in a branch-
type instruction.
 Thus the effective address in the instruction of Fig. 5-2(b) is 457
and in the instruction of Fig 5-2(c) is 1350.
MEMORY REFERENCE
What are Memory Reference Instructions?
 Memory reference instructions are those commands or
instructions which are in the custom to generate a reference to
the memory and approval to a program to have an approach to
the commanded information that states from where the data is
cached continually.

 These instructions are known as Memory Reference

Instructions.
THERE ARE SEVEN MEMORY REFERENCE
INSTRUCTIONS WHICH ARE AS FOLLOWS
1. AND to AC

The AND instruction implements the AND logic operation on the

bit collection from the register and the memory word that is
determined by the effective address.

 The result of this operation is moved back to the register.

 D0T4: DRM[AR]

 D0T5: AC AC ^ DR, SC 0

2. ADD to AC
The ADD instruction adds the content of the memory
word that is denoted by the effective address to the value
of the register.

 D1T4: DRM[AR]

 D1T5: AC  AC + DR, E  Cout, SC  0

3. LDA – Load to AC
The LDA instruction shares the memory word denoted
by the effective address to the register.
• D2T4: DR  M[AR]
• D2T5: AC  DR, SC  0
4. STA - Store AC
• STA saves the content of the register into the memory
word that is defined by the effective address.
• The output is next used to the common bus and the data
input is linked to the bus.
• It needed only one micro-operation.

D3T4: M[AR]  AC, SC  0

5. BUN - Branch Unconditionally
 The Branch Unconditionally (BUN) instruction can send the
instruction that is determined by the effective address.
 They understand that the address of the next instruction to be
performed is held by the PC and it should be incremented by one
to receive the address of the next instruction in the sequence.
 Ifthe control needs to implement multiple instructions that are not
next in the sequence, it can execute the BUN instruction.
D4T4: PC  AR, SC  0
6. BSA - Branch and Save Return Address
• BSA stands for Branch and Save return Address.
• These instructions can branch a part of the program
(known as subroutine or procedure).
• When this instruction is performed, BSA will store the
address of the next instruction from the PC in a memory
location that is determined by the effective address.
M[AR]  PC, PC  AR + 1
M[135] 21, PC 135 + 1 = 136
6. BSA - Branch and Save Return Address
• It is not possible to perform the operation of the BSA
instruction in one clock cycle when we use the bus system of
the basic computer.

• To use the memory and the bus properly, the BSA

instruction must be executed with a sequence of two
microoperations:
D5T4: M[AR]  PC, AR  AR + 1
D5T5: PC  AR, SC  0
7. ISZ - Increment and Skip if Zero
• The Increment if Zero (ISZ) instruction increments the word
determined by effective address.
• If the incremented cost is zero, thus PC is incremented by 1.
• A negative value is saved in the memory word through the
programmer.
• It can influence the zero value after getting incremented
repeatedly. Thus, the PC is incremented and the next instruction is
skipped.
D6T4: DR  M[AR]
D6T5: DR  DR + 1
D6T4: M[AR]  DR, if (DR = 0) then (PC  PC + 1), SC  0
TIMING AND CONTROL
 The timing for all registers in the basic computer is controlled by
a master clock generator.
 The clock pulses are applied to all flip-flops and registers in the
system, including the flip-flops and registers in the control unit.
 The clock pulses do not change the state of a register unless the
register is enabled by a control signal.
 The control signals are generated in the control unit and provide
control inputs for the multiplexers in the common bus, control
inputs in processor registers, and micro operations for the
accumulator.
INPUT-OUTPUT AND INTERRUPT
 A computer can serve no useful purpose unless it communicates with the
external environment. Instructions and data stored in memory must come
from some input device.

 Computational results must be transmitted to the user through some output

device

 Commercial computers include many types of input and output devices.

 To demonstrate the most basic requirements for input and output

communication, we will use as an illustration a terminal unit with a keyboard
and printer.
 INPUT-OUTPUT AND INTERRUPT

A Terminal with a keyboard and a Printer

• Input-Output Configuration
Input-output Serial Computer
terminal communication registers and
interface
flip-flops
INPR Input register - 8 bits Printer
Receiver
OUTR FGO
interface
OUTR Output register - 8 bits
FGI Input flag - 1 bit
FGO Output flag - 1 bit AC
IEN Interrupt enable - 1 bit
Transmitter
Keyboard interface INPR FGI

Serial Communications Path

Parallel Communications Path
- The terminal sends and receives serial information
- The serial info. from the keyboard is shifted into INPR
- The serial info. for the printer is stored in the OUTR
- INPR and OUTR communicate with the terminal
serially and with the AC in parallel.
- The flags are needed to synchronize the timing
difference between I/O device and the computer
PROGRAM CONTROLLED DATA TRANSFER
-- CPU -- -- I/O Device --
loop: If FGI = 0 goto loop /* Input */ /* Initially FGI = 0 */
AC  INPR, FGI  0 loop: If FGI = 1 goto loop
INPR  new data, FGI  1
/* Output */ /* Initially FGO = 1 */
loop: If FGO = 0 goto loop
OUTR  AC, FGO  0 loop: If FGO = 1 goto loop
consume OUTR, FGO  1
FGI=0 FGO=1
Start Input Start Output

yes yes
FGI=0
FGO=1
no
no
AC  INPR
Consume OUTR
yes FGO  1
FGI  0

More yes More

Character Character
no no
END END
Interrupt Flowhart – refer notes
 INTERCONNECTION STRUCTURES
A computer consists of a set of components or modules of
three basic types (processor, memory, I/O) that
communicate with each other.
 In effect, a computer is a network of basic modules. Thus,
there must be paths for connecting the modules.
 The collection of paths connecting the various modules
is called the interconnection structure.
 The design of this structure will depend on the
exchanges that must be made among modules.
BUS INTERCONNECTION

 A bus is a communication pathway connecting two or more devices.

 A key characteristic of a bus is that it is a shared transmission medium.

 Multiple devices connect to the bus, and a signal transmitted by any one
device is available for reception by all other devices attached to the bus.

 If two devices transmit during the same time period, their signals will
overlap and become garbled. Thus, only one device at a time can
successfully transmit.
BUS STRUCTURE
 The data lines provide a path for moving data among
system modules. These lines, collectively, are called the
data bus.
 The address lines are used to designate the source or
destination of the data on the data bus.
 The control lines are used to control the access to and the
use of the data and address lines.
THANK YOU