M 05 BIST0504

Memory Built-In Self-Test
Cheng-Wen Wu 吳誠文
Lab for Reliable Computing

Dept. Electrical Engineering
National Tsing Hua University
Outline
• Introduction
• ROM BIST
• RAM BIST approaches
• RAM BIST architectures
− Typical MBIST architectures
− March-programmable MBIST
− Processor-programmable MBIST
• BRAINS: a RAM BIST compiler
• Conclusions
m05bist5.04 Cheng-Wen Wu, NTHU 2

Memory Cores on SOC
• Embedded memories are among the most
common cores in SOC
• How to test embedded memories?
CPU DSP
Bus/IO SRAM
ROM
DRAM Flash

Embedded Memory Testing
• Memories are one of the most universal cores
− In Alpha 21264, cache RAMs represent 2/3
transistors and 1/3 area; in StrongArm SA110, the
embedded RAMs occupy 90% area [Bhavsar, ITC-99]
− In average SOC, memory cores will represent more
than 90% of the chip area by 2010 [ITRS 2000]
• Embedded memory testing is increasingly difficult
− High bandwidth (speed and I/O data width)
− Heterogeneity and plurality
− Isolation (accessibility)
− AC test, diagnostics, and repair
• BIST is considered the best solution

ROM BIST Architecture
Controller Status Pattern Generator
Address
Delay ROM
Data
Go/No-Go Status Signature Analyzer

Pattern Generator
• Counter or LFSR/PRPG
D0 D1
… Dn

Signature Analyzer
• Based on MISR (or CRC)

− 24 or 32 bits
I0 I1 In
D0 D1 … Dn

Experimental Results
• Typical 0.35um CMOS Cell Library
ROM size 256x8 2048x8 2048x64 4096x32

BIST gate count 436 455 930 561
Clock Period (ns) 2.44 2.8 3.46 3.51
Test Time 267 2059 2115 4131
(clock cycles)

ROM BIST Area Overhead
• Typical 0.35um CMOS Cell Library
ROM size 256x8 2048x8 2048x64 4096x32

BIST Area (B) 38,180 39,844 81,440 49,126
ROM Area (R) 49,396 143,668 631,222 626,076
B/R (%) 77.3 27.7 13 7.8
•Area is in um2
•BIST logic can be shared

Exercise
1. If the word length is 16, how do you design the
signature analyzer based on 24-bit MISR?
2. If the word length is 40, how do you design the
signature analyzer based on 24-bit MISR?
3. How do you perform diagnosis under the MISR-
based ROM BIST scheme? Do you have a better
ROM BIST approach so far as diagnosis is
concerned?
4. How do you deal with multiple heterogeneous
ROM cores (considering test time and hardware
cost)?
5. How do you perform diagnosis under the BIST
scheme?
ROM Physical Structure
• ROM bit cell is much smaller than SRAM cell
− Wire pitch is too small for decoder logic to fit into the same
pitch as the bit cells
• Row/column decoders may be twice as wide as a bit cell
Row Decoder
Exercise: Wordsize
1. Does the physical structure 6 7

ROM
affect the ROM BIST circuit Block 0
design?
4 5
2. Do you think address or
data scrambling is 2 3
necessary?
0 1
3. Can you test PLA/PAL in a Column
similar way? Read
1 3 5 7 Logic
4. How do you reduce test
time by exploring possible 0 2 4 6
parallelism?
Source: Cadence
Embedded RAM Test Support
Test run Isolation only Isolation & BIST

Probe test Tester Tester/BIST
Pre-BI test Tester BIST
BI BI board BIST
Post-BI test Tester BIST
Final test Tester Tester/BIST

What Can BIST do?
• What are the functional faults to be covered?
− Static and dynamic
− Operation modes
• What are the defects to be covered?
− Opens, shorts, timing parameters, voltages, currents, etc.
• Can it support fault location and redundancy repair?
• Can it support BI?
• Can it support on-chip redundancy analysis and repair?
• Does it allow characterization test as well as mass
production test?
• Can it really replace ATE (and laser repair machine)?
− Programmability, speed, timing accuracy, threshold range,
parallelism, etc.

How Is BIST Done?
BIST RAM
Ö Can it be a processor or RAM controller?

Typical RAM BIST Approaches
• Methodology
− Processor-based BIST
∗ Programmable
− Hardwired BIST
∗ Fast
∗ Compact
− Hybrid
• Interface
− Serial (scan, 1149.1)
− Parallel (embedded controller; hierarchical)
• Patterns (address sequence)
− March & March-like
− Pseudorandom
− Others
Typical RAM BIST Architecture
Controller
Test Collar (MUX)

Pattern
RAM
Generator
Comparator
Go/No-Go
BIST Module
RAM Controller

Test Collar

Serial March (SMarch)
{⇑ ( r x w 0 ) c ( r 0 w 0 ) c ; ⇑ ( r 0 w1) c ( r1w1) c ; ⇑ ( r1w 0 ) c ( r 0 w 0 ) c ;
⇓ ( r 0 w1) c ( r1w1) c ; ⇓ ( r1w 0 ) c ( r 0 w 0 ) c ; ⇓ ( r 0 w 0 ) c ( r 0 w 0 ) c }
• From March C-
• Serial interface
X Decoder
• One BIST for many Memory Cell Array
RAMs (cascaded)
• One-bit read/write at a
time, but one pattern
(word) per cycle Addr Y Decoder
• Slow SI Transparent Serial Data-MUX SO
• No diagnostics c
c
D Q
Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990

Serial Testing of Embedded RAM
Go
BIST mode Done
Control Block
Timing
Counters Generator
BIST on
S0 S1
msb
Mission Control Read/Write
mode
interface { Data out
Data in
Address
1sb
c-1
Clock
Multiplexers Multiplexers Multiplexers

log2W c c 2
Address Data In Data Out Control

RAM
(w words c bits)

Overhead of Serial Testing
Ratio of Test
RAM Total BIST BIST to
Chip Configuration Bits Circuits Chip Area Time
1 1 X 64 X 32 (S) 2,048 1 1.8% 25 ms
2 1 X 512 X 10 (D) 7,680 2 3.4% 200 ms

1 X 512 X 5 (S)
3 2 X 512 X 8 (S) 25,600 2 4.3% 400 ms

2 X 512 X 16 (D)
2 X 64 X 8 (D)

Syntest MBIST
• Algorithms:
CE
− March C-
FSM OE
− MOVI
WEB
− March C++
− Checkerboard
ADR Control A
• Shared controller
for multiple RAMs
• Synthesizable RTL Data Generator D
code
Pass
BistFail Analyzer Q
Finish
Source: Syntest, 2000

NTHU/GUC EDO DRAM BIST

DRAM Page-Mode Read-Write Cycle

Programmable Memory BIST (PMBIST)

PMBIST Architecture

PMBIST External I/O
• MBS (Memory BIST Selection): controller test collar
(normal/test mode selection)
• MBC (Memory BIST Control): Controller input
• MCK (Memory BIST Clock)
• MBR (Memory BIST Reset)
• MSI (Memory BIST Scan In): for test commands and scan
test inputs
• MSO (Memory BIST Scan Out): for diagnostic data and
scan test outputs
• MBO (Memory BIST Output): error indicator
• MRD (Memory BIST Output Ready): BIST completion flag

PMBIST I/O Summary

Controller and Sequencer
• Controller
− Microprogram
− Hardwired
− Shared CPU core
− IEEE 1149.1 TAP
− PLD
• Sequencer (Pattern Generator)

− Counter
− LFSR
− LUT
− PLD

Controller

Sequencer
D Q D Q
Combination Logic #0
D Q D Q
Combination Logic #1
BIST Row Address Counter

D Q D Q
Controller eDRAM
Column Address
D Q D Q
Counter
eDRAM
Control Counter
control
State signal
Flags
MCK MCK
Comparator

Disable
Sequencer States
BIST_EN=low
SEQ_EN=low
All outputs and
flags are high-z
Idle& Wait
BIST_EN=high
SEQ_EN=low
All outputs and
flags are in
precharged
state
Reset/Initiate CBR Refresh

BIST_EN=high
SEQ_EN=high
All outputs and
flags seted to
known state
NON_EDO NON_EDO
Self
A B EDO_ROW EDO_ROW EDO_ROW
Refresh
WD RDWD'
EDO_COL EDO_COL EDO_COL

0 1 2
WD RDWD' RDWD'RD'
Done &
Change
Command

BIST Interface Example
MCK MSI MSO MBS MBR MBO MRD MBC
PMBIST
xRas xCash xCasl Addr xWe D Q
Courtesy Global UniChip Co. (GUC).

Exercise
1. The BIST circuit is a synchronous sequential
circuit, but the EDO DRAM is asynchronous.
How can the BIST circuit generate waveforms
satisfying the timing specifications of the EDO
DRAM?
2. How does it cover data retention fault?
3. The BIST circuit supports March tests, which are
good for static functional faults. How can we
improve it so that dynamic (timing) faults can be
covered?
4. How does it support diagnostics, burn-in (BI),
and redundancy repair?

PMBIST Test Modes
1. Scan-Test Mode
2. RAM-BIST Mode
1.Functional faults
2.Timing faults (setup/hold times, rise/fall times,

etc.)
3.Data retention faults
3. RAM-Diagnosis Mode
4. RAM-BI Mode

PMBIST Controller Commands
Bit 4 Bit 3 Bit 2, Bit 1, Bit 0

Addressing order Data type Operations
1: ⇑ (increasing) 1: d = DB 000: EOT (End of test)
0: ⇓ (decreasing) 0: d = ~DB 001: Rd (READCycle)
010: Wd (Early WRITE Cycle)
011: RdW~d (READ-WRITE) Cycle
EDO-PAGE-MODE
100: Wd (Early WRITE Cycle
101: RdW~d (READ-WRITE) Cycle
110: RdW~dR~d (READEarly WRITE Cycle)
111: Refresh

PMBIST Control Sequence

BIST Area Overhead
3%
Overhead
Mem size
0.3%

Processor-Based RAM BIST
Processor
On-Chip Processor-Based RAM BIST
• BIST program is stored in boot ROM during
design phase, and memory BIST is done by
executing BIST program
Address DATAI DATAO Control
bus bus bus bus
BOOT
ROM
Embedded
memory
CPU core
I/O port

Testing RAM Core by On-Chip CPU
• 6502 assembly program that performs March C-
test algorithm
data background
.org 0HFF00
LDX #$$00 write data background to memory
LDA #$$55
March C- algorithm
M0: STA 0000,X
INX
Ï(W0)
CPX #$$FF Ï(R0W1)
BNE M0
LDX #$$00 Ï(R1W0)
M1: LDA 0000,X Ð(R0W1)
CMP #$$55
BNE ERROR Ð(R1W0)
LDA #$$AA
STA 0000,X Ï(R0)
INX
CPX #$$FF
read from memory
BNE M1
LDX #$$00
. . . . . write data background to memory

Test Speed Consideration
• Processor-BIST speed is lower than dedicated
BIST circuit
• Total clock cycles to implement MARCH C- is
O(114N)
Table 1. 6502 instruction cycles
IMM ABX IMP REL

LDA 2 4 - -
LDX 2 - - -
STA - 4 - -
INX - - 2 -
CPX 2 - - -
BNE - - - 2~4
CMP 2 - - -

Exercise
1. What are the limitations of processor-based
memory test?
2. Can the processor be used for diagnostics, too?
3. Has the instruction set anything to do with the
following?
1. Performance (test time)
2. Fault coverage
4. How do you test memories that are not

connected to the same bus, or those embedded
in other cores?

Processor-Based BIST Controller
Processor

NTHU Processor-Programmable BIST
ADDR_cpu ADDR
0
A
1
DATAO_cpu DATAO
0
ADDR_bist DI
on-chip bus
1
DATAO_bist
embedded clock_cpu
BIST core embedded
CPU mux_sel
ctrl_bist
memory
control
1
ctrl_cpu control
0
1 DATAI_bist DATAI_sys DATAI

0
DATAI_cpu DO
BIST circuitry
mux_sel = 0 in normal mode I/O circuitry
mux_sel = 1 in BIST mode
Ref: ASP-DAC01

Advantages and Disadvantages
• Advantages
− Reuse of on-chip CPU core
∗ Might need modification
− Core March elements can be implemented in
hardware, allowing different March algorithms to be
executed via assembly programming
• Disadvantages
− Some address space will be occupied by PPBIST
− Area overhead

PPBIST Implementation
DATAO_cpu
DATAO_bist
RBG
lowest / highest address
RAL ADDR_bist
ADDR_cpu address counter
address RAH REA
decoder
up / down read / write
RME RFLAG
control
RIR RED controller
match / unmatch
DATAI_bist DATAI_sys
comparator
data background

PPBIST Data Registers
Register Function
R BG Store background data
R AL Store lowest address
R AH Store highest address
R ME Store current March element
R IR Instruction register
R FLAG Status register
R ED Erroneous response of defective memory cell
R EA Address of defective memory cell

PPBIST Test Procedure
CPU write data background
CPU write start/stop address
CPU write MARCH element instruction
CPU write START instruction to wrapper
BIST core BIST core BIST core BIST core BIST core BIST core
Ï(W0) Ï(R0W1) Ï(R1W0) Ð(R0W1) Ð(R1W0) Ï(R0)
yes write error flag

compare error?
write faulty address
no write faulty data
no
complete?
yes
write complete flag CPU take over

PPBIST Example Using 6502
• 6502 assembly program that performs March C-
test algorithm under the proposed BIST scheme
START: LDA #$$55 END: LDA #$$04
STA 0HFFE0 STA 0HFFE6
LDA #$$00 JMP FINISH
STA 0HFFE1
LDA #$$00 BIST: LDA #$$00
STA 0HFFE2 STA 0HFFE6
LDA #$$FF LOOP: LDA 0HFFE7
STA 0HFFE3 CMP #$$01
LDA #$$0F BEQ ERROR
STA 0HFFE4 CMP #$$FF
M0: LDA #$$00 BNE LOOP
STA 0HFFE5 RTS
JSR BIST
ERROR: LDA #$$03
M1: LDA #$$01 STA 0HFFEA
. . . . . . JMP FINISH

PPBIST Example
• Addresses of the registers in the BIST experiment
R e g is te r A d d re s s R e g is te r A d d re s s
R BG FFE0 R IR FFE6
R AL FFE1 ~ FFE2 R FLAG FFE7
R AH FFE3 ~ FFE4 R ED FFE8
R ME FFE5 R EA FFE9 ~ FFEA
• March elements and the corresponding RME

M0 M1 M2 M3 M4 M5
0H 1H 2H 3H 4H 5H

• Total test time in terms of clock cycles
− The sum of all the March elements' test time plus
30 clock cycles
− 10N clock cycles to perform March C-
• Test time of each March element:
M0 M1 M2 M3 M4 M5
1N 2N 2N 2N 2N 1N

Comparison of BIST Methodologies
BIST scheme Test time H/W overhead Routing overhead
Integrated BIST core Short Low High
On-chip processor Very long Zero Zero
Ours Short Very low zero

Exercise
1. The CPU has to run the test program. Where
does it store the test program? Does the
processor-based RAM BIST approach have the
same issue?
2. Can the processor be used for diagnostics, too?
3. Has the instruction set anything to do with the
following?
1. Performance (test time)
2. Fault coverage
4. How do you test memories that are not
connected to the same bus, or those embedded
in other cores?

RAM BIST Compiler
• Use of RAM cores is increasing
− SRAM, DRAM, flash RAM
− Multiple cores
• RAM BIST compiler is the trend
• BRAINS (BIST for RAM in Seconds)
− Proposed BIST Architecture
− Memory Modeling
− Command Sequence Generation
− Configuration of the Proposed BIST

BRAINS Output Specification
• Synthesizable BIST design
− At-speed testing
− Programmable March algorithms
− Optional diagnosis support
∗ BISD
• Activation sequence
• Test bench
• Synthesis script

BRAINS Inputs and Outputs

BIST Synthesis Flow
Memory
GUI
Library
RTL
Compile
RAM/BIST Engine
Synthesis Netlist
Description
Parser
BIST Cell
Template Library

NTHU/GUC PMBIST Architecture
Programmable Memory BIST
MCK
MBS
MBC Controller Sequencer TPG
MBR
Controls
MSI
Test Collar
MSO
Address
MRD
Comparator
MBO Memory
D
Normal
Access

PMBIST with Scan
Test Comm and/Information Storage
M odule
Serial Serial
data in data out
M emory
Comm and Comm and
To
BIST Hand- Test M emory
control Controller shaking Sequencer Address Pattern
signals Generator
Error Error
Source: Cheng, et al., DFT00

State Diagram of Control Module
BIST
idle
BIST
idle
BIST BIST
done active
BIST BIST
done apply
BIST
apply
For SRAM For DRAM

Sequencer Block Diagram
March element
address
en Address Generator
done
Control
Sequence Generator
Module
go command
Command Generator
error go
info.
Error Handling Module error
signature

Function of the TPG
BIST
Controller Sequencer TPG RAM
• The test pattern generator (TPG) translates high-

level memory commands to memory input signals
• Four parameters to model a memory’s I/Os
− Type: input, output, and in/out
− Width
− Latency: number of clock cycles the TPG generates the
physical signal after it receives a command from the
sequencer
− Packet_length: number of different signal values packed
within a single clock cycle

Architecture of the TPG

DRAM Page-Mode Operation

Memory Specification Techniques
¾ Memory Specifications
¾I/O Specification
¾Command Specification
¾Task Specification
¾Delay Constraint Specification
¾AC Parameter Specification
¾ Support customized memories

I/O Specification
¾ Four parameters
¾ IO_type
¾ IO_width
¾ IO_latency
¾ IO_packet_length
¾ IO_type: input, output, or inout
¾ IO_width: port width (#bits), can be a constant
or specified by user

I/O Specification
• IO_latency: port latency

I/O Modeling
• IO_packet_length: #bits packed within a clock
cycle for the port

Command Specification
• Specifies the memory’s instructions

Task Specification
• Specifies a complete memory operation
• A task can be a single command or a sequence
of commands

Delay Constraint Specification
• Specifies the minimal time interval between any
two tasks

AC Parameter Specification
• Specifies input and output delays
• Specified parameters will be inserted into the
synthesis script

Memory Specification Example
• Zero-Bus Turnaround (ZBT) SRAM:
− A synchronous-burst SRAM with no bus latency
− Method A:
∗ @latency D = 1;
∗ @task write = {write};
− Method B:
∗ @latency D = 0;
∗ @task write = {pre_write, post_write};
• The BIST circuit from method A is faster than
the one from method B, but it has higher area
overhead

Sequence Generation
• For each March element, the compiler generates
the command sequence according to the read
task, write task, and minimum delay between the
two tasks
• For example:
− task read = {A}
− task write = {B, C}
− minimum delay between read and write = 10ns
− clock period = 10 ns
− Then the (rw) element becomes {A, nop, B, C}
• One can also optimize the command sequence

Fast Access Mode

Diagnosis Support
• The BIST circuit scans out the error information
(element, address, signature, and polarity) during
the diagnosis mode
• Assume address 20d stuck-at 64h:

Multiple RAM Cores
• Controller and sequencer can be shared
Test pattern
Ram Core A
generator
sequencer
Test pattern
generator Ram Core B
controller
Test pattern
sequencer Ram Core C
generator

Sharing Controller & Sequencer

Grouping and Scheduling

BRAINS BIST Architecture
External Tester
MBS MSI MBO MRD MSO MBC MBR MCK

Controller
Memory
BIST
Sequencer Sequencer Sequencer
TPG TPG TPG TPG TPG TPG
RAM RAM RAM RAM RAM RAM
Source: ATS’01
BRAINS GUI

Supported Memories
• The Built-In Memory List
− DRAM
∗ EDO DRAM
∗ SDRAM
∗ DDR SDRAM
− SRAM
∗ Single-Port Synchronous SRAM
∗ Single-Port Asynchronous SRAM
∗ Two-Port Synchronous Register File
∗ Dual-Port Synchronous SRAM
∗ Micron ZBT SRAM
• BRAINS can support new memory architectures
easily


Area Overhead

Case 1
• Four single-port SRAM BIST circuits share the same
controller and sequencer
• Size of the SRAM core: 8K x 16
Original Shared
BIST area for single-port Gate count: 3350
SRAM: 1438 (gates)
Total area = 1438 * 4 =
5752 (gates)

Case 2
• 8K x 16 single-port synchronous SRAM (0.25um)
• Area:
− Die size: 1780.74 x 755.07 um2
− BIST area: 80.1 x 583.48 um2
− Area overhead : 3.4%

Case 3
• 2K x 32 two-port register file (0.25um)
− Die size: 1130.74 x 936.34 um2
− BIST area: 77.88 x 620 um2
− Area overhead: 4.5%

Case 4
• Serial test: 1,641,472 clock cycles
• Proposed test time: 667,648 clock cycles
(59% reduced)
Memory BIST (um2) Memory Over-
Config. Ctrl. Seq. TPG Total (um2) head
16k X 32 11905.44
12k X 24 9443.30
8k X 64 23099.77
4541.96 6514.75 107378 5301800 2.025%
4k X 128 41389.96
1k X 8 3930.25
512 X 16 6530.03

Memory and Logic BIST
Source: Genesys
Conclusions
• BIST is considered the best solution for testing
embedded memories
− Low cost
− Effective and efficient
• Further improvement can be expected to extend
the scope of RAM BIST:
− Timing/delay faults and disturb faults
− BISD and BISR
− CAM BIST and flash BIST
− BIST/BISD/BISR compiler
− Wafer-level BI and test
∗ Known good die

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Memory Built-In Self-Test

Lab for Reliable Computing

m05bist5.04 Cheng-Wen Wu, NTHU 2

m05bist5.04 Cheng-Wen Wu, NTHU 3

m05bist5.04 Cheng-Wen Wu, NTHU 4

Controller Status Pattern Generator

Go/No-Go Status Signature Analyzer

m05bist5.04 Cheng-Wen Wu, NTHU 5

m05bist5.04 Cheng-Wen Wu, NTHU 6

• Based on MISR (or CRC)

m05bist5.04 Cheng-Wen Wu, NTHU 7

ROM size 256x8 2048x8 2048x64 4096x32

m05bist5.04 Cheng-Wen Wu, NTHU 8

ROM size 256x8 2048x8 2048x64 4096x32

m05bist5.04 Cheng-Wen Wu, NTHU 9

1. Does the physical structure 6 7

Test run Isolation only Isolation & BIST

m05bist5.04 Cheng-Wen Wu, NTHU 12

m05bist5.04 Cheng-Wen Wu, NTHU 13

Ö Can it be a processor or RAM controller?

m05bist5.04 Cheng-Wen Wu, NTHU 14

Test Collar (MUX)

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Multiplexers Multiplexers Multiplexers

Address Data In Data Out Control

Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990

m05bist5.04 Cheng-Wen Wu, NTHU 19

1 1 X 64 X 32 (S) 2,048 1 1.8% 25 ms

2 1 X 512 X 10 (D) 7,680 2 3.4% 200 ms

3 2 X 512 X 8 (S) 25,600 2 4.3% 400 ms

Source: Nadeau-Dostie et al., IEEE D&T, Apr. 1990

m05bist5.04 Cheng-Wen Wu, NTHU 20

Source: Syntest, 2000

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m05bist5.04 Cheng-Wen Wu, NTHU 27

• Sequencer (Pattern Generator)

m05bist5.04 Cheng-Wen Wu, NTHU 28

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BIST Row Address Counter

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Reset/Initiate CBR Refresh

EDO_COL EDO_COL EDO_COL

m05bist5.04 Cheng-Wen Wu, NTHU 31

xRas xCash xCasl Addr xWe D Q

Courtesy Global UniChip Co. (GUC).

m05bist5.04 Cheng-Wen Wu, NTHU 32

m05bist5.04 Cheng-Wen Wu, NTHU 33

2.Timing faults (setup/hold times, rise/fall times,

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Bit 4 Bit 3 Bit 2, Bit 1, Bit 0

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