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    DataPath Design

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    Oliver Barrina Jaguines
    The document discusses the stages and components of a datapath design for a microprocessor, including instruction fetch, decode, execution, memory access, and register write stages. It describes the functional units needed like the program counter, instruction memory, ALU, registers, and buses to route data. The instruction fetch stage fetches instructions from memory and increments the PC. The decode stage gathers instruction fields. The ALU performs operations. Memory is accessed for load and store instructions. Registers are written with results.

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    DataPath Design

    Uploaded by

    Oliver Barrina Jaguines
    110 views23 pages
    The document discusses the stages and components of a datapath design for a microprocessor, including instruction fetch, decode, execution, memory access, and register write stages. It describes the functional units needed like the program counter, instruction memory, ALU, registers, and buses to route data. The instruction fetch stage fetches instructions from memory and increments the PC. The decode stage gathers instruction fields. The ALU performs operations. Memory is accessed for load and store instructions. Registers are written with results.

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    The document discusses the stages and components of a datapath design for a microprocessor, including instruction fetch, decode, execution, memory access, and register write stages. It describes the functional units needed like the program counter, instruction memory, ALU, registers, and buses to route data. The instruction fetch stage fetches instructions from memory and increments the PC. The decode stage gathers instruction fields. The ALU performs operations. Memory is accessed for load and store instructions. Registers are written with results.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    110 views23 pages

    DataPath Design

    Uploaded by

    Oliver Barrina Jaguines
    The document discusses the stages and components of a datapath design for a microprocessor, including instruction fetch, decode, execution, memory access, and register write stages. It describes the functional units needed like the program counter, instruction memory, ALU, registers, and buses to route data. The instruction fetch stage fetches instructions from memory and increments the PC. The decode stage gathers instruction fields. The ALU performs operations. Memory is accessed for load and store instructions. Registers are written with results.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    of 23

    Data Path Design

    ALU/DATA PATH
    Data path and Control
    DATAPATH
    implements fetch-
    decode-execute
    Functional Units to build datapath design
    Abstract/Simplified view of datapath
    design
    Stages of Datapath

    • Instruction Fetch
    • Instruction Decode
    • ALU(execution)
    • Memory Access
    • Register write
    Instruction Fetch
    • the 32-bit instruction word must first be fetched from memory (the
    cache-memory hierarchy)
    • also, this is where we Increment PC (that is, PC = PC + 4, to point to
    the next instruction: byte addressing so + 4)
    • A memory unit to store instructions of a program and supply
    instructions given an address.
    • Needs to provide only read access (once the program is loaded).
    • PC (Program Counter or Instruction address register) is a register that
    holds the address of the current instruction.
    • Adder to increment the PC to the address of the next instruction
    • An ALU permanently wired to do only addition. No extra control
    signal required
    Data Portion for Instruction Fetch

    PC=PC+4
    Instruction Decode
    • gather data from the fields (decode all necessary)
    Set of Instruction Formats
    ALU(Algorithmic Logic Unit)
    • the real work of most instructions is done here
    • is connected to storage elements (registers for holding data to be
    processed and the results of the processing) by data buses.
    • is normally composed of single element (one-bit) processors
    (primarily adders), which are assembled together to form a 32-bit
    processor
    • In the MIPS CPU, all arguments in the process are stored in registers.
    • This requires two buses to route data to the ALU.
    • All registers are tied to both output buses.
    • A single input bus carries results back to all 32 registers.
    Memory Access
    • only the load and store instructions do anything during this stage; the
    others remain idle during this stage or skip it all together
    Register Write
    • most instructions write the result of some computation into a
    register
    Branch Datapath
    • the program counter gets an entirely new address (new address =
    [PC] + 16-bit immediate from instruction [± 32,768])
    • Not only do we need an add function, but also a left shift 2 places
    (since memory is addressed as bytes, but the 16-bit immediate in the
    branch instruction is a word address).
    Jump ALU Path
    • A jump instruction unconditionally transfers program control to a
    new location in the program.
    • The ALU must therefore use the 26-bit immediate address in the
    instruction to create a new PC address.
    • This is done by (1) shifting left 2 (to create a proper 28-bit byte
    address), and (2) adding the upper four PC bits to complete the new
    32-bit address.
    • This new address is then loaded into the program counter as the
    address of the next instruction to be executed.
    Jump ALU Path
    Generic Steps of Datapath
    Microprocessor
    Signals

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