Interrupts (Chapter 12)

Interrupt Types
Hardware Interrupts: External event
Software Interrupts: Internal event (Software generated)
Maskable and non-maskable interrupts
Interrupt priority

Interrupt Vectors and Interrupt Handlers

Interrupt Controllers

The Purpose of Interrupts

Interrupts are useful when interfacing I/O devices with low datatransfer rates, like a keyboard or a mouse, in which case polling the
device wastes valuable processing time
The peripheral interrupts the normal application execution,
requesting to send or receive data.
The processor jumps to a special program called Interrupt Service
Routine to service the peripheral
After the processor services the peripheral, the execution of the
interrupted program continues.

Main Program

Main Program
Printer Interrupt

Main Program
Modem Interrupt

Main Program
Modem Interrupt

BASIC INTERRUPT TERMINOLOGY

Interrupt pins: Set of pins used in hardware interrupts
Interrupt Service Routine (ISR) or Interrupt handler: code used for handling a specific
interrupt
Interrupt priority: In systems with more than one interrupt inputs, some interrupts have a
higher priority than other
They are serviced first if multiple interrupts are triggered simultaneously

Interrupt vector: Code loaded on the bus by the interrupting device that contains the
Address (segment and offset) of specific interrupt service routine
Interrupt Masking: Ignoring (disabling) an interrupt
Non-Maskable Interrupt: Interrupt that cannot be ignored (power-down)

Interrupt processing flow

Hardware Interrupts Interrupt pins and timing

x86 Interrupt Pins
INTR: Interrupt Request. Activated by a peripheral device to interrupt the processor.
Level triggered. Activated with a logic 1.
/INTA: Interrupt Acknowledge. Activated by the processor to inform the interrupting device the the
interrupt request (INTR) is accepted.
Level triggered. Activated with a logic 0.
NMI: Non-Maskable Interrupt. Used for major system faults such as parity errors and power failures.
Edge triggered. Activated with a positive edge (0 to 1) transition.
Must remain at logic 1, until it is accepted by the processor.
Before the 0 to 1 transition, NMI must be at logic 0 for at least 2 clock cycles.
No need for interrupt acknowledgement.

Interrupt Vectors
The processor uses the interrupt vector to determine the address of the
ISR of the interrupting device.
In the 8088/8086 processor as well as in the 80386/80486/Pentium
processors operating in Real Mode (16-bit operation), the interrupt vector
is a pointer to the Interrupt Vector Table.
The Interrupt Vector Table occupies the address range from 00000H to
003FFH (the first 1024 bytes in the memory map).
Each entry in the Interrupt Vector Table is 4 bytes long:
The first two represent the offset address and the last two the
segment address of the ISR.
The first 5 vectors are reserved by Intel to be used by the processor.
The vectors 5 to 255 are free to be used by the user.

The Intel x86 Vector Interrupts:- Protected Mode (32-bit)

In the 80386/80486/Pentium processors operating in the Protected Mode (32bit operation), the interrupt vector is a pointer to the Interrupt Descriptor Table.
The Interrupt Descriptor Table can be located anywhere in the memory.
Its starting address is pointed by the Interrupt Descriptor Table Register
(IDTR).
Each entry in the Interrupt Vector Table is 8 bytes long:
Four bytes represent the 32-bit offset address, two the segment selector
and the rest information such as the privilege level.
The first 32 vectors are reserved by Intel to be used by the processor.
The vectors 33 to 255 are free to be used by the user.

The protected mode

interrupt descriptor

Offset (A31 - A16)

5 PF

01110

00H

Segment Selector

Offset (A15 - A0)

Circuits for generating Interrupt Vectors

Interrupt Vector: FFH

Interrupt Vector: any

Interrupt Vector - Example

Draw a circuit diagram to show how a device with interrupt vector 4CH can be
connected on an 8088 microprocessor system.
Answer:

The peripheral device activates the INTR line

The processor responds by activating the INTA signal
The NAND gate enables the 74LS244 octal buffer
the number 4CH appears on the data bus

The processor reads the data bus to get the interrupt vector

8088 System

D7

Peripheral
Device
D0
A0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
E2

INTR

LS244

A19

E1
I7 I6 I5 I4 I3 I2 I1 I0

INTA

4C = 0 1 0 0 1 1 0 0
INTR

+5V

Interrupt Vector Table Real Mode (16-bit) Example

Using the Interrupt Vector Table shown below, determine the address of the ISR of a device
with interrupt vector 42H.
Answer: Address in table = 4 X 42H = 108H

(Multiply by 4 since each entry is 4 bytes)

Offset Low = [108] = 2A,

Offset High = [109] = 33

Segment Low = [10A] = 3C,

Segment High = [10B] = 4A

Address = 4A3C:332A = 4A3C0 + 332A = 4D6EAH

0

00000
00010
.........
00100
00110
.........
00250

3C 22 10 38 6F 13 2C 2A 33
11 3C 32 88 90 16 44 32 14
... ... ... ... ... ... ... ... ...
4A 33 3C 4A AA 1A 1B A2 2A
C1 58 4E C1 4F 11 66 F4 C5
... ... ... ... ... ... ... ... ...
00 10 10 20 3F 26 33 3C 20

22
30
...
33
58
...
26

21 67 EE F1
42 58 30 36
... ... ... ...
3C 4A AA 1A
4E 20 4F 11
... ... ... ...
20 C1 3F 10

32
34
...
3E
F0
...
28

25
66
...
77
F4
...
32

00260
.........
003E0

20
...
3A

4E
...
10

00
...
45

10
...
2F

50
...
4E

88
...
33

22
...
6F

38
...
90

10
...
3A

5A
...
44

38
...
37

10
...
43

4C
...
3A

55
...
54

14
...
54

54
...
7F

003F0

22

3C

80

01

3C

4F

4E

88

22

3C

50

21

49

3F

F4

65

Interrupt Vector Table Real Mode (16-bit) Example

Write a sequence of instructions that initialize vector 40H to point to the ISR isr40.
Answer: Address in table = 4 X 40H = 100H

Set ds to 0 since the Interrupt Vector Table begins at 00000H

Get the offset address of the ISR using the Offset directive

and store it in the addresses 100H and 101H

Get the segment address of the ISR using the Segment directive

and store it in the addresses 102H and 103H

push
push
mov
mov
mov
mov
mov
mov
pop
pop

ax
Save registers in the stack
ds
ax,0
Set ds to 0 to point to the interrupt vector table
ds,ax
ax,offset isr40
Get the offset address of the ISR and store
it in the address 0100h (4X40h = 100h)
[0100h],ax
ax,segment isr40
Get the segment address of the ISR
[0102h],ax
and store it in the address 0102h
ds
Restore registers from the stack
ax

Expanding Interrupt to seven request lines

IR0

IR1

IR2

IR3

IR4

IR5

IR6

Vector

FEH

FDH

FBH

F7H

EFH

DFH

BFH

Identifying Interrupt Source

Software Polling,

Checking each device

Hardware Polling, (Daisy Chain),

Hardware Identification (Vectored Interrupts).

Daisy-Chained Interrupt
Each device is connected to
the same interrupt request
line, but there is only a
single interrupt vector.
The device that sent the
request will respond.

Interrupt Masking
The processor can inhibit certain types of interrupts by use of a special interrupt mask
bit.
This mask bit is part of the flags/condition code register, or a special interrupt register.
If this bit is clear, and an interrupt request occurs on the Interrupt Request input, it is
ignored.
NMI cannot be masked

Software Interrupts
Traps: (self-interrupt!)
Single step mode
Calls to Operating System (INT 21H - x86, SC PPC)

Exceptions:
Divide by zero
Memory protection fault

Interrupt Processing
Save state

Disable interrupts for the duration of the ISR or allow it to be interrupted too?
Save program counter
Save flags
Save register values?

Jump to interrupt service routine

Location obtained by interrupt vector

Process interrupt
Restore state
Load PC, flags, registers etc.

Interrupt Processing on the 8086 Microprocessor

1. External interface sends an interrupt signal, to the Interrupt Request (INTR) pin,
(or an internal interrupt occurs.)
2. The CPU finishes the present instruction (for a hardware interrupt) and checks
the INTR pin.
If IF=0 the processor ignores the interrupt, else sends Interrupt Acknowledge (INTA)
to hardware interface.
3. The interrupt type N is sent to the Central Processor Unit (CPU) via the Data bus
from the hardware interface.
4. The contents of the flag registers are pushed onto the stack.
5. Both the interrupt (IF FR bit 9) and (TF FR bit 8) flags are cleared. This
disables the INTR pin and the trap or single-step feature.
6. The contents of the code segment register (CS) are pushed onto the Stack.
7. The contents of the instruction pointer (IP) are pushed onto the Stack.
8. The interrupt vector contents are fetched, from (4 x N) and then placed into the IP
and from (4 x N +2) into the CS so that the next instruction executes at the interrupt
service procedure addressed by the interrupt vector.
9. While returning from the interrupt-service routine by the Interrupt Return
(IRET) instruction, the IP, CS and Flag registers are popped from the Stack and
return to their state prior to the interrupt.

The Intel x86 Interrupt Software Instructions

All x86 processors provide the following instructions related to interrupts:
INT nn: Interrupt. Run the ISR pointed by vector nn.
INT 0 is reserved for the Divide Error
INT 1 is reserved for Single Step operation
INT 2 is reserved for the NMI pin
INT 3 is reserved for setting a Breakpoint
INT 4 is reserved for Overflow (Same as the INTO (Interrupt on overflow) instruction.
CLI: Clear Interrupt Flag. IF is set to 0, thus interrupts are disabled.
STI: Set Interrupt Flag. IF is set to 1, thus interrupts are enabled.
IRET: Return from interrupt. This is the last instruction in the ISR (Real Mode only). It
pops from the stack the Flag register, the IP and the CS.
After returning from an ISR the interrupts are enabled, since the initial value of the flag
register is poped from the stack.
IRETD: Return from interrupt. This is the last instruction in the ISR (Protected Mode
only). It pops from the stack the Flag register, the EIP and the CS.

The 8259A Programmable Interrupt Controller

Adds 8 vectored priority encoded interrupts to the microprocessor
Can be expanded without additional hardware to accept up to 64 IRQ (one 8259A
master, and one slave)
Requires 4 wait states to be connected to a x386
D0-D7: Bidirectional data connections
IR0-IR7: Interrupt request inputs
WR: Write input strobe
RD: Read input connects to the IORCsignal
INT: Output, connects to P INTR pin
INTA: Input, connects to P INTA pin
A0: Command word select
CS: Chip select input
SP/EN: Slave program/enable buffer pin
CAS0-CAS2: Outputs from master to slave for cascading multiple 8259A chips

Connecting a single 8259A controller

Programming the 8259A

Initialization Control Words (ICWs)

Prgrammed before 8259A begins to function

A0 must be high
There are four ICWs: ICW1, ICW2, ICW3, ICW4
When there is only one 2259A in the system, ICW3 is not necessary

Operation Control Words (OCWs)

Programmed during normal operation
There are three OCWs: OCW1, OCW2, OCW3
A0 must be low, except in OCW1

ICW1/ICW2
ICW1 Programs the basic operation of the 8259A
Initialization Control Word (ICW1) Bits

7:5 (Interrupt Vector Addresses for MCS-80/85 Mode, dont cares for x86.)
4 (Must be set to 1 for ICW1)
3 (1: Level Triggered Interrupts, 0: Edge Triggered Interrupts)
2 (1: Call Address Interval of 4, 0: Call Address Interval of 8)
1 (1: Single 8259A, 0: Cascaded 8259A)
0 (1: Will be Sending ICW4, 0: Don't need ICW4)

ICW2 specifies the vector number used with the interrupt request inputs
Example: for vectors 08H-0FH, write 08H in ICW2
Example: for vectors 70H-77H, write 70H in ICW2

ICW3/ICW4
ICW3 only used in cascade mode, indicating where the slave is connected to the
master.
Example: If slave is connected in IR3, we write 00001000 = 04H in ICW3

ICW4 bits
7-5: Always 0
4: When 1 a IR request from a slave is recognized by the master while processing
another slave interrupt
3: 1- Buffered operation, 0 Non-buffered operation
2: 1- 8259A is master, 0 8259A is slave
1: 1- Automatic end of interrupt (preferable), 0 normal end of interrupt
0: Always 1 in 8088/8086 mode

OCW1/OCW2
Operation Control Word 1 (OCW1) bits: Sets the mask register

7 Mask IRQ7 (when 1)

6 Mask IRQ6 (when 1)
5 Mask IRQ5 (when 1)
4 Mask IRQ4 (when 1)
3 Mask IRQ3 (when 1)
2 Mask IRQ2 (when 1)
1 Mask IRQ1 (when 1)
0 Mask IRQ0 (when 1)

OCW2 is used when automatic/normal end of interrupt is not selected

OCW3
OCW3 is used to read internal 8259A registers, specify the operation of the special
mask register, and the poll command
Status registers:
Interrupt Request Register (IRR): indicates which IR inputs are active
In-Service Register (ISR): contains the level of the interrupt being serviced
Interrupt Mask Register (IMR): Holds the interrupt mask bits

IRR and ISR are read by programming OCW3, IMR is read through OCW1

Example
Use an 8259A PIC to connect the I/O device in the example of slide 8

Interrupt Service Routine

Interrupt Vectors
The Interrupt Vector contains the address of the interrupt service routine
The Interrupt Vector Table is located in the first 1024 bytes of memory at address
000000H-0003FFH.
It contains 256 different 4-byte interrupt vectors, grouped in 18 types

000H: Type 0 (Divide error)

004H: Type 1 (Single-step)
008H: Type 2 (NMI)
00CH: Type 3 (1-byte breakpoint)
010H: Type 4 (Overflow)
014H: Type 5 (BOUND)
018H: Type 6 (Undefined opcode)
01CH: Type 7 (Coprocessor not available)
020H: Type 8 (Double fault)
024H: Type 9 (Coprocessor segment overrun)
028H: Type 10 (Invlid task state segment)
02CH: Type 11 (Segment not present)

030H: Type 12 (Stack segment

overrun)
034H: Type 13 (General
protection)
038H: Type 14 (Page fault)
03CH: Type 15 (Unassigned)
040H: Type 16 (Coprocessor
error)
044H-07CH: Type 14-31
(Reserved)
080H: Type 32-255 (User)

Interrupt Types

Type 0: Divide error Division overflow or division by zero

Type 1: Single step or Trap After the execution of each instruction when trap flag set
Type 2: NMI Hardware Interrupt 1 in the NMI pin
Type 3: One-byte Interrupt INT3 instruction (used for breakpoints)
Type 4: Overflow INTO instruction with an overflow flag
Type 5: BOUND Register contents out-of-bounds
Type 6: Invalid Opcode Undefined opcode occurred in program
Type 7: Coprocessor not available MSW indicates a coprocessor
Type 8: Double Fault Two separate interrupts occur during the same instruction
Type 9: Coprocessor Segment Overrun Coprocessor call operand exceeds FFFFH
Type 10: Invalid Task State Segment TSS invalid (probably not initialized)
Type 11: Segment not present Descriptor P bit indicates segment not present or invalid
Type 12: Stack Segment Overrun Stack segment not present or exceeded
Type 13: General Protection Protection violation in 286 (general protection fault)
Type 14: Page Fault 80386 and above
Type 16: Coprocessor Error ERROR = 0 (80386 and above)
Type 17: Alignment Check Word/Doubleword data addressed at odd location (486 and above)
Type 18: Machine Check Memory Management interrupt (Pentium and above)

Real Mode Interrupt

When current instruction execution completes, the processor checks:

1.
2.
3.
4.
5.
6.

Instruction executions
Single-step
NMI
Coprocessor segment overrun
INTR
INT instruction

When there is a pending interrupt:

1.
2.
3.
4.
5.

The contents of the flag register are pushed onto the stack
IF and TF are cleared, disabling the INTR pin
CS is pushed to the stack
IP is pushed onto the stack
Interrupt Vector contents are fetched and placed into IP and CS, so the next instruction is the
Interrupt Service Routine indicated by the Interrupt Vector

Protected Mode Interrupt

Exactly the same assignments as in Real Mode, but instead of Interrupt Vectors, there is
an Interrupt Descriptor Table, located anywhere in memory (indicated by the IDTR)

82C55 Keyboard Interrupt Circuit

Interrupt Service Routine for Keyboard