Counters and Time Delays: by Dr. Syed Sahal Nazli Alhady

Counters and Time Delays
by Dr. Syed Sahal Nazli Alhady
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Page 1
Counter
A counter is designed simply by loading an
appropriate no. into one of the register
and using INR (increment by 1) or DCR
(Decrement by 1) instructions.
A loop is established to update the count
and each count is checked to determine
whether it has reached the final numbers.
Page 2
Initialize
Display
Update
NO
Register
=0?
YES
Page 3
Counter
The counting is performed at such high
speed that only the last count can be
observed.
To observe counting, there must be an
appropriate time delay between counts
Page 4
Time Delay
The procedure used to design a specific
delay is similar to that used to set up a
counter
A register is loaded with a number,
depending on the time delay required and
then the register is decremented until it
reaches zero by setting up a loop with a
conditional Jump instruction
The loop causes the delay, depending
upon the clock period of the system
Page 5
Load Delay
Register
Decrement
Register
NO
T-state
MVI C,FFH 7
Loop: DCR C
4
JNZ Loop 10/7
Register
=0?
YES
Page 6
Time Delay
T-states (clock periods) require by the
8085 up to execute each instruction.
MVI requires 7 clock periods
Up with 2MZ clock frequency will execute
the instruction in
Clock frequency f = 2MHZ
Clock periods T = 1/f = 0.5us
Time to execute MVI = 7 T-states x 0.5us
= 3.5us
Page 7
Time Delay
If 1MHz clock frequency is used, up
require
7us
to
execute
the
same
instruction
Register C is loaded with FFH (255)
The next 2 instructions, DCR and JNZ form
a loop with a total of 14 (4 + 10) T-states
The loop repeated 255 times until register
C=0
Page 8
Time Delay
TL = (T x Loop T-states x N10)
Where TL Time delay in the loop
T System clock period
N10 - Equivalent decimal number of
the hex count loaded in the delay register
DCR + JNZ
TL = (0.5 x 10-6 x 14 x 255)

= 1785us
1.8ms
Page 9
Time Delay
To
calculate
the time
delay
more
accurately, we need to adjust for the
execution of JNZ instruction and add the
execution time of the initial instruction
T-states for JNZ shown as 10/7.
Up requires 10 T-states to execute a
conditional jump instruction when it
jumps or changes the sequence
7 T-states when it fall through the loop
(out of the loop)
In the last cycles , JNZ instruction will be
executed in 7 T-states
Page 10
Time Delay
TLA = TL (3 T-states x clock period)
= 1785 (3 x 0.5)
= 1783.5us
Page 11
Time Delay
The total delay must take into account the
execution time of the instruction outside
the loop
MVI C,FFH is one instruction outside the
loop
Total Delay = Time outside loop + Time
inside loop
TD = TO + TLA
= (7 x 0.5) + 1783.5
= 1787us
1.8ms
Page 12
Time Delay
The difference between the loop delay TL
and these calculations is only 2us and can
be ignored in most instances
The time delay can be varied by changing
the count FFH; how ever to increase the
time delay beyond 1.8ms in 2MHz up,
register pair or loop within a loop
technique should be used
Page 13
Time Delay Register Pair

Max FFFFH can be count by using 16 bit
no. Of register pair.
16 bit no. Is dcremented by using DCX
isntruction.
DCX does not set the Zero flag.
Additional techniques therefore must be
used to set the Zero flag
Page 14

LXI B, 2384H
10
Loop: DCX B
6
MOV A,C
4
ORA B
4
JNZ Loop
10/7
The instruction LXI B,2384H loads register
B 23H and C 84H
DCX decrements the entire no by one
MOV A,C and ORA B used to set Zero flag
otherwise
ORA B sets the Zero flag only when the
contents of B and C are simultaneously
zero. Free Powerpoint Templates
Page 15

2384H = 9092
If the clock period of the sys. = 0.5us
TL = (0.5 x 24 x 9092) (3 x 0.5)
= 109104us 1.5
= 109102.5
Total delay
LXI B, 2384H 10T
TD = 109102.5 + TO
= 109102.5 + (5)
= 109097.5
Page 16
Time Delay Loop within Loop

A time delay similar to that of a register
pair can also be achieved by using 2 loops
One loop inside and the other loop is
outside
Page 17
Load register B
MVI C,FFH
LOOP2
Load register C
LOOP1
Decrement C
TL, Delay
in Loop 1
NO
C=
0
YES
Decrement B
DCR B
JNZ LOOP2
NO
B=
0
YES
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Page 18

The follwoing instruction can be used to
implement the flowchart
MVI B,38H
Loop2:
MVI C,FFH
Loop1:
DCR C
JNZ Loop1
DCR B
4T
JNZ Loop2
7T
7T
4T
10/7T
10/7T
Page 19
Time Delay
The disadvantages in using software delay
techniques for real-time applications is
which the demand for time accuracy is
high
the accuracy of the time delay depends
on the accuracy of the systems clock
The up is occupied simply in a waiting
loop; otherwise it could be employed to
perform
the task of calculating accurate time
delay is tedious
Page 20
Quiz 5
Page 21

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Counters and Time Delays

by Dr. Syed Sahal Nazli Alhady

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TL = (0.5 x 10-6 x 14 x 255)

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Time Delay Register Pair

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Time Delay Register Pair

Time Delay Register Pair

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Time Delay Loop within Loop

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Time Delay Loop within Loop

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Time Delay Loop within Loop

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