Interrupt Driven Io

INTERRUPT DRIVEN I/O METHODOLOGY
Interrupt I/O technique requires more complex of hardware and

software than Programmed I/O. The Figure 1 below shows the simple
interrupt processing and Figure 2 shows the basic operation of the
interrupt technique for an input.
Figure 1 :
Simple Interrupt
Processing
For the
PSW : Program
hardware part,
Status Word
when a peripheral
PC: Program Counter
device issues an
interrupt signal to
the processor,
the processor will
finishes the
execution of the current instruction before responding to the interrupt
signal. Next, the processor will send acknowledgment signal to the
device that issues the interrupt for the device to removes its interrupt
signals. Then, the processor needs to prepare to transfer control to the interrupt routine.
The processor needs to save the information which are the PSW and PC in order to
resume the current program at the point of interrupt. These can be pushed into the system
control stack. Next the processor loads the program counter with the entry location of
the interrupt handling program that will respond to the interrupt.
After the program counter has been loaded, the processor will continue with the next
instruction cycle, which begins with an interrupt fetch. The control will transfer to
interrupt handler routine for the current interrupt. At the point, the program counter
and PSW relating to the interrupted program have been saved on the system stack.
Then, the interrupt will be processes. When interrupt processing is complete, the saved
register values are retrieved from the stack and restored to the registers. Lastly is to
restore the PSW and program counter values from the stack. As a result, the next instruction
to be executed will be from the previously interrupted program.
Figure 2 : Interrupt
Driven I/O flowchart
From the point of view

of the I/O module, the
I/O module services
read command from
the processor and
proceed to read data
from an associated
peripheral device. Once
the data are in the
modules data register, the I/O module issues an interrupt to the
processor over a control line. I/O module waits for the processor to
request the data. When the processor made a request, the I/O module
will place the data on the data bus and ready for next operation.
From the processor point of view, the processor issues a read
commands and proceeds to do other work. At the end of each
instruction cycle, the processor will check for interrupts. If interrupt
from I/O module occur, the processor saves the current operation and
process the interrupt. The processor reads the word of data from the
I/O module and write the word into memory. Next, the processor
restores the operation it was working on and resumes execution.
Interrupt Driven I/O Simulation
Figure 3 : The program interface

Figure shows the main interface of the program where the Interrupt
Driven I/O is selected.
Figure 4 : Interrupt Driven I/O simulator
Figure shows the Interrupt Driven I/O simulator that consist of a few
modules such as I/O module, processor module and memory modules.
Memory modules are divided into two sections which are, the main
memory module (top) and the I/O memory module (bottom).
Figure 5 : Simulation start
When the simulation started, the processor send address and control
signal to the main memory to be saved. Then, it will read the memory
data back to the processor.
Figure 6 : Interrupt signal send by READ operation
The processor issues a read command to the I/O module to check for
interrupt signal, and when there is an interrupt, the processor will save
the current program and process the interrupt.
Figure 7 : Stored data in I/O memory
During the interrupt process, the processor send address and control
signal to the I/O memory to be stored. After the data be stored, the I/O
read the data.
Figure 8 : Interrupt operation is complete
The interrupt processes are repeated for four times in order to

complete the interrupt operation. When the interrupt operation is
completed, the processor will proceed execute with its current program
that has been stored before.
Figure 9 : Interrupt signal send by WRITE operation
When the interrupt operation is ready, the I/O module send interrupt
signal to the processor for the WRITE operations. The processor stored
its currents program and process the interrupt program.
Figure 10 : I/O WRITE operation in the I/O memory module
After the processor granted the I/O module permission to process the
interrupt program, the I/O module send I/O write to the processor.
Then, the processor send address and control signal to the I/O memory
and write the memory data back to the processor.
Figure 11 : I/O WRITE operation is complete
When the I/O WRITE operation is completed, the processor restored its
current program and proceed with the execution operation.
RESULT AND DISCUSSION
Figure 12 : Interrupt READ operation

Figure 13 : Interrupt WRITE operation
Based on the result, we can see that the Interrupt Driven I/O simulation
are successful for both READ and WRITE operations. For the READ
operation, after each instruction cycle, the processor will issue READ
command to the I/O module to check for an interrupt. If there is
interrupt signal, the processor will stored its current program and
process the interrupt signal. The I/O module gets data from the
peripheral device and transfer the data to the processor. The processor
then will store the data into the I/O memory in order to complete the
READ interrupt operation. Then, it will restored the last program and
proceed with the execution.
For the WRITE operation, when the interrupt operation is ready, the I/O
module will issue an interrupt signal to the processor. When the
processor requests for the data which is the WRITE operation, the I/O
module will transfer the data to the processor until the operation is
completed. Once the WRITE interrupt operation is completed, the
processor proceed with its current program that has been stored
before.
The Interrupt Driven I/O advantages are, it allows the processor to

execute its instructions in sequence and only stop execute only when it
is told to do so.
However, the Interrupt Driven I/O technique have some design issues.
The issues are how to identify the module that issuing the interrupt
and how to deal with multiple interrupt signals. The solution for the
first design issue can be divided into four techniques. First, by using
multiple interrupt lines by providing multiple lines between the
processor and I/O module. Each interrupt lines are connected to
multiple I/O modules. However, it is not practical for the interrupt lines
to have more than a few bus lines pin to it. Thus, the second technique
which is Software Poll must be used with the multiple interrupt lines
techniques. When the processor detects an interrupt signal, the
processor asks each I/O modules to determine the module that issue
the interrupt signal. The disadvantage of this technique is time
consuming.
Next is a hardware poll or Daisy Chain. This technique must be used
with the multiple interrupt lines technique too. For this technique, all
I/O modules share common interrupt lines. When interrupt is
acknowledge, the module that issue the interrupt will placed a word on
the data lines that referred to as a vector. The processor uses the
vector to identify the handle routine.
The last method is the bus arbitration. This method also utilizes the
vectored interrupt used in hardware poll. In this method, it is involves
the I/O module to gain a control of the bus before the interrupt signal is
raised. Thus, only one module can send interrupt line at one time.
When the processor has acknowledge the module, the module will
placed the vector on the data line.
The second design issue can be solved by using priorities. When there
are multiple interrupt at a time, each interrupt line will be assigned
with the priority position based on the techniques that has been used
to determine the interrupt. Each technique give the higher priority line
to interrupt the lower priority line except the bus arbitration technique.
For bus arbitration technique, only the current master can be interrupt.

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What are the main components of an interrupt driven I/O system?

How does an interrupt driven I/O READ operation work?

INTERRUPT DRIVEN I/O METHODOLOGY

Interrupt I/O technique requires more complex of hardware and

From the point of view

Figure 3 : The program interface

The interrupt processes are repeated for four times in order to

Figure 12 : Interrupt READ operation

The Interrupt Driven I/O advantages are, it allows the processor to

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