Chapter 7.

Basic
Processing Unit
CENG 2213
Computer Organization
Instructor: Dr. Shen
Connection Between the
Processor and the Memory
Fi gure 1.2. Connecti ons between the processor and the memory.
Processor
Memory
PC
IR
MDR
Control
ALU
Rn 1 -
R1
R0
MAR
n general purpose
registers
Chapter 1, class exercise/homework 1.1
Add LOCA, R0

Transfer the contents of register PC to register MAR
Issue a Read command to memory, and then wait until it has transferred the
requested word into register MDR
Transfer the instruction from MDR into IR and decode it
Transfer the address LOCA from IR to MAR
Issue a Read command and wait until MDR is loaded
Transfer contents of MDR to the ALU
Transfer contents of R0 to the ALU
Perform addition of the two operands in the ALU and transfer result into R0
Transfer contents of PC to ALU
Add 4 to operand in ALU and transfer incremented address to PC

Overview
Instruction Set Processor (ISP)
Central Processing Unit (CPU)
A typical computing task consists of a series
of steps specified by a sequence of machine
instructions that constitute a program.
An instruction is executed by carrying out a
sequence of more rudimentary operations.
Some Fundamental
Concepts
Fundamental Concepts
Processor fetches one instruction at a time and
perform the operation specified.
Instructions are fetched from successive memory
locations until a branch or a jump instruction is
encountered.
Processor keeps track of the address of the memory
location containing the next instruction to be fetched
using Program Counter (PC).
Instruction Register (IR)
Executing an Instruction
Fetch the contents of the memory location pointed
to by the PC. The contents of this location are
loaded into the IR (fetch phase).
IR [[PC]]
Assuming that the memory is byte addressable,
increment the contents of the PC by 4 (fetch phase).
PC [PC] + 4
Carry out the actions specified by the instruction in
the IR (execution phase).
Processor Organization
lines
Data
Address
lines
bus
Memory
Carry -in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control ALU
lines
Control signals
R n 1 -
Instruction
decoder and
Internal processor
control logic
A B
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
MUX Select
Constant 4
Datapath
Textbook Page 413
Executing an Instruction
Transfer a word of data from one processor
register to another or to the ALU.
Perform an arithmetic or a logic operation
and store the result in a processor register.
Fetch the contents of a given memory
location and load them into a processor
register.
Store a word of data from a processor
register into a given memory location.
Register Transfers
B A
Z
ALU
Y in
Y
Z in
Z out
R i
in
R i
R i out
b us
Internal processor
Constant 4
MUX
Figure 7.2. Input and output gating for the registers in Figure 7.1.
Select
Textbook Page 416
Register Transfers
All operations and data transfers are controlled by the processor clock.
Fi gure 7.3. Input and output g ati ng for one re gi ster bi t.
D Q
Q
Clock
1
0
Riout
Ri in
Bus
Figure 7.3. Input and output gating for one register bit.
Performing an Arithmetic or
Logic Operation
The ALU is a combinational circuit that has no
internal storage.
ALU gets the two operands from MUX and bus.
The result is temporarily stored in register Z.
What is the sequence of operations to add the
contents of register R1 to those of R2 and store the
result in R3?
1. R1out, Yin
2. R2out, SelectY, Add, Zin
3. Zout, R3in
Fetching a Word from Memory
Address into MAR; issue Read operation; data into MDR.
MDR
Memory -bus
Fi gure 7.4. Connecti on and control si gnal s for re gi ster MDR.
data lines
Internal processor
bus MDRout MDRoutE
MDRin MDRinE
Figure 7.4. Connection and control signals for register MDR.
Fetching a Word from Memory
The response time of each memory access varies
(cache miss, memory-mapped I/O,).
To accommodate this, the processor waits until it
receives an indication that the requested operation
has been completed (Memory-Function-Completed,
MFC).
Move (R1), R2
MAR [R1]
Start a Read operation on the memory bus
Wait for the MFC response from the memory
Load MDR from the memory bus
R2 [MDR]
Timing
Fi gure 7.5. Ti mi ng of a memory Read operati on.
1 2
Clock
Address
MR
Data
MFC
Read
MDRinE
MDRout
Step 3
MARin
Assume MAR
is always available
on the address lines
of the memory bus.
Move (R1), R2
1. R1out, MARin, Read
2. MDRinE, WMFC
3. MDRout, R2in
Execution of a Complete
Instruction
Add (R3), R1
Fetch the instruction
Fetch the first operand (the contents of the
memory location pointed to by R3)
Perform the addition
Load the result into R1
Architecture
B A
Z
ALU
Y in
Y
Z in
Z out
R i
in
R i
R i out
b us
Internal processor
Constant 4
MUX
Figure 7.2. Input and output gating for the registers in Figure 7.1.
Select
Execution of a Complete
Instruction
Step Action
1 PCout , MARin , Read, Sel ect4,Add, Zin
2 Zout , PCin , Yin , WMF C
3 MDRout , IRin
4 R3out , MARin , Read
5 R1out , Yin , WMF C
6 MDRout , Sel ectY,Add, Zin
7 Zout , R1in , End
Fi gure7.6. Control sequencefor executi onof the i nstructi on Add (R3),R1.
lines
Data
Address
lines
bus
Memory
Carry -in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control ALU
lines
Control signals
R n 1 -
Instruction
decoder and
Internal processor
control logic
A B
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
MUX Select
Constant 4
Add (R3), R1
Add R2, R1 ?
Execution of a Complete
Instruction
Step Action
1 PCout , MARin , Read, Sel ect4,Add, Zin
2 Zout , PCin , Yin , WMF C
3 MDRout , IRin
4 R3out , MARin , Read
5 R1out , Yin , WMF C
6 MDRout , Sel ectY,Add, Zin
7 Zout , R1in , End
Fi gure7.6. Control sequencefor executi onof the i nstructi on Add (R3),R1.
lines
Data
Address
lines
bus
Memory
Carry -in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control ALU
lines
Control signals
R n 1 -
Instruction
decoder and
Internal processor
control logic
A B
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
MUX Select
Constant 4
Add R2, R1
R2
out
Execution of Branch
Instructions
A branch instruction replaces the contents of
PC with the branch target address, which is
usually obtained by adding an offset X given
in the branch instruction.
The offset X is usually the difference between
the branch target address and the address
immediately following the branch instruction.
Conditional branch
Execution of Branch
Instructions
Step Action
1 PC
out
, MAR
in
, Read, Select4, Add, Z
in
2 Z
out
, PC
in
, Y
in
, WMF C
3 MDR
out
, IR
in
4 Offset-field-of-IR
out
, Add, Z
in
5 Z
out
, PC
in
, End
Figure 7.7. Control sequence for an unconditional branch instruction.
Multiple-Bus Organization
Memory bus
data lines
Fi gure 7.8. Three-bus organi zati on of the datapath.
Bus A Bus B Bus C
Instruction
decoder
PC
Register
f ile
Constant 4
ALU
MDR
A
B
R
M U X
Incrementer
Address
lines
MAR
IR
Textbook Page 424
Allow the contents of two
different registers to be
accessed simultaneously and
have their contents placed on
buses A and B.
Allow the data on bus C to
be loaded into a third register
during the same clock cycle.
Incrementer unit.
ALU simply passes one of ts
two input operands
unmodified to bus C
control signal: R=A or R=B

Multiple-Bus Organization
Add R4, R5, R6
Step Action
1 PC out , R=B, MAR in , Read, IncPC
2 WMF C
3 MDR outB , R=B, IR
in
4 R4
outA
, R5
outB
, SelectA, Add, R6
in
, End
Figure 7.9. Control sequence for the instruction. Add R4,R5,R6,
for the three-bus organization in Figure 7.8.
Exercise
What is the control
sequence for
execution of the
instruction
Add R1, R2
including the
instruction fetch
phase? (Assume
single bus
architecture)
lines
Data
Address
lines
bus
Memory
Carry -in
ALU
PC
MAR
MDR
Y
Z
Add
XOR
Sub
bus
IR
TEMP
R0
control ALU
lines
Control signals
R n 1 -
Instruction
decoder and
Internal processor
control logic
A B
Fi gure 7.1. Si ngl e-bus organi zati on of the datapath i nsi de a processor.
MUX Select
Constant 4
26
Fetch-Execute Cycle
Two-step process because both instructions
and data are in memory
Fetch
Decode or find instruction, load the code of the
instruction from memory
Execute
Performs operation that instruction requires
Move/transform data
27
Fetch-part of the Cycle
The value in the PC (program counter) register is the
address of the memory location that holds instruction to be
executed
First step is always: transfer (copy) the value in the PC to
the MAR
Then computer can retrieve the instruction located at that
address and place it in the MDR
PC MAR (step 1)
Memory MDR
Next step: transfer instruction to the IR
MDR IR (step 2)
Remaining steps instruction dependent
28
Load Instruction
Next step: the address part of the instruction located
in the IR is copied and placed in the MAR
Computer retrieves actual data located at the address
in memory and places it in the MDR
IR [address] MAR (step 3)
Memory MDR
Next step: MDR copies data to the accumulator
register
MDR A (step 4)
Last step: PC is incremented
PC + 1 PC (step 5)



29
Load Accumulator: Sample (1 of
12)
Task: Simple Eight bit system.
Thirty-two memory locations (0 to 31).
Load instruction is 010.
Value in location 15 is ten (i.e.: binary 00001010)
PC is at 5, about to increment.
The instruction, 01001111, is in location 6.
30
Load Accumulator: Sample (2 of
12)
PC: 00101
IR: (previous)
A: (previous)
MAR: (previous)
MDR: (previous)
CPU Before PC increments
Location 31





15: 00001010



06: 01001111

Location 0
Memory
31
Load Accumulator: Sample (3 of
12)
Increment PC: PC = PC + 1
PC: 00110
IR: (previous)
A: (previous)
MAR: (previous)
MDR: (previous)
Location 31





15: 00001010



06: 01001111

Location 0
Memory
32
Load Accumulator: Sample (4 of
12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: (previous)
MAR loaded with PC: PC -> MAR
Location 31





15: 00001010



06: 01001111

Location 0
Memory
33
Load Accumulator: Sample (5 of
12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: (previous)
Memory Location 00110 Accessed
and Contents Placed in MDR:
Location 31





15: 00001010



06: 01001111

Location 0
Memory
34
Load Accumulator: Sample (6 of
12)
PC: 00110
IR: (previous)
A: (previous)
MAR: 00110
MDR: 01001111
Memory Location 00110 Accessed
and Contents Placed in MDR:
Location 31





15: 00001010



06: 01001111

Location 0
Memory
35
Load Accumulator: Sample (7 of
12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 00110
MDR: 01001111
MDR copied to IR: MDR -> IR
Location 31





15: 00001010



06: 01001111

Location 0
Memory
36
Load Accumulator: Sample (8 of
12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 01001111
IR [ address part ] -> MAR
Location 31





15: 00001010



06: 01001111

Location 0
Memory
37
Load Accumulator: Sample (9 of
12)
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 01001111
Location in MAR (01111) Accessed
Location 31





15: 00001010



06: 01001111

Location 0
Memory
38
Load Accumulator: Sample (10 of
12)
Memory
PC: 00110
IR: 01001111
A: (previous)
MAR: 01111
MDR: 00001010
Contents of 01111 loaded into MDR
Location 31





15: 00001010



06: 01001111

Location 0
39
Load Accumulator: Sample (11 of
12)
Memory
PC: 00110
IR: 01001111
A: 00001010
MAR: 01111
MDR: 00001010
IR [op code] executed: MDR -> A
Location 31





15: 00001010



06: 01001111

Location 0
40
Load Accumulator: Sample (12 of
12)
Memory
PC: 00110
IR: 01001111
A: 00001010
MAR: 01111
MDR: 00001010
Finished !
Location 31





15: 00001010



06: 01001111

Location 0
41
Load Fetch/Execute Cycle
1. PC -> MAR Transfer the address from the
PC to the MAR
2. MDR -> IR Transfer the instruction to the
IR
3. IR(address) -> MAR Address portion of the
instruction loaded in MAR
4. MDR -> A Actual data copied into the
accumulator
5. PC + 1 -> PC

Program Counter
incremented
42
Store Fetch/Execute Cycle (1 of
2)
1. PC -> MAR Transfer the address from
the PC to the MAR
2. MDR -> IR Transfer the instruction to
the IR
3. IR(address) -> MAR Address portion of the
instruction loaded in MAR
4. A -> MDR* Accumulator copies data into
MDR
5. PC + 1 -> PC Program Counter
incremented
*Notice how Step #4 differs for LOAD and STORE
MAIN MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05


A simple program that has been copied from the hard drive and put
into main memory
von-Neuman machine-Stored Program Approach. Where
both the data and program stored in main memory
Fetch-Decode-Execute
Fetch: The next instruction is fetched from Main
Memory.
Decode: The instruction gets
interpreted/decoded, signals produced to control
other internal components (ALU for example).
Execute: The instructions get executed (carried
out)
The processor contains a number of
special purpose registers.

A register is an extremely fast piece of on-
chip memory used for small temporary
storage.

Each of the special purpose registers
have an important role, when a series of
program instructions are fetched-decoded-
executed.


R0
R1
R2
R3
R4
R5
Special purpose registers
Arithmetic
Logic Unit
Current
Instruction
Register
Program
Counter
Status
Register
Control
Unit
Memory
Address
Register
Memory
Data
Register
General purpose registers
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register
Program
Counter:

500
Status
Register
Control Unit Memory
Address
Register
Memory
Data
Register
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
The Program Counter
The program counter holds the address of the next instruction
that is to be fetched-decoded-executed. This will increment
automatically as the current instruction is being decoded.
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register
Program
Counter:

500
Status
Register
Control Unit
Memory
Address
Register:
500
Memory
Data
Register
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Memory Address Register
(MAR)
The Memory Address Register (MAR) holds the address of the current
instruction being executed. It points to the relevant location in
memory where the required instruction is (at this stage the address is
simply copied from the Program Counter).
MAR [PC] (contents of Program
Counter copied to the Memory
Address Register)
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register
Program
Counter:

500
Status
Register
Control Unit Memory
Address
Register:
500
Memory
Data
Register:
LDA 1000
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Memory Data Register (MDR or
MBR)
The Memory Data Register can contain both instructions and data. At this
stage, an instruction has been fetched and is being stored here en route to
the Current Instruction Register. The instruction is copied from the memory
location pointed to by the MAR.
MBR [Memory] addressed
(Contents of addressed memory is
copied to the memory buffer register)
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

500
Status
Register
Control Unit Memory
Address
Register:
500
Memory
Data
Register:
LDA 1000
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Current Instruction Register
(CIR)
The Current Instruction Register is used to store the current
instruction to be decoded and executed (copied from the MDR).
CIR [MBR]
(If contents of MBR is an instruction
then it is copied to the Current
Instruction Register)
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

503
Status
Register
Control Unit Memory
Address
Register:
500
Memory
Data
Register:
LDA 1000
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Decoding and executing the
instruction
The instruction in the CIR gets decoded. In this example, the instruction is telling
the processor to load the value in memory location 1000 (03) to the accumulator
(one of the general purpose registers are usually used for the accumulator). As this
happens the Program Counter automatically increments.
PC [PC] + 1
[CIR] decoded and executed
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

503
Status
Register
Control
Unit
Memory
Address
Register:
1000
Memory
Data
Register:
03
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
The Control Unit
The control unit co-ordinates all of these fetch-decode-
execute activities. At each clock pulse, it controls the movement
of data and instructions between the registers, main memory
and input and output devices.
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

503
Status
Register
Control Unit Memory
Address
Register:
1000
Memory
Data
Register:
03
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Status Register
The Status Register stores a combination of bits used to indicate the result of an
instruction. For example one bit will be set to indicate that an instruction has caused an
overflow. Another bit will be set to indicate that the instruction produced a negative result.
The Status Register also indicates whether an interrupt has been received (we will look at
this later).
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

503
Status
Register
Control Unit Memory
Address
Register:
1000
Memory
Data
Register:
03
MAIN
MEMORY
ADDRESS
CONTENTS
500 LDA 1000
503 ADD 1001
506 STO 1002
.
1000 03
1001 04
1002 05
Arithmetic Logic Unit
The Arithmetic Logic Unit carries out any arithmetic and logical operations (calculations
and value comparisons) required by any instruction that is executed. For example
instruction at 503 would require the Arithmetic Logical Unit to add the number in location
1001 to the value already in the accumulator.
R0
R1
R2
R3
R4
R5
Arithmetic
Logic Unit
Current
Instruction
Register:
LDA 1000
Program
Counter:

503
Status
Register
Control Unit Memory
Address
Register:
1000
Memory
Data
Register:
03
Special Purpose Registers
So why use special
purpose registers
for all of this
passing of data and
instructions, rather
than using main
memory?
Hardwired Control
Overview
To execute instructions, the processor must
have some means of generating the control
signals needed in the proper sequence.
Two categories: hardwired control and
microprogrammed control
Hardwired system can operate at high speed;
but with little flexibility.
Control Unit Organization
Figure 7.10. Control unit organization.
CLK
Clock
Control step
IR
encoder
Decoder/
Control signals
codes
counter
inputs
Condition
External
Detailed Block Description
External
inputs
Fi gure 7.11. Separati on of the decodi ng and encodi ng functi ons.
Encoder
Reset CLK
Clock
Control signals
counter
Run End
Condition
codes
decoder
Instruction
Step decoder
Control step
IR
T1 T2 Tn
INS1
INS2
INSm
Generating Z
in
Z
in
= T
1
+ T
6
ADD + T
4
BR +
Figure 7.12. Generation of the Z
in
control signal for the processor in Figure 7.1.

T
1
Add
Branch
T
4
T
6
Generating End
End = T
7
ADD + T
5
BR + (T
5
N + T
4
N) BRN +
Fi gure 7.13. Generati on of the End control si gnal .
T7
Add Branch
Branch<0
T5
End
N N
T4 T5
A Complete Processor
Instruction
unit
Integer
unit
Floating-point
unit
Instruction
cache
Data
cache
Bus interf ace
Main
memory
Input/
Output
Sy stem b us
Processor
Fi gure 7.14. Bl ock di agram of a compl ete processor .
Microprogrammed
Control
Microprogrammed Control
Control signals are generated by a program similar to machine
language programs.
Control Word (CW); microroutine; microinstruction
P
Ci n
P
Co u t
M
A
R
i n
R
e a d
M
D
Ro u t
I R
i n
Y
i n
S
e l e c t
A
d d
Zi n
Z
o u t
R
1o u t
R
1i n
R
3o u t
W
M
F
C
E
n d
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
Micro -
instruction
1
2
3
4
5
6
7
Fi gure 7.15 An exampl e of mi croi nstructi ons for Fi gure 7.6.
: Textbook page430
Overview
Step Action
1 PCout , MARin , Read, Sel ect4,Add, Zin
2 Zout , PCin , Yin , WMF C
3 MDRout , IRin
4 R3out , MARin , Read
5 R1out , Yin , WMF C
6 MDRout , Sel ectY,Add, Zin
7 Zout , R1in , End
Fi gure7.6. Control sequencefor executi onof the i nstructi on Add (R3),R1.
Textbook page 421
Basic organization of a
microprogrammed control unit
Control store
Fi gure 7.16. Basi c organi zati on of a mi croprogrammed control uni t.
store
Control
generator
Starting
address
CW
Clock PC
IR
One function
cannot be carried
out by this simple
organization.
Conditional branch
The previous organization cannot handle the situation when the control
unit is required to check the status of the condition codes or external
inputs to choose between alternative courses of action.
Use conditional branch microinstruction.
Address Microinstruction
0 PC
out
, MAR
in
, Read, Select4, Add, Z
in
1 Z
out
, PC
in
, Y
in
, WMF C
2 MDR
out
, IR
in
3 Branch to starting address of appropriate microroutine
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25 If N=0, then branch to microinstruction 0
26 Offset-field-of-IR
out
, SelectY, Add, Z
in
27 Z
out
, PC
in
, End
Figure 7.17. Microroutine for the instruction Branch<0.
Microprogrammed Control
Figure 7.18. Organization of the control unit to allow
conditional branching in the microprogram.
Control
store
Clock
generator
Starting and
branch address
Condition
codes
inputs
External
CW
IR
P C
Microinstructions
A straightforward way to structure
microinstructions is to assign one bit position
to each control signal.
However, this is very inefficient.
The length can be reduced: most signals are
not needed simultaneously, and many signals
are mutually exclusive.
All mutually exclusive signals are placed in
the same group in binary coding.
Partial Format for the
Microinstructions
F2 (3 bits)
000: No transf er
001: PCin
010: IRin
011: Zin
100: R0in
101: R1in
110: R2in
111: R3in
F1 F2 F3 F4 F5
F1 (4 bits) F3 (3 bits) F4 (4 bits) F5 (2 bits)
0000: No transf er
0001: PCout
0010: MDRout
0011: Zout
0100: R0out
0101: R1out
0110: R2out
0111: R3out
1010: TEMPout
1011: Of f set out
000: No transf er
001: MARin
010: MDRin
011: TEMPin
100: Yin
0000: Add
0001: Sub
1111: XOR
16 ALU
f unctions
00: No action
01: Read
10: Write
F6 F7 F8
F6 (1 bit) F7 (1 bit) F8 (1 bit)
0: SelectY
1: Select4
0: No action
1: WMFC
0: Continue
1: End
Fi gure 7.19. An exampl e of a parti al format for fi el d-encoded mi croi nstructi ons.
Microinstruction
What is the price paid for
this scheme?
Require a little more hardware
Further Improvement
Enumerate the patterns of required signals in
all possible microinstructions. Each
meaningful combination of active control
signals can then be assigned a distinct code.
Vertical organization
Horizontal organization
Textbook page 434
Microprogram Sequencing
If all microprograms require only straightforward
sequential execution of microinstructions except for
branches, letting a PC governs the sequencing
would be efficient.
However, two disadvantages:
Having a separate microroutine for each machine instruction results
in a large total number of microinstructions and a large control store.
Longer execution time because it takes more time to carry out the
required branches.
Example: Add src, Rdst
Four addressing modes: register, autoincrement,
autodecrement, and indexed (with indirect forms).
- Bit-ORing
- Wide-Branch Addressing
- WMFC
Textbook page 436
OP code 0 1 0 Rsrc Rdst
Mode
Contents of IR
0 3 4 7 8 10 11
Figure 7.21. Microinstruction for Add (Rsrc)+,Rdst.
Note: Microinstruction at location 170 is not executed for this addressing mode.
Address Microinstruction
(octal)
000 PC
out
, MAR
in
, Read, Select 4 , Add, Z
in
001 Z
out
, PC
in
, Y
in
, WMFC
002 MDR
out
, IR
in
003 Branch { PC 101 (from Instruction decoder);
PC
5,4
[IR
10,9
]; PC
3

121 Rsrc
out
, MAR
in
, Read, Select4, Add, Z in
122 Z
out
, Rsrc
in
123
170 MDR
out
, MAR
in
, Read, WMFC
171 MDR
out
, Y
in
172 Rdst
out
, SelectY , Add, Z
in
173 Z
out
, Rdst
in
, End
[IR
10
] [IR
9
] [IR
8
]}
Branch { PC

170; PC
0

[IR
8
]}, WMFC
Textbook page 439
Microinstructions with Next-
Address Field
The microprogram we discussed requires several
branch microinstructions, which perform no useful
operation in the datapath.
A powerful alternative approach is to include an
address field as a part of every microinstruction to
indicate the location of the next microinstruction to
be fetched.
Pros: separate branch microinstructions are virtually
eliminated; few limitations in assigning addresses to
microinstructions.
Cons: additional bits for the address field (around
1/6)
Microinstructions with Next-
Address Field
Fi gure 7.22. Mi croi nstructi on-sequenci ng organi zati on.
Condition
codes
IR
Decoding circuits
Control store
Next address
Microinstruction decoder
Control signals
Inputs
External
AR
I R
F1 (3 bits)
000: No transf er
001: PCout
010: MDRout
011: Zout
100: Rsrc out
101: Rdst out
110: TEMPout
F0 F1 F2 F3
F0 (8 bits) F2 (3 bits) F3 (3 bits)
000: No transf er
001: PCin
010: IRin
011: Zin
100: Rsrc in
000: No transf er
001: MARin
F4 F5 F6 F7
F5 (2 bits) F4 (4 bits) F6 (1 bit)
0000: Add
0001: Sub
0: SelectY
1: Select4
00: No action
01: Read
Microinstruction
Address of next
microinstruction
101: Rdst in
010: MDRin
011: TEMPin
100: Yin
1111: XOR
10: Write
F8 F9 F10
F8 (1 bit)
F7 (1 bit)
F9 (1 bit) F10 (1 bit)
0: No action
1: WMFC
0: No action
1: ORindsrc
0: No action
1: ORmode
0: NextAdrs
1: InstDec
Fi gure 7.23. Format for mi croi nstructi ons i n the exampl e of Secti on 7.5.3.
Implementation of the
Microroutine
(See Fi gure 7.23 for encoded si gnal s.)
Fi gure 7.24. Impl ementati on of the mi crorouti ne of Fi gure 7.21 usi ng a
1
0
1
1 1 1 1 0
0 1 1 1 1 1 0
0 0 1
0 0 1
1
2 1 0
0 0
0
0 0
0
0
0
0
0
0
0
0
0
0
0 0
0
0
0 0
0 0
0 1 0 1
1 1 0
3 7
7
0 0 0 0 0 0 0 0
0 1 1 1 1
1 1 0
0
0
0
1 7
0 7
F9
0
0
0
0
0
0
F10
0
0
0
0
0
0
0 0
0
0
0
0
0
0
F8 F7 F6 F5 F4
0 0 0 0 0 0 0 0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0 1
1
0
0
0 0
1
0
0
0
1 0 0 0 0
0 0 0 0
1 1 0 0 0 0 0
1 0
0
0
0
0
0
0
1
0 0
0
0
0
0
0
0 0 0 1
0 0 0
0 0 0
0 0 1
1 1 0
1 0 0
1 0
F2
1
1 1 0 0 0 0 0 0
1
1
2 2 1
0
1 1 1 1 0
1 1 1 0 0
1
1
2
0
2 1
0
0 0
address
Octal
1 1 1 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
F0 F1
0
0 0 1 0 0
0 1 0
0 1 0
0 1 1
0 0 1
1 1 0
1 0 0
0
0
0
1
1
0
1
F3
next-mi croi nstructi on address fi el d.
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0decoder
Microinstruction
Control store
Next address F1 F2
Other control signals
F10 F9 F8
Decoder
Decoder
circuits Decoding
Condition
External
codes
inputs
Rsrc Rdst IR
Rdstout
Rdstin
Rsrcout
Rsrcin
AR
InstDecout
ORmode
ORindsrc
R15in R15out R0in R0out
Fi gure 7.25. Some detai l s of the control -si gnal -generati ng ci rcui try.
bit-ORing
Further Discussions
Prefetching
Emulation