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    CH 08

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    The document discusses the basic components and operations of a central processing unit (CPU). It describes the fundamental steps to execute an instruction, including fetching the instruction from memory and performing the specified operations. It also explains the different approaches to implement control logic in a CPU, including hardwired control and microprogrammed control.

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    CH 08

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    104 views19 pages
    The document discusses the basic components and operations of a central processing unit (CPU). It describes the fundamental steps to execute an instruction, including fetching the instruction from memory and performing the specified operations. It also explains the different approaches to implement control logic in a CPU, including hardwired control and microprogrammed control.

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    The document discusses the basic components and operations of a central processing unit (CPU). It describes the fundamental steps to execute an instruction, including fetching the instruction from memory and performing the specified operations. It also explains the different approaches to implement control logic in a CPU, including hardwired control and microprogrammed control.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    104 views19 pages

    CH 08

    Uploaded by

    adddata
    The document discusses the basic components and operations of a central processing unit (CPU). It describes the fundamental steps to execute an instruction, including fetching the instruction from memory and performing the specified operations. It also explains the different approaches to implement control logic in a CPU, including hardwired control and microprogrammed control.

    Copyright:

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    of 19

    Chapter 8

    Basic Processing Unit


    Jin-Fu Li
    Department of Electrical Engineering
    National Central University
    Jungli, Taiwan

    Outline
    Fundamental Concepts
    Hardwired Control
    Microprogrammed Control

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Content Coverage
    Main Memory System
    Address

    Data/Instruction

    Central Processing Unit (CPU)


    Operational
    Registers
    Cache
    memory

    Program
    Counter

    Arithmetic
    and
    Logic Unit

    Instruction
    Sets

    Control Unit

    Input/Output System
    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Instruction Execution
    To execute an instruction, the processor has to
    perform the following three steps:
    Step 1: fetch the contents of the memory location pointed by the
    PC. The contents of this location are interpreted as an
    instruction to be executed. Hence, they are loaded into the IR.
    Symbolically, this can be written as IR[[PC]]
    Step 2: assuming that the memory is byte addressable,
    increment the contents of the PC by 4, that is, PC[PC]+4
    Step 3: carry out the actions specified by the instruction in the
    IR

    Step 1 and Step 2fetch phase


    Step 3decode phase, execution phase, and/or write
    phase
    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Single-Bus Organization of the Datapath


    Control signals
    PC

    Address
    lines

    Instruction
    decoder and
    control logic

    MAR

    Memory bus

    MDR

    Data
    lines

    IR

    Constant 4
    R0
    Select

    ALU control
    lines

    R(n-1)

    ALU
    Carry-in

    TEMP
    Z
    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Instruction Execution
    An instruction can be executed by performing
    one or more of the following operations in some
    specified sequence
    Transfer

    a word of data from one processor register to


    another or to the ALU
    Perform an arithmetic or a logic operation and store
    the result in a processor register
    Fetch the contents of a given memory location and
    load them into a processor register
    Store a word of data from a processor register into a
    given memory location

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Register Transfers
    Riin
    Ri

    Rjout

    1 Riout
    Yin

    Rj

    Y
    Constant 4

    Rjin 1

    Select
    A

    ALU

    Zin
    Z
    Zout
    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Input and Output Gating for 1-bit Register


    Bus

    1
    Riout
    Riin

    Clock

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Arithmetic Operation
    R1in

    Add R3, R1, R2

    R1

    R2out 1

    1 R1out
    1 Yin

    R2

    Y
    Constant 4
    1 Select

    R2in
    1

    R3out

    ALU

    B
    R3

    1 Zin
    R3in 1

    Z
    1 Zout
    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    Fetching a Word from Memory


    Memory data bus

    Internal processor bus

    MDRoutE

    MDRout

    Move (R1), R2
    1. R1out, MARin, Read
    2. MDRinE, WMFC
    3. MDRout, R2in

    MDR

    MDRinE

    Advanced Reliable Systems (ARES) Lab.

    MDRin

    Jin-Fu Li, EE, NCU

    WMFC: is the control


    signal that causes the
    processors control
    circuitry to wait for the
    arrival of the MFC signal.

    10

    Execution of a Complete Instruction


    Ass (R3), R1: adds the contents of a memory
    location pointed to by R3 to register R1.
    Executing this instruction requires the following
    actions:
    Fetch

    the instruction
    Fetch the first operand (the contents of the memory
    location pointed to by R3)
    Perform the addition
    Load the result into R1

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    11

    Control Sequence
    Riin
    Rjout
    Ri
    Rj

    Riout
    Yin

    Rjin

    Instruction fetch

    Constant 4
    Step Action
    Select
    A

    ALU

    Zin
    Z
    Zout
    Advanced Reliable Systems (ARES) Lab.

    1
    2
    3
    4
    5
    6
    7

    PCout, MARin, Read, Select4 Add, Zin


    Zout, PCin, Yin, WMFC
    MDRout, IRin
    R3out, MARin, Read
    R1out, Yin, WMFC
    MDRout, SelectY, Add, Zin
    Zout, R1in, End

    Jin-Fu Li, EE, NCU

    12

    Control
    To execute instructions, the processor must have
    some means of generating the control signals
    needed in the proper sequence. Computer
    designers use a wide variety of techniques to
    solve this problem.
    The approaches used fall into one of two
    categories: hardwired control and
    microprogrammed control

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    13

    Control Unit Organization


    CLK
    Clock

    Control step counter

    External inputs
    IR

    Decoder/encoder
    Conditional
    codes

    Control signals

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    14

    Finite State Machine for Control


    P C W rit e
    P C W rite C o n d
    Io rD
    M em R e ad
    M e m W rite
    IR W rit e
    C o n tro l lo g ic

    M e m to R e g
    P C S o u rce
    ALUOp
    O u tp u ts

    A L U S rc B
    A L U S rc A
    R e g W rite
    R e gD st
    NS3
    NS2
    NS1
    NS0

    I n s tru c tio n re g is te r
    o p c o d e fie ld

    Advanced Reliable Systems (ARES) Lab.

    S0

    S1

    S2

    S3

    Op0

    Op1

    Op2

    Op3

    Op4

    Op5

    In p u ts

    S ta te re g is te r

    Jin-Fu Li, EE, NCU

    15

    PLA Implementation
    Op5
    Op4
    Op3
    Op2
    Op1
    Op0
    S3
    S2
    S1
    S0
    PCWrite
    PCWriteCond
    IorD
    MemRead
    MemWrite
    IRWrite
    MemtoReg
    PCSource1
    PCSource0
    ALUOp1
    ALUOp0
    ALUSrcB1
    ALUSrcB0
    ALUSrcA
    RegWrite
    RegDst
    NS3
    NS2
    NS1
    NS0

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    16

    ROM Implementation
    ROM = "Read Only Memory"
    values

    of memory locations are fixed ahead of time

    A ROM can be used to implement a truth table


    if

    the address is m-bits, we can address 2m entries in the


    ROM.
    our outputs are the bits of data that the address points
    to.
    0 0 0 0 0 1 1
    m

    0
    0
    0
    1
    1
    1
    1

    0
    1
    1
    0
    0
    1
    1

    1
    0
    1
    0
    1
    0
    1

    1
    1
    1
    0
    0
    0
    0

    m is the "height", and n is the "width"


    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    1
    1
    0
    0
    0
    1
    1

    0
    0
    0
    0
    0
    1
    1

    0
    0
    0
    0
    1
    0
    1

    Microprogrammed Control
    Microprogrammed control

    Control signals are generated by a program similar to machine


    language programs
    Control unit

    Microcode memory

    Outputs

    Input

    PCWrite
    PCWriteCond
    IorD
    MemRead
    MemWrite
    IRWrite
    BWrite
    MemtoReg
    PCSource
    ALUOp
    ALUSrcB
    ALUSrcA
    RegWrite
    RegDst
    AddrCtl

    Datapath

    1
    Microprogram counter
    Adder
    Address select logic

    Instruction register
    opcode field

    Advanced Reliable Systems (ARES) Lab.

    Jin-Fu Li, EE, NCU

    18

    Microinstruction format

    Field name
    ALU control

    SRC1

    SRC2

    Value
    Add
    Subt
    Func code
    PC
    A
    B
    4
    Extend
    Extshft
    Read

    ALUOp = 10
    ALUSrcA = 0
    ALUSrcA = 1
    ALUSrcB = 00
    ALUSrcB = 01
    ALUSrcB = 10
    ALUSrcB = 11

    Write ALU

    RegWrite,
    RegDst = 1,
    MemtoReg = 0
    RegWrite,
    RegDst = 0,
    MemtoReg = 1
    MemRead,
    lorD = 0
    MemRead,
    lorD = 1
    MemWrite,
    lorD = 1
    PCSource = 00
    PCWrite
    PCSource = 01,
    PCWriteCond
    PCSource = 10,
    PCWrite
    AddrCtl = 11
    AddrCtl = 00
    AddrCtl = 01
    AddrCtl = 10

    Register
    control
    Write MDR

    Read PC
    Memory

    Read ALU
    Write ALU
    ALU

    PC write control

    ALUOut-cond
    jump address

    Sequencing

    Signals active
    ALUOp = 00
    ALUOp = 01

    Seq
    Fetch
    Dispatch 1
    Dispatch 2

    Advanced Reliable Systems (ARES) Lab.

    Comment

    Cause the ALU to add.


    Cause the ALU to subtract; this implements the compare for
    branches.
    Use the instruction's function code to determine ALU control.
    Use the PC as the first ALU input.
    Register A is the first ALU input.
    Register B is the second ALU input.
    Use 4 as the second ALU input.
    Use output of the sign extension unit as the second ALU input.
    Use the output of the shift-by-two unit as the second ALU input.
    Read two registers using the rs and rt fields of the IR as the register
    numbers and putting the data into registers A and B.
    Write a register using the rd field of the IR as the register number and
    the contents of the ALUOut as the data.
    Write a register using the rt field of the IR as the register number and
    the contents of the MDR as the data.
    Read memory using the PC as address; write result into IR (and
    the MDR).
    Read memory using the ALUOut as address; write result into MDR.
    Write memory using the ALUOut as address, contents of B as the
    data.
    Write the output of the ALU into the PC.
    If the Zero output of the ALU is active, write the PC with the contents
    of the register ALUOut.
    Write the PC with the jump address from the instruction.
    Choose the next microinstruction sequentially.
    Go to the first microinstruction to begin a new instruction.
    Dispatch using the ROM 1.
    Dispatch using the ROM 2.

    Jin-Fu Li, EE, NCU

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