Janusz Rajski Nilanjan Mukherjee: Mentor Graphics Corporation

Janusz Rajski Nilanjan Mukherjee
Mentor Graphics Corporation
Presenters and authors

Presenters: Janusz Rajski
Nilanjan Mukherjee
Mentor Graphics Corporation [email protected]
Co-author:
Jerzy Tyszer Poznan Univ. of Technology
Tutorial ground rules
Definition: Embedded Test refers to design-fortestability techniques where testing is accomplished entirely or partially through on-chip hardware. Disclaimer: This tutorial is not intended to endorse or discredit any commercial technology or product.
Audience
Everybody interested in state-of-the-art embedded test technology, to reduce the cost of manufacturing test
In particular:

Designers of complex integrated circuits IP core providers and integrators Test engineers EDA tools developers EDA tools users Researchers Project managers
Tutorial objectives
To present: Compelling reasons for ET adoption Common barriers for ET adoption State-of-the-art ET fundamentals and practice Architectures for logic and memory BIST Embedded deterministic techniques At-speed ET

multiple-clock domain designs multi-frequency designs
Tools for BIST synthesis automation Application examples and case studies
Outline

Introduction Embedded stimuli generators Compactors of test responses Logic BIST Deterministic forms of embedded test Embedded at-speed test Comparison of scan/ATPG, logic BIST and embedded forms of deterministic test BIST schemes for embedded memory arrays Summary of embedded test
Design characteristics
DSP core IP core Memory ASIC Memory ASIC
CPU core
I/0 IP core PLL
Memory Memory Memory
ASIC Analog ASIC
System on Chip characteristics
System architecture
Microprocessors, DSP cores Buses, peripherals, memory ASIC portion

CPU core
DSP core IP core
ASIC
Memory
ASIC
Memory
Structures: Logic, memory, analog Multiple embedded memories: DRAM, Flash, CAM Analog and mixed signal: PLLs, clock recovery Field programmable logic RF cores: wireless receivers IP cores and reusable blocks available from multiple vendors Design efficiency achieved by hierarchical core-based design style
I/0
IP core
Memory Memory Memory
ASIC
Analog
ASIC
PLL
New defects

Geometries shrink at 30% every three years Defect sizes do not shrink in proportion Increase of wiring levels from 6 to 9 Interconnect delays dominate Gate delays reduced Bridging faults
Sematech S-121
Test Method Evaluation Key Findings & Conclusions Objective: Evaluate various test methodologies

Large sample size Extensive data collection & analysis
[Sematech, 1998]
Sematech S-121

Device 116K equivalent gates 0.45 m L effective (0.8 m drawn) 50 MHz operating speed 249 signal I/Os 3 metal levels Full LSSD Scan plus JTAG boundary scan
8 Chains, 5,280 master/slave LSSD latches (10,560 total latches)
Sample size 20,000 units Test methods:
Stuck-at faults, Functional tests, Transition delay faults & IDDQ
Sematech S-121
Package test results (pre Burn-in)

7 FUNC 6 0 1
IDDQ 1463 8 13
1251
SAF - 99.5% coverage (8300 patterns)
FUNC - 52% SAF coverage (532K cycles)

Delay - 90% Transition coverage (15232 patterns) IDDQ - >96% pseudo SAF coverage (195 patterns)
36
SAF 6
FUNC
52 14
Delay 34
IDDQ
S-121 Conclusions

All test methods detected unique defects Near 100% SAF coverage missed many defects Large defect coverage overlap between SAF & Delay
SAF are a subset of Transition faults
IDDQ threshold setting significantly affects yield
98% of the IDDQ fails survived burn-in

But diminishing IDDQ effectiveness in DSM
Many (bridging) defects detected only by IDDQ
Some Functional tests are still required Opportunity to optimize test coverage levels & capital
Process Shrinks vs. Defect Types

Defect Pareto 350 nm
Unknown BridgeM1-2 Via break Bridge M2 Bridge M4 Break trans Bridge Poly M2 Bridge M3 Bridge M1-3 Bridge poly M1 Bridge M3-4 Open Poly Open Contact Bridge M1 Unknown Br Break M3 Bridge Poly M2 Break M2 Bridge M3-4 Break M1 Bridge Poly M4 Bridge Poly
350 nm Process 5 million Transistors
Al 4-5 Levels
W Plugs Oxide Dielectric
A Transistor
Process Shrinks vs. Defect Types

Defect Pareto 100 nm
100 nm Process -- 250 million transistors
Unknown
Cu (8 Levels)
Low-K Dielectric
Defect distribution change with process
Cu Plugs
A Transistor
Defects vs. Fault Coverage

Wired
AND & OR models are not sufficient Speed limiting defects Frequency of bridging defects is increasing Need to drive ATE & modeling requirements from the defects to be detected Will drive need for more scan vectors
Bridge Defect Observed Resistance

.18 um .25 um
Test chip FA results
10
100
1000
K-Ohms
Increasing defect populations causing more V , Temp, & freq sensitive device fails DD
[M. Rodgers , et. al. DAC 2000]
Quality requirements
Escapes
1-p
Faults detected
1-Y
Quality requirements
Escapes = (1 - Y)(1 - p)
0.01 0.009 0.008 0.007 0.006 0.005 0.004 0.003 0.002 0.001 0
0.990 0.991 0.992 0.993 0.994 0.995 0.996 0.997 0.998 0.999 1.000
Yield = 0.9
Yield = 0.1
Fault models
Stuck-at-0 and stuck-at-1 Transitions Path delay

Multiple detects
VDD
Very high test quality

Very high fault coverage Wide range of fault models
stuck-at transition path delay at-speed testing multiple detects bridging defect based cross-talk effects ... fading IDDQ
Coverage
Escapes
High-performance MPU/ASIC gate count

Gate count
300 250
ITRS Roadmap 2001

200 150 100 50 0 2001 2002 2003 2004 2005 2006 2007
Scan chains
The pattern count for transition faults may reach 20,000
Scan test
Primary outputs
Scan input channels
Primary inputs
ATE
Scan output channels
ATE cost
Tester cost = b + S m p
b - base cost (zero pins) m - incremental cost per pin p - number of pins
b [ K$ ]
Test cost can be $0.05/second
m[$] 2700 - 6000 150 - 650 1200 - 2500
p 512 512 - 2500 256 - 1024
High performance ASIC / MPU

DFT tester Low performance Microcontroller
250 - 400 100 - 350 200 - 350
Volume of scan test data
Test cycles =
Scan cells Patterns Scan chains
...
Scan test time
Scan cells Patterns Test time = Scan chains Frequency
...
Scan test cost

Gate count Scan chains Padding ratio Scan patterns 10M 32 1.4 20K 500,000 15,625 21,875 437.5M Scan cells Cells per scan Longest scan chain Cycles
Shift frequency
Vector memory Reload penalty Insertions Tester rate
20 MHz
64MV 2s 4 0.05$
21.9s
6 12.0s 87.5s 4.4$
Scan test time

Passes Reload time Time pre device Cost per device
More
High-performance MPU/ASIC
Required ATE memory Gigabits/channel
12 10 8 6 4 2 0 2001 2002 2003 2004 2005 2006 2007
32 channels 20,000 patterns
High-performance MPU/ASIC
Scan test time seconds
120 100
100 MHz scan shift

80 60 40 20 0 2001 2002 2003 2004 2005 2006 2007
ATE accuracy vs. device speed

Tester accuracy will improve from 200 ps to 175 ps by 2012 Clock period will decrease to 330 ps Margin of error for ATE approaches 50% clock period
600
500
400
300
Device period
200
100
ATE accuracy Accuracy required

2001 2002 2003 2004 2005 2006 2007
Requirements for Embedded Test
Increasing device complexity, operating speed, and new fault models stress conventional scan based test:

Exploding volume of test data Increasing scan test time, and Escalating scan test cost
Embedded Test is required to:
Generate most of the test data on-chip Compacting test responses on-chip, and Providing on-chip control for at-speed test
Very low cost

Dramatically reduced volume of test data (10-100X) Dramatically reduced scan test time (10-400X)
10X 2M gates Scan/ATPG
16 scan chains 5k vectors 2s handler/index time 1 test 10MHz scan shift
ATE Memory 35 [Mvectors] 30
25 20 15 10 5 0 0 1
10X
2 3 4 5 6 7 Scan test time[s]
Long term scalability

100X increase in 10 years!
100
10
Volume in conventional DFT
0.1 0 1.5 3 4.5 6 7.5 9 10.5
years
Radical compression is required!

Immediate 5-10X compression Compression ahead of volume for 10 years
100
Compression factor
10

1
0.1 0 1.5 3 4.5 6 7.5 9 10.5
years
Radical compression is required

100
Compression should be ahead of Moores law for 10 years!
Compression factor
10

1
Compressed volume
0.1 0 1.5 3 4.5 6 7.5 9 10.5
years

Janusz Rajski Nilanjan Mukherjee: Mentor Graphics Corporation

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Janusz Rajski Nilanjan Mukherjee: Mentor Graphics Corporation

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Janusz Rajski Nilanjan Mukherjee

Mentor Graphics Corporation

Presenters and authors

Tutorial ground rules

multiple-clock domain designs multi-frequency designs

I/0 IP core PLL

Memory Memory Memory

ASIC Analog ASIC

System on Chip characteristics

Microprocessors, DSP cores Buses, peripherals, memory ASIC portion

DSP core IP core

Memory Memory Memory

Large sample size Extensive data collection & analysis

8 Chains, 5,280 master/slave LSSD latches (10,560 total latches)

Sample size 20,000 units Test methods:

Stuck-at faults, Functional tests, Transition delay faults & IDDQ

Package test results (pre Burn-in)

SAF - 99.5% coverage (8300 patterns)

FUNC - 52% SAF coverage (532K cycles)

SAF are a subset of Transition faults

IDDQ threshold setting significantly affects yield

98% of the IDDQ fails survived burn-in

Many (bridging) defects detected only by IDDQ

Process Shrinks vs. Defect Types

350 nm Process 5 million Transistors

W Plugs Oxide Dielectric

Process Shrinks vs. Defect Types

Defect distribution change with process

Defects vs. Fault Coverage

Bridge Defect Observed Resistance

[M. Rodgers , et. al. DAC 2000]

Stuck-at-0 and stuck-at-1 Transitions Path delay

Very high test quality

Very high fault coverage Wide range of fault models

High-performance MPU/ASIC gate count

ITRS Roadmap 2001

The pattern count for transition faults may reach 20,000

Scan input channels

Scan output channels

Test cost can be $0.05/second

m[$] 2700 - 6000 150 - 650 1200 - 2500

p 512 512 - 2500 256 - 1024

High performance ASIC / MPU

250 - 400 100 - 350 200 - 350

Volume of scan test data

Scan cells Patterns Scan chains

Scan test time

Scan cells Patterns Test time = Scan chains Frequency

Scan test cost

Scan test time

12 10 8 6 4 2 0 2001 2002 2003 2004 2005 2006 2007

32 channels 20,000 patterns

100 MHz scan shift

ATE accuracy vs. device speed

ATE accuracy Accuracy required

Requirements for Embedded Test

Embedded Test is required to:

Very low cost