Utc Tea1062/1062A Linear Integrated Circuit: Low Voltage Telephone Transmission Circuit With Dialler Interface
Utc Tea1062/1062A Linear Integrated Circuit: Low Voltage Telephone Transmission Circuit With Dialler Interface
Utc Tea1062/1062A Linear Integrated Circuit: Low Voltage Telephone Transmission Circuit With Dialler Interface
SOP-16
operate down to D.C. line voltage of 1.6V (with reduced performance) to facilitate the use of more telephone sets in parallel.
DIP-16
FEATURES
* Low d.c. line voltage; operates down to 1.6V (excluding polarity guard). *Voltage regulator with adjustment static resistance. *Provides supply with limited current for external circuitry. *Symmetrical high-impedance inputs (64k)for dynamic, magnetic or piezoelectric microphones. *Asymmetrical high-impedance inputs (32k)for electret microphones. *DTMF signal input with confidence tone. *Mute input for pulse or DTMF dialing. *Receivering amplifier for several types of earphones. *Large amplification setting range on microphone and earpiece amplifiers. *Line loss compensation facility , line current depedant (microphone and earpiece amplifiers). *Gain control adaptable to exchange supply. *Possibility to adjust the d.c. line voltage.
typ. typ.
1.8mA 0.7mA
UTC
QW-R108-001,A
MIC+ 7 MIC6
2 GAS1
3 GAS2 DTMF 11
dB
MUTE 12 SUPPLY AND REFERENCE CONTROL CURRENT CURRENT REFERENCE 9 VEE 14 REG 15 AGC 8 STAB LOW VOLTAGE CIRCUIT
16 SLPE
Fig.1
Block Diagram
LN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SLPE AGC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
LN GAS1 GAS2 QR GAR MICMIC+ STAB VEE IR DTMF MUTE Vcc REG AGC SLPE
positive line terminal gain adjustment; transmitting amplifier gain adjustment; transmitting amplifier non-inverting output,receiving amplifier gain adjustment; receiving amplifier inverting microphone input on-inverting microphone input current stabilizer negative line terminal receiving amplifier input dual-tone multi-frequency input mute input positive supply decoupling voltage regulator decoupling automatic gain control input slope (DC resistance) adjustment
Fig.2
PIN CONFIGURATIONS
UTC
QW-R108-001,A
MIN
MAX
12 13.2
UNIT
V V
VLN 28 V Iline 140 mA Vi VCC+0.7 V -Vi 0.7 V Total Power Dissipation(2) R9=20 Ptot 640 mW Storage Temperature Range Tstg -40 +125 C Operating Ambient Temperature Range Tamb -25 +75 C Junction Temperature Tj +125 C 1. Mostly dependent on the maximum required Tamb and the voltage between LN and SLPE (see Figs 6 ). 2. Calculated for the maximum ambient temperature specified Tamb=75C and a maximum junction temperature of 125C. Line Current (1) Voltage on All Other Pins
THERMAL RESISTANCE
From junction to ambient in free air Rth j-a = 75K/W
TEST CONDITIONS
SYMBOL
MIN
TYP
MAX
UNIT
Variation with Temperature Voltage Drop Over Circuit, between LN and VEE with External Resistor RVA
MIC inputs open Iline=1mA Iline=4mA Iline=15mA Iline=100mA Iline=140mA Iline=15mA Iline=15mA RVA(LN to REG) =68k Iline=15mA RVA(REG to SLPE) =39k VCC=2.8V Iline=15mA Ip=1.2mA;MUTE=HIGH lp=0mA;MUTE=HIGH Ip=1.2mA;MUTE=LOW lp=0mA;MUTE=LOW
3.55 4.9
V V V V V mV/K
3.5
V mA
Supply Current Supply Voltage Available for Peripheral Circuitry TEA1062 TEA1062A
2.2 2.2
V V V V
UTC
QW-R108-001,A
SYMBOL
MIN
TYP
MAX
UNIT
64 32 82
k k dB
Gv Gvf
50.5
52.0 +-0.2
53.5
dB dB
w.r.t.25C without R6; Iline=50mA Dual-tone multi-frequency input DTMF (pin 11) Input impedance Voltage Gain from DTMF to LN Iline=15mA R7=68k Gain Variation with Frequency at f=300Hz and f=3400Hz w.r.t.800Hz Gain Variation with Temperature at -25C and +75C w.r.t.25C Iline=50mA
GvT Zi Gv Gvf 24
dB k dB dB
GvT
+-0.2
dB
Gv Iline=15mA THD=10% Iline=4mA THD=10% Iline=15mA; R7=68k; 200 between MIC- and MIC+; psophometrically weighted
-8
dB
VLN(rms) VLN(rms)
1.7
2.3 0.8
V V
VNO(rms) Zi Zo
-69 21 4
dBmp k
Gv
29.5
31
32.5
dB
UTC
QW-R108-001,A
TEST CONDITIONS
w.r.t.800Hz w.r.t.25C without R6 Iline=50mA sinwave drive; Ip=0mA;THD=2% R4=100k Iline=15mA RL=150 RL=450 THD=10% R4=100k RL=150 Iline=4mA Iline=15mA R4=100k IR open-circuit psophometrically weighted RL=300
SYMBOL
Gvf
MIN
TYP
0.2
MAX
UNIT
dB
GvT
+-0.2
dB
Output Voltage
VO(rms) VO(rms)
0.22 0.3
0.33 0.48
V V
Output Voltage
VO(rms)
15
mV
VNO(rms)
50
Gv
-11
dB
Reduction of Gain
MIC+ or MIC- to QR Voltage Gain from DTMF to QR
Gv
-19
dB
Controlling the Gain from lR to QR and the Gain from MIC+/MICto LN;R6 between AGC and VEE Gain Control Range Highest Line Current for Maximum Gain Minimum Line Current for Minimum Gain
R6=110k Iline=70mA
Gv Iline Iline
-5.8 23 61
dB mA mA
UTC
QW-R108-001,A
Microphone inputs(MIC+ and MIC-) and gain pins (GAS1 and GAS2)
The UTC TEA1062/1062A has symmetrical inputs. Its input impedance is 64k (2*32k) and its voltage gain is typically 52 dB (when R7=68k.see Fig.13). Dynamic, magnetic, piezoelectric or electret (with built-in FET source followers) can be used. Microphone arrangements are illustrated in Fig.10. The gain of the
UTC
QW-R108-001,A
Side-tone suppression
The anti-sidetone network, R1//Zline, R2, R3, R8, R9 and Zbal,(see Fig.4) suppresses the transmitted signal in the earpiece. Compensation is maximum when the following conditions are fulfilled: (a) R9*R2=R1[R3+(R8//Zbal)]; (b) [Zbal/(Zbal+R8)]=[Zline/(Zline+R1)]; If fixed values are chosen for R1, R2, R3 and R9 then condition(a) will always be fullfilled when R8/ZballR3. To obtain optimum side-tone suppression condition(b) has to be fulfilled which results in: Zbal=(R8/R1) Zline=k*Zline where k is a scale factor; K=(R8/R1). The scale factor (k), dependent on the value of R8, is chosen to meet following criteria: (a) Compatibility with a standard capacitor from the E6 or E12 range for Zbal, (b)Zbal//R8R3 fulfilling condition (a) and thus ensuring correct anti-sidetone bridge operation, (c) Zbal+R8R9 to avoid influencing the transmitter gain. In practice Zline varies considerably with the type and length. The value chosen for Zbal should therefore be for an average line length thus giving optimum setting for short or long lines.
Example The balance impedance Zbal at which the optimum suppression is present can be calculated by: Suppose Zline = 210+(1265//140nF) representing a 5km line of 0.5 mm diameter, copper, twisted pair cable matched to 600(176/km;38nF/km). When k=0.64
UTC
QW-R108-001,A
R1 VCC C1
100 F
Rp=16.2k Leq=C3*R9*Rp
VEE
Fig.3 Equivalent impedance circuit
The anti-sidetone network for the UTCTEA1062/1062A family shown in Fig.4 attenuates the signl received from the line by 32 dB before it enters the receiving amplifier. The attenuation is almost constant over the whole audio frequency range. Fig.5 shows a convertional Wheatstone bridge anti-sidetone circuit that can be used as an alternative. Both bridge types can be used with either resistive or complex set impedances.
Zline
R1
R2
Zline
R1
R2
im VEE
R9 R8
IR
R3 Rt
im VEE
R9 R8
IR
Rt
SLPE
Zbal
RA SLPE
UTC TEA1062/1062A
Fig 5
UTC
QW-R108-001,A
110
(1)
90
(2)
70
50
30
VLN-VSLPE(V)
Rline
Iline
R1
ISLPE + 0.5mA
LN
VCC 0.5mA C1
PERIPHERAL CIRCUITS
Rexch
DC AC
REG
STAB
SLPE
VEE
Vexch C3
R5
ISLPE
R9
UTC
QW-R108-001,A
Ip (mA) b
1.6
0.8
0 0 1 2 3 4
(a) Ip=2.1mA (b) Ip=1.7mA Iline=15mA at V LN=4V R1=620 and R9=20 Vcc(V)
5
Fig.9
curve
(a) is valid when the receiving amplifier is not driven or when MUTE =LOW(UTC TEA1062 is HIGH) .curve(b) is valid when MUTE=HIGH(UTC TEA1062 is LOW) and the receiving amplifier is
driven;Vo(rms)=150mV,RL=150.The supply possibilities can be increased simply by setting the voltage drop over the circuit VLN to a high value by means of resistor RVA connected between REG and SLPE.
7 MIC+ (1) 7 13 7 MIC+ 6 MIC6 MICMIC+
VCC
VEE
9
MIC-
(a)
(b)
Fig. 10 Alternative microphone arrangement
(c)
(a) Magnetic or dynamic microphone. The resistor marked(1) may be connected to decrease the terminating impedance. (b) Electret microphone. (c) Piezoelectric microphone.
UTC
10
QW-R108-001,A
QR 4
(2)
VEE 9
VEE 9
VEE 9
(a)
(b)
Fig.11 Alternative receiver arrangement
(c)
(a) Dynamic earpiece. (b) Magnetic earpiece.The resistor marked(1) may be connected to prvent distortion(inductive load) (c) Piezoelectric earpiece.The earpiece marked(2) is requirred to increase the phase margin (capacitive load) Fig.12 Variation of gain with line urrent,with R6 as a parameter.
Gv (dB) R6= 0 -2 -4 -6 0 20 40 60 80 100 120 140 Iline (mA)
Rexch()
400
600 R6(k)
800
1000
36
100 140
78.7 110
93.1
82
Vexch(V)
Table 1
48
60 120 102 Values of resistor R6 for optimum line loss compensation,for various usual values of exchange supply vloltage(Vexch) and exchange feeding bridge resistance(Rexch);R9=20.
UTC
11
QW-R108-001,A
1
LN QR
100 F
4 5 2
R7 68k R4 100k
C4 100pF C7 1nF
RL 600 10 TO 140 mA
GAR GAS1
Vo
10 F
C8 1nF C6 100pF
Vi
C3 4.7 F
14
R6
15 8
R5 3.6k
16
R9 20
Fig.13 Test circuit defining voltage gain of MIC+,MIC- and DTMF inputs. Voltage gain is defined as : GV=20*log(|VO/Vi|).For measuring the gain from MIC+ and MIC- the MUTE input should be HIGH(UTC TEA1062 is LOW) or open-circuit, for measuring the DTMF input MUTE should be LOW(UTC TEA1062 is HIGH) .Inputs not under test should be open-circuit.
R1=620 13
VCC LN QR
1 4
R4 100k
10 IR 7 MIC+
C1 100F
C4 Vo 100pF C7 1nF
6 MIC11 DTMF 12
10 F
R7 68k
C8 1nF C6 100pF
MUTE
VEE REG AGC STAB
Vi
C3 4.7 F
14
R6
15 8
R5 3.6k
16
R9 20
Fig.14 Test circuit for defining voltage gain of the receiving amplifier. Voltage gain is defined as: GV=20*log(|VO/Vi|).
UTC
12
QW-R108-001,A
R2 132k
C5 100nF 10 IR
1 LN
13 VCC
C1 100 F
Telephone Line
C2
BZW14 (x2)
R4 R3 3.92k C7 1nF
C4 QR 100pF
5 GAR 7 6
DTMF
UTC TEAI062/A
MUTE
R8 390
C6 100pF
STAB VEE 8 9
R7 RVA(R16.R14) R5 3.6k
Zbal
R9 20
C8 1nF
C3 4.7 F
R6
Fig.15 Typical application of the UTC TEA1062A ,shown here with a piezoelectric earpiece and DTMF dialling. The bridge to the left ,the Zener diode and R10 limit the current into the circuit and the voltage across the circuit during line transients.Pulse dialling or register recall required a different protection arrangement. The DC line voltage can be set to a higher value by resistor RVA(REG to SLPE).
LN
VCC DTMF
VDD DTMF
CARDLE CONTRAT
UTC1062A
MUTE VEE
dialling circuit
M1 VSS DP/FL
TELEPHONE LINE
BSN254A
Fig.16
Typical applications of the UTC TEA1062/1062A (simplified) The dashed lines show an optional flash ( register recall by timed loop break).
UTC
13
QW-R108-001,A
UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.
UTC
14
QW-R108-001,A