sfp diferencial

SN65HVD10, SN65HVD11, SN65HVD12

SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
SNx5HVD1x 3.3-V RS-485 Transceivers
1 Features 3 Description
• Operates with a 3.3-V supply The SN65HVD10, SN75HVD10, SN65HVD11,
• Bus-pin ESD protection exceeds 16-kV HBM SN75HVD11, SN65HVD12, and SN75HVD12 bus
• 1/8 Unit-load option available (up to 256 nodes on transceivers all combine a 3-state differential line
the bus) driver, as well as a differential input line receiver
• Optional driver output transition times for signaling that operates with a single 3.3-V power supply. They
rates 1of 1 Mbps, 10 Mbps, and are designed for balanced transmission lines and
32 Mbps meet or exceed ANSI standard TIA/EIA-485-A and
• Meets or exceeds the requirements of ANSI TIA/ ISO 8482:1993. These differential bus transceivers
EIA-485-A are monolithic integrated circuits, designed for
• Bus-pin short-circuit protection from –7 V to bidirectional data communication on multipoint bus-
12 V transmission lines. The drivers and receivers have
• Low-current standby mode: 1 µA, typical active-high and active-low enables, that can be
• Open-circuit, idle-bus, and shorted-bus fail-safe externally connected together to function as direction
receiver control. Very low device standby supply current, can
• Thermal shutdown protection be achieved by disabling the driver and the receiver.
• Glitch-free power-up and power-down protection
The driver differential outputs and receiver differential
for hot-plugging applications
inputs connect internally to form a differential input/
• SN75176 footprint
output (I/O) bus port, that is designed to offer
2 Applications minimum loading to the bus whenever the driver is
disabled or VCC = 0. These parts feature wide positive
• Digital motor control
and negative common-mode voltage ranges, making
• Utility meters
them suitable for party-line applications.
• Chassis-to-chassis interconnects
• Electronic security stations Device Information
• Industrial process control PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Building automation SN65HVD10
• Point-of-sale (POS) terminals and networks SN65HVD11 SOIC (8) 4.90 mm × 3.91 mm
SN65HVD12
SN75HVD10
SN75HVD11 PDIP (8) 9.81 mm × 6.35 mm
SN75HVD12
(1) For all available packages, see the orderable addendum at

the end of the data sheet.
R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B
R R
D D
R RE DE D R RE DE D
Copyright © 2016, Texas Instruments Incorporated
Typical Application Diagram
1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022 www.ti.com
Table of Contents
1 Features............................................................................1 9.2 Functional Block Diagram......................................... 17
2 Applications..................................................................... 1 9.3 Feature Description...................................................17
3 Description.......................................................................1 9.4 Device Functional Modes..........................................17
4 Revision History.............................................................. 2 10 Application and Implementation................................ 19
5 Device Comparison Table...............................................3 10.1 Application Information........................................... 19
6 Pin Configuration and Functions...................................3 10.2 Typical Application.................................................. 20
7 Specifications.................................................................. 4 11 Power Supply Recommendations..............................23
7.1 Absolute Maximum Ratings........................................ 4 12 Layout...........................................................................23
7.2 ESD Ratings............................................................... 4 12.1 Layout Guidelines................................................... 23
7.3 Recommended Operating Conditions.........................4 12.2 Layout Example...................................................... 24
7.4 Thermal Information....................................................5 12.3 Thermal Considerations..........................................24
7.5 Driver Electrical Characteristics.................................. 5 13 Device and Documentation Support..........................26
7.6 Receiver Electrical Characteristics............................. 6 13.1 Device Support....................................................... 26
7.7 Power Dissipation Characteristics.............................. 6 13.2 Related Links.......................................................... 26
7.8 Driver Switching Characteristics................................. 7 13.3 Receiving Notification of Documentation Updates..26
7.9 Receiver Switching Characteristics.............................8 13.4 Support Resources................................................. 26
7.10 Dissipation Ratings................................................... 8 13.5 Trademarks............................................................. 26
7.11 Typical Characteristics.............................................. 9 13.6 Electrostatic Discharge Caution..............................26
8 Parameter Measurement Information.......................... 11 13.7 Glossary..................................................................26
9 Detailed Description......................................................17 14 Mechanical, Packaging, and Orderable
9.1 Overview................................................................... 17 Information.................................................................... 26
4 Revision History
Changes from Revision O (February 2017) to Revision P (February 2022) Page
• Changed the Thermal Information table............................................................................................................. 5
Changes from Revision N (July 2015) to Revision O (February 2017) Page

• Added MIN value of –55°C to the Storage temperature in Absolute Maximum Ratings ....................................4
Changes from Revision M (July 2013) to Revision N (July 2015) Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device
Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information
section ............................................................................................................................................................... 1
Changes from Revision L (July 2013) to Revision M (July 2013) Page

• Changed the VIT+ TYP value From: –0.65 V To: –0.065 V ................................................................................ 6
Changes from Revision K (September 2011) to Revision L (July 2013) Page

• Added TYP = –0.65 V to VIT+ .............................................................................................................................6
• Added TYP = –0.1 V to VIT– ...............................................................................................................................6
Changes from Revision J (February 2009) to Revision K (September 2011) Page

• Added new section 'LOW-POWER STANDBY MODE', in the Application Information section........................18
2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated
Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

www.ti.com SLLS505P – FEBRUARY 2002 – REVISED FEBRUARY 2022
5 Device Comparison Table

PART NUMBER
SIGNALING RATE UNIT LOADS TA SOIC MARKING
SOIC(1) PDIP
SN65HVD10D SN65HVD10P 32 Mbps 1/2 VP10
SN65HVD11D SN65HVD11P 10 Mbps 1/8 –40°C to 85°C VP11
SN65HVD12D SN65HVD12P 1 Mbps 1/8 VP12
SN75HVD10D SN75HVD10P 32 Mbps 1/2 VN10
SN75HVD11D SN75HVD11P 10 Mbps 1/8 –0°C to 70°C VN11
SN75HVD12D SN75HVD12P 1 Mbps 1/8 VN12
SN65HVD10QD SN65HVD10QP 32 Mbps 1/2 VP10Q
–40°C to 125°C
SN65HVD11QD SN65HVD11QP 10 Mbps 1/8 VP11Q
(1) The D package is available as a tape and reel. Add an R suffix to the part number (that is, SN75HVD11DR) for this option.
6 Pin Configuration and Functions
R 1 8 VCC
RE 2 7 B
DE 3 6 A
D 4 5 GND
Figure 6-1. D, JD, or HKJ Package

8-Pin SOIC or PDIP
(Top View)
Table 6-1. Pin Functions

PIN
TYPE DESCRIPTION
NAME NO.
A 6 Bus input/output Driver output or receiver input (complementary to B)
B 7 Bus input/output Driver output or receiver input (complementary to A)
D 4 Digital input Driver data input
DE 3 Digital input Active-high driver enable
GND 5 Reference potential Local device ground
R 1 Digital output Receive data output
RE 2 Digital input Active-low receiver enable
VCC 8 Supply 3-V to 3.6-V supply
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted (1) (2)
MIN MAX UNIT
VCC Supply voltage –0.3 6 V
Voltage at A or B –9 14 V
Input voltage at D, DE, R, or RE –0.5 VCC + 0.5 V
Voltage input, transient pulse, A and B, through 100 Ω, see Figure 8-12 –50 50 V
IO Receiver output current –11 11 mA
Continuous total power dissipation See Section 7.10
TJ Junction temperature 170 °C
Tstg Storage temperature –55 145 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Section 7.3 is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
7.2 ESD Ratings

VALUE UNIT
Pins 5, 6, and 7 ±16000
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
All pins ±4000
Electrostatic
V(ESD) Charged device model (CDM), per JEDEC specification ±1000 V
discharge All pins
JESD22-C101(2)
Electrical fast transient/burst(3) Pins 5, 6, and 7 ±4000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) Tested in accordance with IEC 61000-4-4.
7.3 Recommended Operating Conditions

over operating free-air temperature range unless otherwise noted
MIN NOM MAX UNIT
VCC Supply voltage 3 3.6
VI or VIC Voltage at any bus terminal (separately or common mode) –7(1) 12
VIH High-level input voltage D, DE, RE 2 VCC V
VIL Low-level input voltage D, DE, RE 0 0.8
VID Differential input voltage See Figure 8-8 –12 12
Driver –60
IOH High-level output current mA
Receiver –8
Driver 60
IOL Low-level output current mA
Receiver 8
RL Differential load resistance 54 60 Ω
CL Differential load capacitance 50 pF
HVD10 32
Signaling rate HVD11 10 Mbps
HVD12 1
TJ (2) Junction temperature 145 °C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) See thermal characteristics table for information regarding this specification.

7.4 Thermal Information

SNx5HVD1xx
THERMAL METRIC(1) D (SOIC) P (PDIP) UNIT
8 Pins 8 Pins
RθJA Junction-to-ambient thermal resistance 116.7 84.3 °C/W
Rθ
Junction-to-case (top) thermal resistance 56.3 65.4 °C/W
JC(top)
RθJB Junction-to-board thermal resistance 63.4 62.1 °C/W

ψJT Junction-to-top characterization parameter 8.8 31.3 °C/W
ψJB Junction-to-board characterization parameter 62.6 60.4 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Driver Electrical Characteristics

Over recommended operating conditions unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
IO = 0 2 VCC
|VOD| Differential output voltage(2) RL = 54 Ω, See Figure 8-1 1.5 V
Vtest = –7 V to 12 V, See Figure 8-2 1.5
Change in magnitude of differential output
Δ|VOD| See Figure 8-1 and Figure 8-2 –0.2 0.2 V
voltage
Peak-to-peak common-mode output
VOC(PP) 400 mV
voltage
VOC(SS) Steady-state common-mode output voltage See Figure 8-3 1.4 2.5 V
Change in steady-state common-mode
ΔVOC(SS) –0.05 0.05 V
output voltage
IOZ High-impedance output current See receiver input currents
D –100 0
II Input current μA
DE 0 100
IOS Short-circuit output current –7 V ≤ VO ≤ 12 V –250 250 mA
C(OD) Differential output capacitance VOD = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V 16 pF
RE at VCC,
Receiver disabled and
D and DE at VCC, 9 15.5 mA
driver enabled
No load
RE at VCC,
Receiver disabled
D at VCC,
ICC Supply current and driver disabled 1 5 μA
DE at 0 V,
(standby)
No load
RE at 0 V,
Receiver enabled and
D and DE at VCC, 9 15.5 mA
driver enabled
No load
(1) All typical values are at 25°C and with a 3.3-V supply.
(2) For TA > 85°C, VCC is ±5%.

7.6 Receiver Electrical Characteristics

VIT+ Positive-going input threshold voltage IO = –8 mA –0.065 –0.01
Negative-going input threshold V
VIT– IO = 8 mA –0.2 –0.1
voltage
Vhys Hysteresis voltage (VIT+ – VIT–) 35 mV
VIK Enable-input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –8 mA, see Figure 8-8 2.4 V
VOL Low-level output voltage VID = –200 mV, IOL = 8 mA, see Figure 8-8 0.4 V
IOZ High-impedance-state output current VO = 0 or VCC, RE at VCC –1 1 μA
VA or VB = 12 V 0.05 0.11
VA or VB = 12 V, VCC = 0 V HVD11, HVD12, 0.06 0.13
mA
VA or VB = –7 V Other inputs at 0 V –0.1 –0.05
VA or VB = –7 V, VCC = 0 V –0.05 –0.04
II Bus input current
VA or VB = 12 V 0.2 0.5
VA or VB = 12 V, VCC = 0 V HVD10, 0.25 0.5
mA
VA or VB = –7 V Other inputs at 0 V –0.4 –0.2
VA or VB = –7 V, VCC = 0 V –0.4 –0.15
IIH High-level input current, RE VIH = 2 V –30 0 μA
IIL Low-level input current, RE VIL = 0.8 V –30 0 μA
CID Differential input capacitance VID = 0.4 sin(4E6πt) + 0.5 V, DE at 0 V 15 pF
RE at 0 V
Receiver enabled and driver
D and DE at 0 V 4 8 mA
disabled
No load
RE at VCC
D at VCC Receiver disabled and driver
ICC Supply current 1 5 μA
DE at 0 V disabled (standby)
No load
RE at 0 V
Receiver enabled and driver
D and DE at VCC 9 15.5 mA
enabled
No load
7.7 Power Dissipation Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
HVD10
198 250
RL= 60 Ω, CL = 50 pF, (32Mbps)
DE at VCC, RE at 0 V,
HVD11
PD Device power dissipation Input to D is a 50% duty-cycle 141 176 mW
(10Mbps)
square wave at indicated signaling
rate HVD12
133 161
(500 kbps)
High-K board, no airflow D pkg –40 116
TA Ambient air temperature(1) °C
No airflow(2) P pkg –40 123
TJSD Thermal shutdown junction temperature(1) 165 °C
(1) See Section 12.3.1 section for an explanation of these parameters.

(2) JESD51−10, Test Boards for Through-Hole Perimeter Leaded Package Thermal Measurements.

7.8 Driver Switching Characteristics

HVD10 5 8.5 16
Propagation delay time,
tPLH HVD11 18 25 40 ns
low-to-high-level output
HVD12 135 200 300
HVD10 5 8.5 16
tPHL HVD11 18 25 40 ns
high-to-low-level output
HVD12 135 200 300
HVD10 3 4.5 10
Differential output signal RL = 54 Ω, CL = 50 pF
tr HVD11 10 20 30 ns
rise time See Figure 8-4
HVD12 100 170 300
HVD10 3 4.5 10
Differential output signal
tf HVD11 10 20 30 ns
fall time
HVD12 100 170 300
HVD10 1.5
tsk(p) Pulse skew (|tPHL – tPLH|) HVD11 2.5 ns
HVD12 7
HVD10 6
tsk(pp) (2) Part-to-part skew HVD11 11 ns
HVD12 100
HVD10 31
Propagation delay
tPZH time, high-impedance-to- HVD11 55 ns
high-level output
HVD12 RL = 110 Ω, RE at 0 V 300
HVD10 See Figure 8-5 25
Propagation delay
tPHZ time, high-level-to-high- HVD11 55 ns
impedance output
HVD12 300
HVD10 26
Propagation delay
tPZL time, high-impedance-to- HVD11 55 ns
low-level output
HVD12 RL = 110 Ω, RE at 0 V 300
HVD10 See Figure 8-6 26
Propagation delay
tPLZ time, low-level-to-high- HVD11 75 ns
impedance output
HVD12 400
Propagation delay time, standby-to-high- RL = 110 Ω, RE at 3 V
tPZH 6 μs
level output See Figure 8-5
Propagation delay time, standby-to-low- RL = 110 Ω, RE at 3 V
tPZL 6 μs
level output See Figure 8-6
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.

7.9 Receiver Switching Characteristics

tPLH HVD10 12.5 20 25
low-to-high-level output
ns
tPHL HVD10 12.5 20 25
high-to-low-level output
Propagation delay time, HVD11
tPLH VID = –1.5 V to 1.5 V 30 55 70 ns
low-to-high-level output HVD12
CL = 15 pF
Propagation delay time, HVD11 See Figure 8-9
tPHL 30 55 70 ns
high-to-low-level output HVD12
HVD10 1.5
tsk(p) Pulse skew (|tPHL – tPLH|) HVD11 4 ns
HVD12 4
HVD10 8
tsk(pp) (2) Part-to-part skew HVD11 15 ns
HVD12 15
tr Output signal rise time CL = 15 pF 1 2 5
ns
tf Output signal fall time See Figure 8-9 1 2 5
tPZH (1) Output enable time to high level 15
tPZL (1) Output enable time to low level 15
CL = 15 pF, DE at 3 V
ns
tPHZ Output disable time from high level See Figure 8-10 20
tPLZ Output disable time from low level 15
Propagation delay time, standby-to-high-
tPZH (2) 6
level output CL = 15 pF, DE at 0
μs
Propagation delay time, standby-to-low- See Figure 8-11
tPZL (2) 6
level output
(1) All typical values are at 25°C and with a 3.3-V supply
(2) tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
7.10 Dissipation Ratings

TA ≤ 25°C DERATING FACTOR(1) TA = 70°C TA = 85°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D(2) 597 mW 4.97 mW/°C 373 mW 298 mW 100 mW
D(3) 990 mW 8.26 mW/°C 620 mW 496 mW 165 mW
P 1290 mW 10.75 mW/°C 806 mW 645 mW 215 mW
(1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
(2) Tested in accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
(3) Tested in accordance with the High-K thermal metric definitions of EIA/JESD51-7.

7.11 Typical Characteristics

70 70
TA = 25°C RL = 54 W TA = 25°C RL = 54 W
RE at VCC CL = 50 pF RE at VCC CL = 50 pF VCC = 3.6 V
I CC − RMS Supply Current − mA

DE at VCC DE at VCC
60 VCC = 3.6 V 60
50 50
VCC = 3 V
VCC = 3 V
40 VCC = 3.3 V VCC = 3.3 V

40
30 30
0 5 10 15 20 25 30 35 40 0 2.5 5 7.5 10
Signaling Rate − Mbps Signaling Rate − Mbps
Figure 7-1. HVD10 RMS Supply Current vs Signaling Rate Figure 7-2. HVD11 RMS Supply Current vs Signaling Rate
70 300
TA = 25°C RL = 54 W TA = 25°C
RE at VCC CL = 50 pF 250 DE at 0 V
DE at VCC
VCC = 3.6 V 200
I I − Bus Input Current − uA

60
150 VCC = 0 V
VCC = 3.3 V
100
50 50
VCC = 3 V
VCC = 3.3 V
0
−50
40
−100
−150
30 −200
100 400 700 1000 −7 −6−5 −4−3 −2−1 0 1 2 3 4 5 6 7 8 9 10 11 12
Signaling Rate − kbps VI − Bus Input Voltage − V
Figure 7-3. HVD12 RMS Supply Current vs Signaling Rate Figure 7-4. HVD10 Bus Input Current vs Bus Input Voltage
90 150
80 TA = 25°C TA = 25°C
IOH − High-Level Output Current − mA
70 DE at 0 V DE at VCC
100
D at VCC
60
VCC = 3.3 V
I I − Bus Input Current − uA
50
VCC = 0 V 50
40
30
0
20
10
0 VCC = 3.3 V −50
−10
−20 −100
−30
−40 −150
−50
−60 −200
−7−6 −5 −4 −3 −2 −1 0 1 2 3 4 5 6 7 8 9 10 11 12 −4 −2 0 2 4 6
VI − Bus Input Voltage − V VOH − Driver High-Level Output Voltage − V
Figure 7-5. HVD11 or HVD12 Bus Input Current vs Bus Input Figure 7-6. High-Level Output Current vs Driver High-Level
Voltage Output Voltage

7.11 Typical Characteristics (continued)

200 2.5
TA = 25°C VCC = 3.3 V
180 2.4
DE at VCC DE at VCC
I OL − Low-Level Output Current − mA
VOD − Driver Differential Output − V

160 D at 0 V 2.3 D at VCC
VCC = 3.3 V
140
2.2
120
2.1
100
2.0
80
1.9
60
1.8
40
1.7
20
0 1.6
−20 1.5
−4 −2 0 2 4 6 8 −40 −15 10 35 60 85
VOL − Driver Low-Level Output Voltage − V TA − Free-Air Temperature − °C
Figure 7-7. Low-Level Output Current vs Driver Low-Level Figure 7-8. Driver Differential Output vs Free-Air Temperature
Output Voltage
−40 600
TA = 25°C
DE at VCC
−35
D at VCC 500
I O − Driver Output Current − mA
RL = 54 Ω
−30 HVD12
400
−25 Enable Time − ns
HVD11
−20 300
−15 HVD10
200
−10
100
−5
0 0
0 0.50 1 1.50 2 2.50 3 3.50 -7 -2 3 8 13
VCC − Supply Voltage − V V(TEST) − Common-Mode Voltage − V
Figure 7-9. Driver Output Current vs Supply Voltage Figure 7-10. Enable Time vs Common-Mode Voltage

8 Parameter Measurement Information

VCC
II DE IOA
A
0 or 3 V VOD 54 Ω±1%
B IOB
VI
VOB VOA
Figure 8-1. Driver VOD Test Circuit and Voltage and Current Definitions
375 Ω ±1%
VCC
DE
A
D
0 or 3 V VOD 60 Ω ±1%
+
B _ −7 V < V(test) < 12 V
375 Ω ±1%
Figure 8-2. Driver VOD With Common-Mode Loading Test Circuit
A VA
VCC
27 Ω ± 1%
DE B VB
A
D VOC(PP)
Input DVOC(SS)
27 Ω ± 1%
B VOC
CL = 50 pF ±20% VOC
CL Includes Fixture and

Instrumentation Capacitance
Input: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
VCC 3V
VI 1.5 V 1.5 V
DE CL = 50 pF ±20%
A
D VOD CL Includes Fixture t PLH t PHL
and Instrumentation ≈2 V
Input RL = 54 Ω Capacitance 90% 90%
VI 50 Ω B
Generator ± 1% 0V 0V
VOD 10% 10%
≈ –2 V
tr tf
Generator: PRR = 500 kHz, 50% Duty Cycle, tr < 60 ns, tf < 6 ns ZO = 50 Ω
Figure 8-4. Driver Switching Test Circuit and Voltage Waveforms

A 3V
D S1
VO VI 1.5 V 1.5 V
3V
B 0V
DE 0.5 V
CL = 50 pF ±20% RL = 110 Ω t PZH
Input ± 1% VOH
Generator VI 50 Ω
CL Includes Fixture
and Instrumentation VO 2.3 V
Capacitance ≈0V
t PHZ
Figure 8-5. Driver High-Level Enable and Disable Time Test Circuit and Voltage Waveforms
3V
RL = 110 Ω ≈3 V
± 1%
A
S1 VI 1.5 V 1.5 V
D VO
3V
0V
B t PZL t PLZ
DE
Input CL = 50 pF ±20% ≈3 V
Generator VI 50 Ω 0.5 V
CL Includes Fixture
and Instrumentation VO 2.3 V
Capacitance VOL
Figure 8-6. Driver Low-Level Output Enable and Disable Time Test Circuit and Voltage Waveforms
375 Ω ± 1%
Y -7 V < V(TEST) < 12 V

D VOD 60 W
0 or 3 V ± 1%
Z
DE
375 Ω ± 1%
Input V 50 Ω
Generator
50%
tpZH(diff)
VOD (high)
1.5 V
0V
tpZL(diff)
-1.5 V
VOD (low)
The time tPZL(x) is the measure from DE to VOD(x). VOD is valid when it is greater than 1.5 V.
Figure 8-7. Driver Enable Time from DE to VOD

IA
A
IO
VA R
VID
B
VB
VIC IB VO
VA + VB
2
Figure 8-8. Receiver Voltage and Current Definitions

A
R VO
Input
Generator VI 50 Ω B
1.5 V CL = 15 pF ±20%
RE
0V CL Includes Fixture
and Instrumentation
Capacitance
Generator: PRR = 500 kHz, 50% Duty Cycle, tr <6 ns, t f <6 ns, Z o = 50 Ω
3V
VI 1.5 V 1.5 V
0V
t PLH t PHL
VOH
90% 90%
VO 1.5 V 1.5 V
10% 10% V
OL
tr tf
Figure 8-9. Receiver Switching Test Circuit and Voltage Waveforms

3V 3V
DE A A
R VO 1 kΩ ± 1%
D S1
0 V or 3 V B CL = 15 pF ±20%
RE B
CL Includes Fixture
and Instrumentation
Input Capacitance
Generator VI 50 Ω
Generator: PRR = 500 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Z o = 50 Ω
3V
VI
1.5 V 1.5 V
0V
t PZH(1) t PHZ
VOH D at 3 V
VOH –0.5 V
S1 to B
VO 1.5 V
≈0V
t PZL(1) t PLZ
≈3V
D at 0 V
VO 1.5 V S1 to A
VOL +0.5 V
VOL
Figure 8-10. Receiver Enable and Disable Time Test Circuit and Voltage Waveforms With Drivers Enabled

3V
A A
0 V or 1.5 V R VO 1 kΩ ± 1%
S1
B
1.5 V or 0 V RE CL = 15 pF ±20%
B
CL Includes Fixture
Input and Instrumentation
VI Capacitance
Generator 50 Ω
Generator: PRR = 100 kHz, 50% Duty Cycle, t r <6 ns, t f <6 ns, Z o = 50 Ω
3V
VI 1.5 V
0V
t PZH(2)
VOH
A at 1.5 V
VO 1.5 V B at 0 V
S1 to B
GND
t PZL(2)
3V
A at 0 V
B at 1.5 V
VO 1.5 V
S1 to A
VOL
Figure 8-11. Receiver Enable Time From Standby (Driver Disabled)

0 V or 3 V
RE
A
R
B
100 W
± 1%
Pulse Generator ,
15 ms Duration, + D
1% Duty Cycle _
t r, t f ≤ 100 ns
DE
3 V or 0 V
NOTE: This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 8-12. Test Circuit, Transient Over Voltage Test

D and RE Inputs DE Input

VCC VCC
100 kΩ
1 kΩ 1 kΩ
Input Input
9V 100 kΩ
9V
A Input B Input
VCC VCC
16 V 16 V
R1 R1
R3 R3
Input Input
16 V R2 16 V R2
A and B Outputs R Output

VCC VCC
16 V
5Ω
Output
Output
9V
16 V
R1/R2 R3
SN65HVD10 9 kW 45 kW
Figure 8-13. Equivalent Input and Output Schematic Diagrams

9 Detailed Description
9.1 Overview
The SN65HVD10, SN65HVD11, and SN65HVD12 are 3.3 V, half-duplex, and RS-485 transceivers that are
available in 3 speed grades suitable for data transmission up to 32 Mbps, 10 Mbps, and 1 Mbps.
These devices have both active-high driver enables and active-low receiver enables. A standby current of less
than
5 µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagram
9.3 Feature Description

Internal ESD protection circuits protect the transceiver bus terminals against ±16-kV Human Body Model (HBM)
electrostatic discharges and ±4-kV electrical fast transients (EFT) according to IEC61000-4-4.
The SN65HVD1x half-duplex family provides internal biasing of the receiver input thresholds for open-circuit,
bus-idle, or short-circuit fail-safe conditions, as well as a typical receiver hysteresis of 35 mV.
9.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE
pin has an internal pulldown resistor to ground; therefore, when left open, the driver is disabled (high-impedance)
by default. The D pin has an internal pullup resistor to VCC; therefore, when left open while the driver is enabled,
output A turns high and B turns low.
Table 9-1. Driver Functions(1)
INPUT ENABLE OUTPUTS
FUNCTION
D DE A B
H H H L Actively drive bus High
L H L H Actively drive bus Low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus High by default
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,

turns high. When VID is negative and lower than the negative input threshold, VIT–, the receiver output, R, turns
low. If VID is between VIT+ and VIT–, the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go fail-safe-high when the transceiver
is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or when the bus is not
actively driven (idle bus).
Table 9-2. Receiver Functions(1)
DIFFERENTIAL INPUT ENABLE OUTPUT
FUNCTION
VID = VA – VB RE R
VID > VIT+ L H Receive valid bus High
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus Low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
(1) H = high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
9.4.1 Low-Power Standby Mode

When both the driver and receiver are disabled (DE low and RE high) the device is in standby mode. If the
enable inputs are in this state for less than 60 ns, the device does not enter standby mode. This guards against
inadvertently entering standby mode during driver or receiver enabling. Only when the enable inputs are held in
this state for 300 ns or more, the device is assured to be in standby mode. In this low-power standby mode, most
internal circuitry is powered down, and the supply current is typically less than 1 µA. When either the driver or
the receiver is re-enabled, the internal circuitry becomes active.

10 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information

The SN65HVD10, 'HVD11, and 'HVD12 are half-duplex RS-485 transceivers commonly used for asynchronous
data transmissions. The driver and receiver enable pins allow the configuration of different operating modes.
R R R
R R R
RE A RE A RE A
DE B DE B DE B
D D D
D D D
a) Independent driver and b) Combined enable signals for c) Receiver always on

receiver enable signals use as directional control pin
Figure 10-1. Half-Duplex Transceiver Configurations
1. Using independent enable lines provides the most flexible control, as it allows the driver and the receiver
to be turned on and off individually. While this configuration requires two control lines, it allows selective
listening into the bus traffic, whether the driver is transmitting data or not.
2. Combining the enable signals simplify the interface to the controller, by forming a single direction-control
signal. In this configuration, the transceiver operates as a driver when the direction-control line is high, and
as a receiver when the direction-control line is low.
3. Only one line is required when connecting the receiver-enable input to ground and controlling only the
driver-enable input. In this configuration, a node not only receives the data from the bus, but also the data it
sends and can verify that the correct data have been transmitted.

10.2 Typical Application

An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows higher data rates over a longer
cable length.
R R R R
A A
RE RE
RT RT
B B
DE DE
D D D D
A B A B
R R
D D
R RE DE D R RE DE D
Figure 10-2. Typical RS-485 Network With Half-Duplex Transceivers
10.2.1 Design Requirements

RS-485 is a robust electrical standard suitable for long-distance networking, that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and bus length, meaning the higher the data rate, the shorter
the cable length; and conversely, the lower the data rate, the longer the cable may be without introducing data
errors. While most RS-485 systems use data rates between 10 kbps and 100 kbps, some applications require
data rates up to 250 kbps at distances of 4000 feet and longer. Longer distances are possible by allowing small
signal jitter of up to 5 or 10%.
10000
5%, 10%, and 20% Jitter
Cable Length (ft)
1000
Conservative
Characteristics
100
10
100 1k 10 k 100 k 1M 10 M 100 M
Data Rate (bps)
Figure 10-3. Cable Length vs Data Rate Characteristic

10.2.1.2 Stub Length

When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a nonterminated piece of bus line, which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length or round-trip delay
of a stub should be less than one-tenth of the rise time of the driver, therefore giving a maximum physical stub
length as shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c (1)
where
• tr is the 10/90 rise time of the driver
• v is the signal velocity of the cable or trace as a factor of c
• c is the speed of light (3 × 108 m/s)
Per Equation 1, Table 10-1 lists the maximum cable-stub lengths for the minimum-driver output rise-times of the
SN65HVD1x full-duplex family of transceivers for a signal velocity of 78%.
Table 10-1. Maximum Stub Length
MINIMUM DRIVER OUTPUT MAXIMUM STUB LENGTH
DEVICE
RISE TIME (ns) (m) (ft)
SN65HVD10 3 0.07 0.23
SN65HVD11 10 0.23 0.75
SN65HVD12 100 2.34 7.67
10.2.1.3 Bus Loading

The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1
unit load represents a load impedance of approximately 12 kΩ. SN65HVD11 and HVD12 are both 1/8 UL
transceivers, which means that up to 256 receivers can be connected to the bus. The SN65HVD10 is a 1/4 UL
transceiver, and up to 64 receivers can be connected to the bus.
10.2.1.4 Receiver Fail-safe
The differential receivers of the SN65HVD1x family are fail-safe to invalid bus states caused by:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving.
In any of these cases, the differential receiver will output a fail-safe logic High state so that the output of the
receiver is not indeterminate.
Receiver fail-safe is accomplished by offsetting the receiver thresholds, such that the input indeterminate range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a High when the differential input VID is more positive than +200 mV, and must output a Low when
VID is more negative than –200 mV. The receiver parameters which determine the fail-safe performance are
VIT(+) and VIT(–). As shown in Section 7.6, differential signals more negative than –200 mV will always cause
a Low receiver output, and differential signals more positive than +200 mV will always cause a High receiver
output.
When the differential input signal is close to zero, it is still above the maximum VIT(+) threshold of –10 mV, and
the receiver output will be High.

10.2.2 Detailed Design Procedure

To protect bus nodes against high-energy transients, the implementation of external transient protection devices
is therefore necessary. Figure 10-4 shows a protection circuit against 10-kV ESD (IEC 61000-4-2), 4-kV EFT
(IEC 61000-4-4), and 1-kV surge (IEC 61000-4-5) transients.
Vcc
Vcc
10 k
0.1 μF R1
1 8
RxD R Vcc
2 7
TVS
MCU RE A
XCVR
3 6
DIR DE B
4 5
TxD D GND
R2
10 k
Figure 10-4. Transient Protection Against ESD, EFT, and Surge Transients
Table 10-2. Bill of Materials

DEVICE FUNCTION ORDER NUMBER MANUFACTURER
XCVR 3.3-V, full-duplex RS-485 SN65HVD1xD TI
transceiver
R1, R2 10-Ω, pulse-proof, thick- CRCW0603010RJNEAHP Vishay
film resistor
TVS Bidirectional 400-W CDSOT23-SM712 Bourns
transient suppressor
10.2.3 Application Curve

Figure 10-5 demonstrates operation of the SN65HVD12 at a signaling rate of 250 kbps. Two SN65HVD12
transceivers are used to transmit data through a 2,000 foot (600 m) segment of Commscope 5524 category
5e+ twisted pair cable. The bus is terminated at each end by a 100-Ω resistor, matching the cable characteristic
impedance.
Driver Input
Driver Output
Receiver Input
Receiver Output
Figure 10-5. SN65HVD12 Input and Output Through 2000 Feet of Cable

11 Power Supply Recommendations

To assure reliable operation at all data rates and supply voltages, each supply must be buffered with a 100-nF
ceramic capacitor located as close to the supply pins as possible. The TPS76333 linear voltage regulator is
suitable for the 3.3-V supply.
12 Layout
12.1 Layout Guidelines
On-chip IEC-ESD protection is sufficient for laboratory and portable equipment, but never sufficient for EFT and
surge transients occurring in industrial environments. Therefore, robust and reliable bus node design requires
the use of external transient protection devices.
It is because ESD and EFT transients have a wide frequency bandwidth from approximately 3 MHz to 3 GHz,
that high-frequency layout techniques must be applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from entering the board.
2. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents follow the path of
least inductance and not the path of least impedance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF bypass capacitors as close as possible to the VCC pins of transceiver, UART, and
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of bypass capacitors and protection devices to
minimize effective via-inductance.
6. Use 1-kΩ to 10-kΩ pull-up or pull-down resistors to enable lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof series resistors into the A and B bus lines if the TVS clamping voltage is higher than
the specified maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping
current into the transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.

12.2 Layout Example
5
Via to ground
C 4 Via to VCC
R
6 R
R 1
JMP
MCU 7 R
R 5
TVS
6 R
XCVR 5
Figure 12-1. SN65HVD1x Layout Example
12.3 Thermal Considerations

12.3.1 Thermal Characteristics of IC Packages
RθJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to
ambient temperature divided by the operating power.
RθJA is not a constant and is a strong function of:
• the PCB design (50% variation)
• altitude (20% variation)
• device power (5% variation)
RθJA can be used to compare the thermal performance of packages when specific test conditions are defined
and used. Standardized testing includes specification of PCB construction, test chamber volume, sensor
locations, and the thermal characteristics of holding fixtures. RθJA is often misused when it is used to calculate
junction temperatures for other installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition
thermal performance, and it consists of a single copper trace layer 25 mm long and 2-oz thick. The high-k board
gives best case in-use condition, and it consists of two 1-oz buried power planes with a single copper trace layer
25 mm long and 2-oz thick. A 4% to 50% difference in RθJA can be measured between these two test cards.
RθJC (Junction-to-Case Thermal Resistance) is defined as the difference in junction temperature to case
divided by the operating power. It is measured by putting the mounted package up against a copper block cold
plate to force heat to flow from the die, through the mold compound into the copper block.
RθJC is a useful thermal characteristic when a heat sink is applied to package. It is not a useful characteristic
to predict junction temperature, because it provides pessimistic numbers if the case temperature is measured
in a nonstandard system and junction temperatures are backed out. It can be used with RθJB in 1-dimensional
thermal simulation of a package system.
RθJB (Junction-to-Board Thermal Resistance) is defined as the difference in the junction temperature and the
PCB temperature at the center of the package (closest to the die) when the PCB is clamped in a cold-plate
structure. RθJB is only defined for the high-k test card.
RθJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal
resistance (especially for BGAs with thermal balls) and can be used for simple 1-dimensional network analysis of
package system, see Figure 12-2.

Figure 12-2. PCB Thermal Resistances

13 Device and Documentation Support

13.1 Device Support
13.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 13-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
SN65HVD10 Click here Click here Click here Click here Click here
13.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 26-Apr-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SN65HVD10D OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 85 VP10

SN65HVD10DR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10 Samples
SN65HVD10DRG4 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 VP10 Samples
SN65HVD10P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 65HVD10 Samples
SN65HVD10QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP10Q Samples
SN65HVD11QDR ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VP11Q Samples
SN75HVD10P NRND PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD10
SN75HVD12P ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12 Samples
SN75HVD12PE4 ACTIVE PDIP P 8 50 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 75HVD12 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
Addendum-Page 1
PACKAGE OPTION ADDENDUM
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN65HVD10, SN65HVD11, SN65HVD12 :
• Enhanced Product : SN65HVD10-EP, SN65HVD12-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN65HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD10QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD11QDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
SN65HVD12DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65HVD10DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD10DR SOIC D 8 2500 340.5 336.1 25.0
SN65HVD10QDR SOIC D 8 2500 340.5 336.1 25.0
SN65HVD10QDR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD11DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD11DR SOIC D 8 2500 340.5 336.1 25.0
SN65HVD11QDR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD11QDR SOIC D 8 2500 340.5 336.1 25.0
SN65HVD12DR SOIC D 8 2500 356.0 356.0 35.0
SN65HVD12DR SOIC D 8 2500 340.5 336.1 25.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
SN65HVD10P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD11P P PDIP 8 50 506 13.97 11230 4.32
SN65HVD12P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD10P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD12P P PDIP 8 50 506 13.97 11230 4.32
SN75HVD12PE4 P PDIP 8 50 506 13.97 11230 4.32
PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1
.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]
4X (0 -15 )
4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK
EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
8X (.061 )
[1.55] SYMM
1
8
8X (.024)
[0.6] SYMM
(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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SN65HVD10, SN65HVD11, SN65HVD12

SN75HVD10, SN75HVD11, SN75HVD12

SNx5HVD1x 3.3-V RS-485 Transceivers

(1) For all available packages, see the orderable addendum at

Typical Application Diagram

Changes from Revision N (July 2015) to Revision O (February 2017) Page

Changes from Revision M (July 2013) to Revision N (July 2015) Page

Changes from Revision L (July 2013) to Revision M (July 2013) Page

Changes from Revision K (September 2011) to Revision L (July 2013) Page

Changes from Revision J (February 2009) to Revision K (September 2011) Page

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12

5 Device Comparison Table

6 Pin Configuration and Functions

Figure 6-1. D, JD, or HKJ Package

Table 6-1. Pin Functions

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7.2 ESD Ratings

7.3 Recommended Operating Conditions

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7.4 Thermal Information

RθJB Junction-to-board thermal resistance 63.4 62.1 °C/W

7.5 Driver Electrical Characteristics

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

7.6 Receiver Electrical Characteristics

7.7 Power Dissipation Characteristics

(1) See Section 12.3.1 section for an explanation of these parameters.

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7.8 Driver Switching Characteristics

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7.9 Receiver Switching Characteristics

7.10 Dissipation Ratings

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7.11 Typical Characteristics

I CC − RMS Supply Current − mA

40 VCC = 3.3 V VCC = 3.3 V

VCC = 3.6 V 200

I I − Bus Input Current − uA

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7.11 Typical Characteristics (continued)

VOD − Driver Differential Output − V

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8 Parameter Measurement Information

Copyright © 2017, Texas Instruments Incorporated

Figure 8-2. Driver VOD With Common-Mode Loading Test Circuit

CL Includes Fixture and

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Copyright © 2017, Texas Instruments Incorporated

Figure 8-4. Driver Switching Test Circuit and Voltage Waveforms

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Copyright © 2017, Texas Instruments Incorporated

Copyright © 2017, Texas Instruments Incorporated

Y -7 V < V(TEST) < 12 V

Figure 8-7. Driver Enable Time from DE to VOD

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Product Folder Links: SN65HVD10 SN65HVD11 SN65HVD12 SN75HVD10 SN75HVD11 SN75HVD12