UNIT III:8086 Interfacing

• Semiconductor memories interfacing (RAM, ROM)

• Intel 8255 programmable peripheral interface
• Interfacing switches and LEDS
• Interfacing seven segment displays
• Stepper motor
• A/D and D/A converters
• Software and hardware interrupt applications
• Intel 8251 USART architecture and interfacing
• Intel 8237a DMA controller
• Need for 8259 programmable interrupt controllers
8086 Interfacing
• Interface refers to the path for communication between two
components. Interfacing is of two types, memory interfacing,
and I/O interfacing.
• Memory Interfacing occurs when we need the
microprocessor to access the memory for reading instruction
codes and the data stored in the memory.
• There are various communication devices like the keyboard,
mouse, printer, etc. So, we need to interface the keyboard
and other devices with the microprocessor by using latches
and buffers. This type of interfacing is known as I/O
interfacing.
Block Diagram of Memory and I/O Interfacing
Semiconductor memories interfacing (RAM, ROM)
• Memory is simply a device that can be used to store the
information i.e Programs and data.
• Semiconductor memory is a digital electronic semiconductor
device used for digital data storage, such as computer
memory.
• It typically refers to MOS memory, where data is stored
within metal–oxide–semiconductor (MOS) memory cells on
a silicon integrated circuit memory chip.
Types of Semiconductor Memories:
Advantages of ROM
• The advantages of ROM are as follows −
• Non-volatile in nature
• Cannot be accidentally changed
• Cheaper than RAMs
• Easy to test
• More reliable than RAMs
• Static and do not require refreshing
• Contents are always known and can be verified
Semiconductor RAM types
Types of Semiconductor Memories:
Semiconductor Memory Interfacing
• Semiconductor memories are of two types: RAM and ROM.
• The semiconductor memories are arranged as two dimensional arrays
of memory locations.
• For example, 1K X 8 memory chip contains 1024 locations and each of
them is one byte wide. i.e.1024 bytes of information can be stored in
that chip.
• Each location should have an address. So, there has to be certain
number of address lines on the memory chips.
• If we designate it as n, then n = log2N, where N is the number of
locations that could be addresses in that chip and n is no.of address
lines we need to use.
No.of address lines required:

• n = log2N, where N is the number of locations that could be addresses in that chip and n is
no.of address lines we need to use.
2n=N
• For 1K chip n would be 10

• Available memory is 2K*8 means 8 bit data line and address line, 2K=21×210=211

• So 11 address lines A10,A9,⋯A0

• For 1K chip n would be 10, for 2K it is 11, for 4k it will be 12 etc.

The general procedure of static memory interfacing with 8086 is
described as follows:
1. Arrange the available memory chips so that they form a 16-bit data
bus width. The upper 8-bit bank called odd address memory bank and
the lower 8-bit bank is called even address memory bank.
2. Connect available memory address lines with control signals like
read, write of the microprocessor with those of memory chip.
3. Remaining address lines along with A0and BHE are used for decoding
the required chip select signals for odd and even banks
• Problem:
Interface two 4K×8 EPROMS and two4K×8 RAM chips with 8086.
Solution:
• First we have to write the memory map from the problem given.
• It will reveal the logic to be used for decoding circuit.
• Total 8K bytes of EPROM need 13 address lines A0 -A 12 (since 213 = 4K).
• Since for n address lines, the number of memory locations able to
address is 2^n.
• Address lines A 13 - A 19 are used for decoding to generate the chip select .
• The memory system in this example contains in total four 4K x 8 memory chips.
• The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit
data bus width.
• The BHE signal goes low when a transfer is at odd address or higher byte of data
is to be accessed.
• Let us assume that the latched address. BHE and demultiplexed data lines are
readily available for interfacing.
• Since the first instruction is fetched from FFFF0h after the microprocessor is
reset, we will make that address to be present in EPROM and write the
memory map as follows.
• And, to avoid windowing let us keep the locations to be present in the RAM as
immediate addresses .
• Locations having addresses from FFFFFH to FE000H are allocated to EPROM
1 and 2.
• Immediate address map FDFFFH to FD000H is allocated to RAM1 and 2.
Memory Chip Selection
Memory
• Each memory device has at least one chip select (CS)or chip enable
(CE) or select (S)pin that enables the memory device.
• –This enables read and/or write operations.
•Each memory device has at least one control pin.
–For ROMs, an output enable (OE) or gate (G) is present.
• The OE pin enables and disables a set of tristate buffers.
–For RAMs, a read-write (R/W) or write enable (WE) and read enable
• (OE) are present
Intel 8255 programmable peripheral interface
• 8255 is a programmable I/O device that acts as
interface between peripheral devices and
the microprocessor for parallel data transfer.
• 8255 PPI (programmable peripheral interface) can be
programmed to transfer data under various
conditions, from simple I/O to interrupt I/O.
• It is an important general purpose I/O device that can
be used with almost any microprocessor.
Architecture of 8255
 Architecture of 8255

It consists of Three sections :

1. Data Bus Buffer
2. Read/Write Control logic
3. Group A & Group B Ports-
Group A (Port A and Port C i.e., PC7 – PC4)
Group A (Port A and Port C Lower i.e., PC3 – PC0)
 Data Bus Buffer
• This three-state bi-directional 8-bit buffer is used to interface the
8255 to the system data bus.
• Data is transmitted or received by the buffer upon execution of input
or output instructions by the CPU.
• Control words and status information are also transferred through the
data bus buffer.
• Read/Write and Control Logic
• The function of this block is to manage all of the internal and
external transfers of both Data and Control or Status words. It
accepts inputs from the CPU Address and Control busses and in
turn, issues commands to both of the Control Groups.
• (CS) Chip Select. A "low" on this input pin enables the
communication between the 8255 and the CPU.
• (RD) Read. A "low" on this input pin enables 8255 to send the
data or status information to the CPU on the data bus. In
essence, it allows the CPU to "read from" the 8255.
• (WR) Write. A "low" on this input pin enables the CPU to write
data or control words into the 8255.
• RD is from CPU to 8255(input line) and WR is from 8255 to
CPU(output Line)
• (A0 and A1) Port Select 0 and Port Select 1. These input signals, in
conjunction with the RD and WR inputs, control the selection of one of the
three ports or the control word register. They are normally connected to
the least significant bits of the address bus (A0 and A1).

A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
CONTROL
1 1
REGISTER
• (RESET) : It is an active high signal that shows the resetting of the PPI. A
high signal at this pin clears the control registers and the ports are set in
the input mode.
Group A & Group B Ports
• It has Three ports Port A, Port B and Port C and as each port has 8
lines.
• Two Groups: 12-bits each
Group A - Port A and Port C Upper (i.e., PC7 – PC4)
Group A - Port A and Port C Lower (i.e., PC3 – PC0)
• Port A – 8-bit buffered I/O Latch and can be programmed by mode0,mode1 &
mode 2
• Port B – 8-bit buffered I/O Latch and can be programmed by mode 0 and
mode 1
• Port C – 8-bit unlatched buffered I/O ,split into 2 parts and programmed by
bit set/ reset mode
Pin diagram of 8255

The external voltage required to

drive the circuit is provided at pin
number 26 i.e., VCC. Also pin
number 7 is the ground
connection of the circuit.

Out of 40 pins, 24 pins are allotted

to I/O ports. Rest of the pins are
allotted to the signals discussed
above.
 Modes of Operation-8255
The 8255A is primarily operated in two modes:
1. The BSR (Bit-Set-Reset) mode
2. I/O (input-output) mode : The I/O mode is further grouped into 3
• Mode 0 - Simple I/O interfacing
• Mode 1 – Handshaking I/O (Strobed I/O)
• Mode 2 – Bi-Directional Handshaking I/O (Strobed bi-directional I/O)
When D7=0, BSR mode
• For port C
• No effect on I/O mode and functions of port A and B
• Individual bits of port C can be used for applications such as ON/OFF
switch
When D7=1, I/O mode
i) Mode 0
• Simple I/O interfacing for port A, B and C
ii) Mode 1
• Interfacing with handshake signals for port A and B
• Port C bits are used for handshake
iii) Mode 2
• Bidirectional I/O interfacing for port A
• Port B: either in mode 0 or mode 1
• Port C bits used for handshake
Input operation :
Output operation:
To communicate with peripherals through 8255 three steps are necessary:
• Determine the addresses of Port A, B, C and Control register according to
Chip Select Logic and the Address lines A0 and A1.
• Write a control word in control register.
• Write I/O instructions to communicate with peripherals through port A, B, C.

The common applications of 8255 are:

• Traffic light control
• Generating square wave
• Interfacing with DC motors and stepper motors
 Interfacing LEDS
• Anode is connected through a resistor to GND & the Cathode is
connected to the Microprocessor pin as shown in Fig.
• When the Port Pin is HIGH, the LED is OFF & when the Port Pin is LOW
the LED is turned ON.
• We now want to flash a LED. It works by turning ON a LED & then
turning it OFF & then looping back to START.
• A delay is generated between the flashing of LEDs.
Interfacing LEDS
ASSEMBLY PROGRAM TO TURN ON AND OFF LEDS USING 8086

1 0 0 0 0 0 0 0
CWR=1000 0000 = 80H
PORT-A as OUTPUT PORT
MOV AL,80H
MOV DX,ADD-CWR
MOV DX,AL

UP: MOV AL,#00H

MOV DX,ADD-PORTA
MOV DX,AL
CALL DELAY
MOV AL,#FFH
MOV DX,AL
CALL DELAY
JMP UP
DELAY: MOV CX,#FFFFH
P0: DEC CX
JNZ P0
RET
Interfacing switches and LEDS
 Interfacing seven segment displays
Seven Segment Displays are used in a number of systems to display the
numeric information.
The seven segments can display one digit at a time.
Thus the no. of segments used depends on the no. of digits in the
number to be displayed.
A seven segment consists of eight LEDs which are aligned in a manner
so as to display digits from 0 to 9 when proper combination of LED is
switched on.
Seven segment uses seven LED’s to display digits from 0 to 9 and the
eighth LED is used for the dot.
A typical seven segment looks like as shown in the figure below
• Seven-segment display is a form of electronic display used for
displaying alpha-numeric characters. A seven-segment display is a set
of seven LEDs elements, arranged to form a figure of 8. Each of the
LEDs is turned ON and OFF and the combination of LEDs which are
ON forms a character. If all elements are activated, the display shows a
numeral 8. Numbers from 0-9 and few alphabets can be displayed.

The working of 7 segment display is on the similar lines as that of and

LED as the 7 segment displays is eventually made up of 7 LEDs and
an LED for the decimal point. The use of the decimal point is to
display decimal numbers like 3.1 or 7.5. The 7 segment display are of
two types viz. Common Anode display and Common Cathode display.
 common anode
common cathode

All of the cathodes (negative terminals) or all of the anodes (positive

terminals) of the segment LEDs are connected and brought out to a
common pin; this is referred to as a "common cathode" or "common
anode" device. Hence a 7 segment plus decimal point package will only
require nine pins. Common cathode implementations require logic low
(0) to turn on a segment, common anode implementations require
logic high (1) to turn on a segment.
Stepper Motor Interfacing
• A stepper motor is a device used to obtain an accurate position control of
rotating shafts
• It employs rotation of its shaft in terms of steps rather than continuous
rotation as in case of AC or DC motors
• To rotate the shaft of the stepper motor, a sequence of pulses is applied to
the windings of the stepper motor in a proper sequence
• The number of pulses required for one complete rotation of the shaft of the
stepper motor is equal to its number of internal teeth on the rotor
• The stator teeth and the rotor teeth lock with each other to fix a position of
the shaft.
• With a pulse applied to the winding input, the rotor rotates by one
tooth position or an angle x
• X=3600/no. of rotor teeth
• After the rotation of the shaft through angle x, the rotor locks itself
with the next tooth in the sequence on the internal surface of stator
• Fig below shows the internal schematic of a four winding stepper
motor.
• Stepper motors have been designed to work with digital circuits.
• Binary level pulses of 0-5v are required at its winding inputs to obtain
the rotation of shafts
• The sequence of pulses can be decided, depending upon the required
motion of the shaft.
• Design a stepper motor controller and write an ALP to rotate shaft of
a 4-phase stepper motor
• (i) in clockwise 5 rotations
• (ii) in anticlockwise 5 rotations
• The 8255 port A address is 0740h. The stepper has 200 rotor teeth
• The port A bit PA0 drives winding Wa, PA1 drives Wb and so on.
• The stepper motor has an initial delay of 10 msec. Assume that the
routine for this delay is already available
A/D CONVERTERS
• In most of the cases, the PIO 8255 is used for interfacing the analog to
digital converters with microprocessor.
• The analog to digital converters is treaded as an input device by the
microprocessor, that sends an initializing signal to the ADC to start the
analogy to digital data conversation process.
• The start of conversation signal is a pulse of a specific duration.
• The process of analog to digital conversion is a slow process, and the
microprocessor has to wait for the digital data till the conversion is over.
• After the conversion is over, the ADC sends end of conversion EOC signal to
• inform the microprocessor that the conversion is over and the result is
ready at the output buffer of the ADC.
• These tasks of issuing an SOC pulse to ADC, reading EOC signal from the
ADC and reading the digital output of the ADC are carried out by the CPU
using 8255 I/O ports.
Control Signals:
SOC: The start of conversation signal
EOC : End of conversion signal
 DAC Interface
• DAC is an acronym used for Digital to Analog Converter and DAC interface is
used to generate analog output by converting the digital signal obtained from
the microprocessor into equivalent analog form.
• More simply, DACs are devices that perform digital to analog conversion
however, this conversion requires a reference value on the basis of which the
conversion takes place.

• In general, it is known that a microprocessor generates only digital signal i.e., in

the form of binary values as its output.
• However, in some applications like in order to control analog devices, analog
signals are needed.
• Due to this reason, DAC interfacing is necessary as using a DAC the digital
output of the microprocessor can be converted into analog form.
DAC – 0800
As it is an 8-bit DAC thus it contains 8 digital
input lines. Other than the input lines we have
two dedicated pins that provide current output
and complement of current output which is
given the name IOUT and I’OUT. There are a
positive and a negative supply voltage pin along
with a pin dedicated for compensation voltage.
Here VLC represents the threshold control pin
and there are two pins for positive and negative
values of reference voltage denoted by VREF (+)
and VREF (-).
It is an 8-bit DAC that offers high speed and is a current
output type of DAC that means it provides analog current as
its output. The conversion time offered by this DAC is around
100 ns. The current output signal obtained from it can be
converted into voltage by making use of a resistor.
 Interfacing DAC0800 with 8086
VOUT = [VREF *(Decimal Input Number)]/8
Program to generate Square wave Program to generate Triangular wave

MOV AL, 80H

MOV AL, 80H
MOV DX, 0FFC6H
MOV DX, 0FFC6H
OUT DX, AL
OUT DX, AL
MOV DX, 0FFC0
MOV DX, 0FFC0H
again: MOV AL, 00H
again: MOV AL, 00H
OUT DX, AL
up1:OUT DX, AL
CALL delay
INC AL
MOV AL, 0FFH
CMP AL, 0FFH
OUT DX, AL
JNE up1
CALL delay
up2: OUT DX, AL
JMP again
DEC AL
CMP AL, 00H
delay: MOV CX,00FF
JNE up2
back: LOOP back
JMP again
RET
Interrupts in 8086 microprocessor
• An interrupt is a condition that halts the microprocessor temporarily
to work on a different task and then returns to its previous task. An
interrupt is an event or signal that requests the CPU’s attention.
• This halt allows peripheral devices to access the microprocessor.
Whenever an interrupt occurs, the processor completes the current
instruction and starts the implementation of an Interrupt Service
Routine (ISR) or Interrupt Handler.
• ISR is a program that tells the processor what to do when the
interrupt occurs. After the ISR execution, control returns to the main
routine where it was interrupted.
Interrupt Types
Hardware Interrupts
• The interrupts initiated by external hardware by sending an
appropriate signal to the interrupt pin of the processor is called
hardware interrupt.
• The 8086 processor has two interrupt pins INTR and NMI. The
interrupts initiated by applying appropriate signal to these pins
are called hardware interrupts of 8086.
Hardware Interrupt Sources
The primary sources of interrupts, however are the
• PCs timer chip,
• keyboard,
• serial ports,
• parallel ports,
• disk drives,
• CMOS real- time clock,
• mouse,
• sound cards,
• and other peripheral devices.
Software Interrupts Types 0 through 255
• The software interrupts are program instructions. These
instructions are inserted at desired locations in a program.
• While running a program, if software interrupt instruction is
encountered then the processor initiates an interrupt.
• The 8086 processor has 256 types of software interrupts.
• The software interrupt instruction is INT n, where n is the type
• number in the range 0 to 255.
Example
• When divide-by-zero error interrupt and INTR interrupt comes simultaneously the 8086
will do a Divide error (type0) interrupt response first.
• When NMI interrupt and divide-by-zero error interrupt comes simultaneously the 8086
will do an NMI (type2) interrupt response first.
Interrupt Applications
Hardware Interrupt Applications
1. Simple Interrupt data input.
2. Counting Applications.
3. Timing Applications.
Software Interrupt Applications
1. To test various ISPs.
2. To insert break points in program for debugging.
3. To call BIOS procedures in an IBM PC type compute
1. Simplex
In simplex, the hardware exists such that data transfer
takes place only in one direction. There is no possibility
of data transfer in the other direction. A typical example
is transmission from a computer to the printer.

2. Half Duplex
The half duplex transmission allows the data transfer in
both directions, but not simultaneously. A typical
example is a walkie-talkie.

3. Full Duplex
The full duplex transmission allows the data transfer in
both direction simultaneously. The typical example is
transmission through telephone lines.
INTEL 8251 USART ARCHITECTURE AND INTERFACING
8251 Universal Synchronous and Asynchronous Receiver Transmitter (USART)
or Programmable Communication Interface (PCI) acts as a mediator between
microprocessor and peripheral to transmit serial data into parallel form and
vice versa.
1.It takes data serially from peripheral (outside devices) and converts into
parallel data.
2.After converting the data into parallel form, it transmits it to the CPU.
3.Similarly, it receives parallel data from microprocessor and converts it into
serial form.
4.After converting data into serial form, it transmits it to outside device
(peripheral).
5.Also, it allows both synchronous and asynchronous transmission and
reception thus is called so.
USART 8251 ARCHITECTURE
USART 8251 Pin Diagram
There are 5-BLOCKS IN 8251:
1. Data bus buffer
2. Read/Write control logic
3. Modem control (modulator/demodulator)
4. Transmitter section
1. Transmit buffer
2. Transmit control
5. Receiver section
1. Receive buffer
2. Receive control
1.Data bus buffer –
This block helps in interfacing the internal data bus of 8251 to the system data bus.
• The data bus buffer has 8-bit bidirectional data bus that allows the transfer of
data bytes, status or command word between the processor and external
devices.
2. Read/Write control logic –
It is a control block for overall device. It controls the overall working by selecting
the operation to be done.
• CS: It is chip select. A low signal at this pin shows that processor has selected
8251 in order to communicate with the peripheral devices.
• C/D: As the system has control, status and data register. So, when a high signal is
present at this pin then control or status register is addressed. While in case of
low signal data register is addressed.
• RD and WR: Both read and write are active low signal pins. A low signal at RD
shows that the processor is reading the control, status or data bytes from the
8251. While at WR indicates the write operation over the data bus of 8251.
• CLK and RESET: CLK stands for clock and it produces the internal timing for the
device. While an active high signal at the RESET pin puts the 8251 in the idle
mode.
3.Modem control (modulator/demodulator) –
A device converts analog signals to digital signals and vice-versa and helps
the computers to communicate over telephone lines or cable wires. The
following are active-low pins of Modem.
1. DSR: Data Set Ready signal is an input signal.

2. DTR: Data terminal Ready is an output signal.

3. CTS: Clear to send- It is an input signal which controls the data transmit circuit.

4. RTS: Ready to send- It is an output signal which is used to set the status RTS.
4. Transmitter Section
It has 2 blocks.
a. Transmit buffer –
This block is used for parallel to serial converter that receives a parallel
byte for conversion into serial signal and further transmission onto the
common channel.
1. TXD: It is an output signal, if its value is one, means transmitter will transmit
the data.
b. Transmit control –
This block is used to control the data transmission with the help of
following pins:
1. TXRDY: It means transmitter is ready to transmit data character.
2. TXEMPTY: An output signal which indicates that TXEMPTY pin has
transmitted all the data characters and transmitter is empty now.
3. TXC: An active-low input pin which controls the data transmission rate of
transmitted data.
5.Receiver Section:
It has 2 blocks.
a. Receive buffer –
This block acts as a buffer for the received data.
1. RXD: An input signal which receives the data.
b. Receive control –
This block controls the receiving data.
1. RXRDY: An input signal indicates that it is ready to receive the data.
2. RXC: An active-low input signal which controls the data transmission rate of
received data.
3. SYNDET/BD: An input or output terminal. External synchronous mode-input
terminal and asynchronous mode-output terminal.
Control Word of 8251:
The Control Word of 8251 defines the complete functional definition of
8251 Block Diagram in Microprocessor and they must be loaded before
any transmission or reception. The control words of Block Diagram of
8251 Microcontroller are split into two formats
1.Mode instruction
2.Command instruction
Mode Instruction : Fig. shows the mode instruction format of 8251.
Command Instruction:
After the mode instruction, command character should be issued to the USART. It controls the
operation of the USART within the basic frame work established by the mode instruction. Fig. shows
command instruction format.
8251A Status Word:
In the data communication systems it is often
necessary to examine the “status” of the
transmitter and receiver. It is also necessary for
CPU to know if any error has occurred during
communication. The 8251 Block Diagram in
Microprocessor allow the programmer to read
above mentioned information from the status
register any time during the functional
operation. Fig. shows the format of status
register.
Interfacing 8251A to 8086 in I/O
Mapped I/O Mode:
Fig. 14.46 shows the interfacing of 8251
with 8086 in I/O mapped I/O technique.
Here, RD and WR signals are activated
when M/IO signal is low, indicating I/O
bus cycle. Only lower data bus (D0 – D7)
is used as 8251 is 8-bit device. Reset out
signal from clock generator is connected
to the reset signal of the 8251.
Interfacing 8251 to 8086 in Memory Mapped I/O:
In this type of I/O interfacing, the 8086 uses 20
address lines to identify an I/O device; an I/O device
is connected as if it is a memory register. The 8086
uses same control signals and instructions to access
I/O as those of memory. Fig. 14.47 shows the
interfacing of 8251 with 8086 in memory mapped
I/O technique. Here, RD and WR signals are
activated when M/IO signal is high, indicating
memory bus cycle. Address line A1 is used to select
either data register, or control register. The
remaining address lines A2-A19 are used to decoder
the addresses for 8251.
 MODES OF DATA TRANSFER:
• We store the binary information received through an external device in the
memory unit.
• The information transferred from the CPU to external devices originates
from the memory unit.
• Although the CPU processes the data, the target and source are always the
memory unit.
We can transfer this information using three different modes of transfer.
1.Programmed I/O
2.Interrupt- initiated I/O
3.Direct memory access( DMA)
8259-Programmable Interrupt Controller (PIC)
The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and
8086 there are five hardware interrupts and two hardware interrupts respectively. By adding
8259, we can increase the interrupt handling capability. This chip combines the multi-interrupt
input source to single interrupt output. This provides 8-interrupts from IR0 to IR7.
Need for 8259-PIC
8259- PIC Architecture
8259 Pin diagram
• The Fig. shows the connection
between 8085/8086 and 8259A.
• The 8259A is a commonly used
priority interrupt controller, which is
specifically designed for use with
interrupt signals INTR and INTA of
Intel series.
• It is packaged in a 28 pin DIP. It uses
NMOS technology and requires a
single + 5V supply.
10 M Questions
1. With neat functional block diagram, explain the 8255 programmable peripheral interface and its operating
modes?
2. Draw and discuss the internal architecture of USART 8251.
3. Explain the operation of 8259 Programmable Interface Controller with a neat diagram.
4. (a) Explain different types of semiconductor memories.
(b) Interface two 4K×8 EPROMS and two4K×8 RAM chips with 8086.
5. With a neat diagram, explain in detail about DMA controller.
6. (a) With neat block diagram explain ADC interfacing with 8086.
(b) With neat block diagram explain DAC interfacing with 8086.
7.

8. (a) Explain How stepper motor is interfacing with 8086.

(b) Write an ALP to rotate Stepper motor clock wise and ani-clock wise direction.
2Maks Questions
1. What is the difference between serial and parallel communication?
2. Write different types of data transfer methods?
3. List the Applications Hardware and software interrupts?
4. What is the need of PIC?
5. What is the difference between RAM and ROM?
6. What is DMA and how DMA initiated?
7. Difference between Asynchronous and Synchronous communication?
8. Define baud-rate?
9. What are the features of 8255.
10.What is USART? List Features of 8251
11.Features of PIC microcontroller.
12.Features of 8237
13.List the operating modes of 8255.