CXD3301R

10-bit, 36Msps CCD Signal Processor

Description
The CXD3301R processes (correlated double 48 pin LQFP (Plastic)
sampling, programmable gain amplifier) the signals
output from a CCD image sensor and performs
conversion from analog signals to digital signals.

Features
• CCD signal processing
— Correlated double sampling (CDS)
— Programmable gain amplifier (PGA)
Absolute Maximum Ratings
Gain range: –6 to +42dB
• Supply voltage AVDD, DVDD 4.0 V
• 10-bit resolution
• Supply voltage difference (between AVDD pins)
No missing code guaranteed
±0.1 V
• Ground voltage difference (between AVSS pins)
Applications
±0.1 V
CCD cameras
• Digital input voltage –0.3 to +5.3 V
• Analog input voltage –0.3 to AVDD + 0.3 V
Structure
• Storage temperature Tstg –55 to +125 °C
Silicon gate CMOS IC

Note) If stress larger than the values listed under

Absolute Maximum Ratings is applied, the
device may be permanently damaged. Also
note that applying the absolute maximum
rating for long periods of time may affect the
device reliability.

Recommended Operating Conditions

• Supply voltage AVDD, DVDD 3.0 to 3.6 V
• Operating temperature Topr –20 to +75 °C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

–1–
E01712
 CXD3301R

Block Diagram

CLPDM

XSHD

ADCK
XSHP

XRST
XCS

SCK
SI
23 21 22 45 46 47 48 16
AVDD6 40
AVDD5 34
AVDD4 33
Serial Timing
AVDD3 27 Interface Control
AVDD2 24
12 D9 (MSB)
AVDD1 18 Input
CCD Clamp 11 D8
Output 10 D7
Signal
9 D6
Correlated Programmable Analog
Double Gain –6dB
to Output 8 D5
30 to
Latch
Sampling Amplifier +42dB Digital 7 D4
CCDIN
(CDS) (PGA) Converter
6 D3
AVSS8 42
5 D2
AVSS7 41
4 D1
AVSS6 36
3 D0 (LSB)
AVSS5 35
AVSS4 26
AVSS3 25 Optical Black Reference Voltage
Preblanking
AVSS2 17 Clamp Generator

AVSS1 15
19 28 20 29 31 32 37 38 39 13 14
PBLK

C1

CLPOB

C2

C3

C4

C5

C6

C7

DVDD
DVSS
Pin Configuration
CCDIN
AVDD5

AVDD4

AVDD3
AVSS6

AVSS5

AVSS4

AVSS3
C4

C3

C2

C1

36 35 34 33 32 31 30 29 28 27 26 25

C5 37 24 AVDD2

C6 38 23 CLPDM

C7 39 22 XSHD

AVDD6 40 21 XSHP

AVSS7 41 20 CLPOB

AVSS8 42 19 PBLK

NC 43 18 AVDD1

NC 44 17 AVSS2

XRST 45 16 ADCK

XCS 46 15 AVSS1

SI 47 14 DVSS

SCK 48 13 DVDD

1 2 3 4 5 6 7 8 9 10 11 12
NC

NC

D0 (LSB)

D1

D2

D3

D4

D5

D6

D7

D8

D9 (MSB)

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 CXD3301R

Pin Description

Pin
Symbol Type Description
No.
1 NC — (Always leave open.)
2 NC — (Always leave open.)
3 D0 (LSB) DO Bit 0, A/D output (LSB)
4 D1 DO Bit 1, A/D output
5 D2 DO Bit 2, A/D output
6 D3 DO Bit 3, A/D output
7 D4 DO Bit 4, A/D output
8 D5 DO Bit 5, A/D output
9 D6 DO Bit 6, A/D output
10 D7 DO Bit 7, A/D output
11 D8 DO Bit 8, A/D output
12 D9 (MSB) DO Bit 9, A/D output (MSB)
13 DVDD P Power supply for digital output driver
14 DVSS P GND for digital output driver
15 AVSS1 P Analog GND
16 ADCK DI Master clock
17 AVSS2 P Analog GND
18 AVDD1 P Analog power supply
19 PBLK DI Preblanking (High: Normal output, Low: All 0 output)
20 CLPOB DI Optical black clamp pulse
21 XSHP DI CCD signal precharge level sampling pulse
22 XSHD DI CCD signal data level sampling pulse
23 CLPDM DI Dummy bit clamp pulse
24 AVDD2 P Analog power supply
25 AVSS3 P Analog GND
26 AVSS4 P Analog GND
27 AVDD3 P Analog power supply
28 C1∗2 AO Optical black clamp circuit reference
29 C2∗3 AO Internal reference P
30 CCDIN AI CCD signal input
31 C3∗4 AO Internal reference C
32 C4∗3 AO Internal reference N
33 AVDD4 P Analog power supply
34 AVDD5 P Analog power supply
35 AVSS5 P Analog GND
36 AVSS6 P Analog GND

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 CXD3301R

Pin
Symbol Type Description
No.
37 C5∗4 AO A/D converter in-phase mode voltage
38 C6∗4 AO A/D converter high potential reference
39 C7∗4 AO A/D converter low potential reference
40 AVDD6 P Analog power supply
41 AVSS7 P Analog GND
42 AVSS8 P Analog GND
43 NC — (Always leave open.)
44 NC — (Always leave open.)
45 XRST DI IC internal reset input (High: Normal operation, Low: Reset operation)
46 XCS DI Serial communication microcomputer strobe input (for various internal settings)
47 SI DI Serial communication microcomputer data input (for various internal settings)
48 SCK DI Serial communication microcomputer clock input (for various internal settings)
∗1 Type column symbols
P: Power supply or GND, DI: Digital input, DO: Digital output, AI: Analog input, AO: Analog output
∗2 Connect to GND through an approximately 0.1µF capacitor.
∗3 Connect to GND through an approximately 390pF capacitor.
∗4 Connect to GND through an approximately 0.1µF capacitor.

–4–
 CXD3301R

General Characteristics

Item Symbol Conditions Min. Typ. Max. Unit

Maximum clock rate fADCKMAX 36 MHz
A/D converter
Resolution 10 Bit
Differential nonlinearity error PGA gain = 0dB ±0.5 LSB
Integral nonlinearity error PGA gain = 0dB ±1 LSB
No missing code Guaranteed
Programmable gain amplifier (PGA)
Gain adjustment resolution 1023 steps
Settable range –6 42 dB
PGA gain
Default (Code = 0080h) 0 dB
Optical black clamp circuit
Level adjustment resolution 15 steps
Settable range 0 60 LSB
Optical black clamp level
Default (Code = 1000) 32 LSB
∗ Unless otherwise noted, the above values are for Ta = 25°C, AVDD = DVDD = 3.3V, clock rate (fADCK = 36MHz),
and no load.

Electrical Characteristics

Item Symbol Conditions Min. Typ. Max. Unit

Power supply
AVDD = DVDD = 3.3V,
PCMAX 165 180 mW
Power consumption fADCK = 36MHz, no load
PCSTB Standby mode 9 11 mW
Analog input
PGA gain = 0dB,
Maximum input signal level 900 mV
full scale output
Input capacitance CINA 15 pF
Digital input
VIH 2.1 V
Input voltage
VIL 1.1 V
Input capacitance CIND 5 pF
Digital output
VOH IOH = –2mA 2.7 V
Output voltage
VOL IOL = 2mA 0.4 V
∗ Unless otherwise noted, the above values are for Ta = 25°C, AVDD = DVDD = 3.3V, clock rate (fADCK = 36MHz),
and no load.

–5–
 CXD3301R

Timing Specifications

The timing chart below shows an example of the XSHP, XSHD and ADCK phase relationships relative to the
signals output from the CCD image sensor. In the CXD3301R, the A/D converter clock is generated
automatically by the timing generator circuit built into the device based on XSHP and XSHD. The digital output
timing is synchronized with the rising edge of ADCK.
See "Electrical Characteristics" for the XSHP, XSHD and ADCK threshold voltages.

CCDOUT N–1 N N+1 N+2 N+3

tWP tS tCKP

XSHP
tPD tDP
tWD tS tCKP

XSHD
tINHIBIT
tADC tADC tCKP

ADCK
tOD

90%
D[9:0] N – 11 N – 10 N–9 N–8
10%

Item Symbol Min. Typ. Max. Unit

Clock period tCKP 27.7 ns
ADCK pulse width tADC 13.8 ns
XSHP pulse width tWP 6.9 ns
XSHD pulse width tWD 6.9 ns
Sampling delay tS 3 ns
Time from XSHP ↑ to XSHD ↓ tPD 4 ns
Time from XSHD ↑ to XSHP ↓ tDP 8 ns
Time from XSHD ↑ to ADCK ↑
(This prescribes the ADCK ↑ prohibited period.)
tINHIBIT∗1 12 ns

Output delay time tOD 18∗2 ns

Data latency DL 9 (Fixed) clock
∗1 When tINHIBIT is set to 12ns or less, the A/D converter may experience latch-up and it may not be possible to
obtain normal images. In addition, when tINHIBIT is set to approximately 0ns, the data latency value changes.
∗2 Load capacitance: 10pF

–6–
 CXD3301R

Serial Interface

The CXD3301R's serial interface is comprised of a 2 bytes long register, and is controlled by the two signals
XCS and SCK. When data of 2 bytes or more is loaded, the last 2 bytes are valid, and the initially loaded data
is lost. The data is reflected after 6 ADCK clock periods.
Avoid serial communication during the effective pixel period. Otherwise, the operation of the logic circuit block
inside the CXD3301R may affect the analog circuit block, causing the picture quality to deteriorate.

tXS tXH

XCS

tCKH tCKL tCKP

SCK
tDS tDH

SI D15 D14 D13 D00

2 bytes

Item Symbol Min. Typ. Max. Unit

Clock period tCKP 100 ns
Clock pulse width (High) tCKH 40 ns
Clock pulse width (Low) tCKL 40 ns
Data setup time tDS 30 ns
Data hold time tDH 30 ns
Time from XCS ↓ to SCK ↑ tXS 30 ns
Time from SCK ↑ to XCS ↑ tXH 30 ns

–7–
 CXD3301R

The CXD3301R has the three serial communication categories of standby mode, PGA gain and optical black
clamp level. The data for one category is set by one communication. When performing consecutive
communication, leave a period of 5 ADCK clocks between the rise of XCS for previous communication and the
fall of XCS for next communication. Table 1 shows the serial data format. Do not change bits noted as "Fixed"
in the table. The CXD3301R's serial interface is MSB first, so transmit the data from the MSB.

Table 1. Serial Data Format

Category
Bit
Standby mode PGA gain Optical black clamp level
D15 (MSB) 0 (Fixed) 0 (Fixed) 0 (Fixed)
D14 0 (Fixed) 0 (Fixed) 0 (Fixed)
D13 0 (Fixed) 0 (Fixed) 1 (Fixed)
D12 0 (Fixed) 1 (Fixed) 0 (Fixed)
D11 0 (Fixed) 0 (Fixed) 0 (Fixed)
D10 0 (Fixed) 0 (Fixed) 0 (Fixed)
D09 0 (Fixed) G9 0 (Fixed)
D08 0 (Fixed) G8 0 (Fixed)
D07 0 (Fixed) G7 0 (Fixed)
D06 0 (Fixed) G6 0 (Fixed)
D05 0 (Fixed) G5 0 (Fixed)
D04 0 (Fixed) G4 0 (Fixed)
D03 0 (Fixed) G3 O3
D02 0 (Fixed) G2 O2
D01 0 (Fixed) G1 O1
D00 (LSB) C0 G0 O0

Table 2 shows the setting contents and default values for each category. In the CXD3301R, the serial setting
values are set to the default values by performing reset. The reset pulse width (low period) is 100ns (min.).
Be sure to perform power-on reset. The setting values are undetermined at power-on, so correct operation is
not possible unless power-on reset is performed.

Table 2. Setting Contents and Default Setting Values for Each Category

Category Setting contents Default

C0 = 0: Normal drive
Standby mode C0 C0 = 0: Normal drive
C0 = 1: Standby mode
G[9:0] = 0080h
PGA gain G[9:0] See "Programmable Gain Amplifier".
Gain: 0dB
O[3:0] = 1000
Optical black clamp level O[3:0] See "Optical Black Clamp".
Clamp level: 32 LSB

–8–
 CXD3301R

Description of Functions

The CXD3301R processes (correlated double sampling, programmable gain amplifier) the signals output from
a CCD image sensor and performs conversion from analog signals to digital signals. The output from the CCD
image sensor is first sent to the CDS block. After that it is sent to the A/D converter block via the
programmable gain amplifier (PGA) block.

Programmable Gain Amplifier (PGA)

The programmable gain amplifier (PGA) block can control the gain value by inputting a digital code via the
serial interface. See Fig. 1 PGA Gain Characteristics for the relationship between the input digital code and the
gain. The control range is from –6 to +42dB.

42

36

30

24
Gain [dB]

18

12

–6
0000 0080 0100 0180 0200 0280 0300 0380 03FF
(Default)
Code [hex]

Fig. 1 PGA Gain Characteristics

–9–
 CXD3301R

Optical Black Clamp

The optical black clamp level can be set by the serial interface. (See Table 3.) See "Serial Interface" for the optical
black clamp level setting method.

Table 3. Input Codes and Set Optical Black Clamp Level

O[3:0]
Clamp level
Decimal notation O3 O2 O1 O0
0 0 0 0 0 0 LSB
1 0 0 0 1 4 LSB
2 0 0 1 0 8 LSB
3 0 0 1 1 12 LSB
4 0 1 0 0 16 LSB
5 0 1 0 1 20 LSB
6 0 1 1 0 24 LSB
7 0 1 1 1 28 LSB
8 (Default) 1 0 0 0 32 LSB
9 1 0 0 1 36 LSB
10 1 0 1 0 40 LSB
11 1 0 1 1 44 LSB
12 1 1 0 0 48 LSB
13 1 1 0 1 52 LSB
14 1 1 1 0 56 LSB
15 1 1 1 1 60 LSB

Standby Mode

The CXD3301R has a standby mode, and can suppress power consumption. Activation of standby mode and
recovery from standby mode is controlled via the serial interface. The serial interface and register are active
even in standby mode.

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 CXD3301R

Application Circuit

CCD AMP

Timing

4.7µ

0.1µ
4.7µ

0.1µ
Generator

390p

390p
AVDD

0.1µ

0.1µ

0.1µ
AVDD

AVDD
36 35 34 33 32 31 30 29 28 27 26 25 4.7µ
AVSS6

AVSS5

AVDD5

AVDD4

C4

C3

CCDIN

C2

C1

AVDD3

AVSS4

AVSS3
0.1µ
37 C5 24
0.1µ AVDD2 0.1µ
38 C6 CLPDM 23
0.1µ
39 C7 XSHD 22
0.1µ AVDD
40 AVDD6 XSHP 21
AVDD
41 AVSS7 CLPOB 20
4.7µ 4.7µ
42 AVSS8 PBLK 19

43 NC AVDD1 18
AVSS 0.1µ
AVDD 44 NC AVSS2 17

45 XRST ADCK 16

100k 46 XCS AVSS1 15

0.1µ 47 SI DVSS 14
0.1µ 4.7µ
48 SCK DVDD 13
AVSS
NC

NC

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

DVDD

1 2 3 4 5 6 7 8 9 10 11 12 DVSS

Serial Bus 100 100 100 100 100 100 100 100 100 100
DSP

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 11 –
 CXD3301R

Package Outline Unit: mm

48PIN LQFP (PLASTIC)

9.0 1.6MAX

7.0 1.4 ± 0.05 0.05 S

D 0.145 ± 0.055

36 25

37 24
A B

48 13

1 12
C
X4 0.5 X4
0.2 C A-B D 0.2 H A-B D 0.08 C
0.22 ± 0.05
0.08 M C A-B S D S

0.25

0.1 ± 0.05
0.6 ± 0.15
(1.0)

0˚ to 7˚

DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN

SONY CODE LQFP-48P-L122 LEAD TREATMENT SOLDER PLATING

JEITA CODE P-LQFP48-7.0x7.0-0.5 LEAD MATERIAL COPPER ALLOY

JEDEC CODE MS-026-BBC PACKAGE MASS 0.18g

LEAD SPECIFICATIONS

ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
LEAD TREATMENT Sn-Bi 2.5%
LEAD TREATMENT THICKNESS 5-18µm

– 12 – Sony Corporation