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    analog lab report (2)

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    Sourabh

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    analog lab report (2)

    Uploaded by

    Sourabh
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    © All Rights Reserved
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    Download as docx, pdf, or txt
    1 views27 pages

    analog lab report (2)

    Uploaded by

    Sourabh

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 27

    Q1-1 ans

    Fig 1

    For Nmos Ids vs vds graph plotted


    Q1-2ans

    Fig2

    Boundary point at between the exponential and quadratic regions((VGST-Vt), IDsat)=

    (0.407813,1.2814uamps)
    Fig3
    To find n value we got sensitivity as 1/11.86 on doing below calculation we got n=1.4
    Q1-3 ans

    Fig4

    On changing VDS values in Nmos, Vth values has been changed


    Q1-4 ans

    Fig5

    Max gm in NMOS obtained at vgs 1.2812v and Vov =1.2812-0.36=0.9212v vt(library file)=0.36 , at
    maximum gm IDsat observed in below plot is 367uamp. hence (0.912,367uamp) observed
    Fig 6

    At vgs 1.2812 ID sat =367uamps observed


    Q1-5 ans

    Fig7

    For Pmos Id vs vds graph plotted


    Fig 8

    Boundary point at between the exponential and quadratic regions((VGST-Vt), IDsat)=

    (-0.49375,2.25uamps)
    Fig9

    To find n value IN PMOSwe got sensitivity as 1/10.783 on doing below calculation we got n=1.5
    Fig 10

    ON changing VDs values Vth values are observed and plotted


    Fig 11

    Max gm in PMOS obtained at vgs -2.24v and Vov = Vov is Vsg-|Vt|=2.24-0.388=1.464 and
    vt(libraryfile)=-0.388 , at maximum gm IDsat observed idsat =730uamps (1.464,730uamps)
    Fig 12

    At vgs =-2.25714 idsat =730uamps observed

    Q1-6

    Transistor model Exponential Region(V) Quadratic Region(V) Linear Region(V)


    NMOS 0 to 0.4078 0.4078 to 1.2812 1.282 to 1.8
    PMOS 0 to -0.4937 -0.4937 to -2.24 -2.24 and 3
    Table 1
    Q2

    Fig13

    NMOS id vs Vds plot


    Fig14

    Vth observed =0.314

    Fig15
    Fig 16
    3Q ans
    Fig17

    For Lmin=0.18um W=0.4067um observed and its gm values


    Fig 18

    For L=5um W=11.32um observed and its gm values

    Negative capacitance

    observed that Cgs and Cbs is negative values the spice is giving the outputs as negative values though
    the values calculated by hand calculation is positive this is due to a convention followed by the
    simulation tool
    Q4

    Fig 19

    Case1:W/L=1u/0.2u

    For Vd value=10mv various gm values obtained


    4)

    Fig 20

    For Vd value=0.2v various gm values obtained


    Fig 21

    For Vd value=1v various gm values obtained


    Fig 22

    For Vd value=1.8v various gm values obtained


    Fig 23

    Case2: W/L ratio=10u/2u

    For Vd value=10mv various gm values obtained


    Fig 25

    For Vd value=0.2v various gm values obtained


    Fig 26

    For Vd value=1v various gm values obtained


    Fig 27

    For Vd value=1.8v various gm values obtained

    Observation: For case (1) the W/L ratio is 5 and for Case (2) W/L is 2,we observed that as W/L
    increases the gm value increases and we have seen this through simulation

    For Vd is 10mv we can see that gm value is low for the both cases Vd is less sensitive to gm and for
    values 0.2v,1v and 1.8v as the transistor wil be in saturation and ids is almost independent of vds as id is
    almost constant in saturation gm also constant

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