International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056

Volume: 04 Issue: 05 | May -2017 www.irjet.net p-ISSN: 2395-0072

Power Optimized Voltage Level Shifter Design for High Speed

Dual Supply Application
Seethal T S1, Mohamed Salih k k2,
1Mtech scholar, Department of ECE, GECI, Kerala, India
2Assistant Professor, Department of ECE, GECI, Kerala, India
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Abstract Reduction of power consumption has always Circuit designers are faced with the challenge of developing
been major design goal in energy harvesting digital devices. systems with increasing functionality and complexity while
One effective way for low power design use of multiple under demanding power and time-to-market constraints.
voltages depends on their speed. This, however, accomplish the Such systems often require voltage level translation devices
use of interface block called level converters or level shifters. to allow interfacing between integrated circuit devices built
This paper presents a modified structure of level shifter for from different process technologies. The choice of the proper
lower power implementation. Simulation results of proposed voltage level translation device depends on many factors and
structure in a 0.18-um CMOS technology show that the design will affect the performance and efficiency of the circuit
of input low supply voltage of 0.4V and high supply voltage of application. Thus voltage level shifters play an important
1.8V, the level shifter has a propagation delay of 12.5ns and a role in widely used VLSI systems.
power dissipation of 87.7nW for a 1-MHz input signal. Then Voltage level translation is needed when two devices have
comparison is done against these level shifters in terms of differing supply voltage nodes. Two possible conditions
power, speed and power delay product. exist. A higher-voltage device may be needed to drive a low-
voltage device. A lower-voltage device may be needed to
Key Words: CMOS, level converter, subthreshold operation, drive a high-voltage device.
Dual supply circuits, power delay product. If the low voltage device is the driver, the circuit typically
cannot function properly without the use of a translation
1. INTRODUCTION device.

Power efficiency and speed are major factor of performance

in all digital circuits. Various techniques have used to reduce
dynamic and static power. On the other hand, reducing the
supply voltage increases the propagation delay of the circuits
[2]. In order to avoid these problems dual supply Fig-1: Voltage levelshifter functioning
architecture are introduced in which a low voltage (VddL) is
supplied for the blocks on the noncritical paths while a high
supply voltage (VddH) is applied to the analog and the high- 2. EXISTING LEVEL SHIFTER IMPLEMENTATION
speed digital blocks. Some of the most commonly used In this section, circuit configuration and advantages of two
techniques are dynamic voltage scaling operating down to level converters recently reported will be briefly explained.
near threshold voltage levels and supporting multiple The operation of the circuit shown in Fig.2, is as follows.
voltage domains .That is why Level shifting circuit is needed When the input signal becomes high transistor Mn1 turns on
to provide exact voltage level for the circuit. A voltage level and nmos transistor Mn4 turns on because the overdrive
shifter is one of the major components in a digital system. voltage of Mp3 larger than the Mn3. Therefore transition
Level shifters are used for provide correct voltage level for current flows Mp1, Mn1, and Mn4 and this current is
each component in the digital circuits. mirrored to Mp2 and tries to pull up the output node. Finally
A wide variety of level shifters have been proposed in the the output is pulled up and the transistor Mp3 turned off
literature review. Designers move their attention to consequently nmos transistor Mn4 pull down by the nmos
implement a voltage level shifter, which operates minimum transistor Mn3, means no static current flows through Mp1,
power consumption and maximum speed. Moreover the Mn1, and Mn4.
level shifter must able to operate correctly for subthreshold If the input is low and INB is high, the nmos transistor Mn2
input signals. Some of the recently reported high conducts and pulls down the output node at the same time
performance voltage level shifters are reviewed. The nmos transistor Mn1 off and no static current flows. This
proposed circuit introduced in section 3. Section 4 presents means that current of Mp2 is not completely close to zero
the simulation result of the modified circuit verifying the weak contention exist. Further reduce the value of current
efficiency of the proposed circuit. Finally, concluded in another device Mp4 is used.
section 5.

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 04 Issue: 05 | May -2017 www.irjet.net p-ISSN: 2395-0072

3. PROPOSED VOLTAGE LEVEL SHIFTER CIRCUIT

A new power optimized proposed voltage level shifter is

introduced. Here the power gating technology is
implemented for power optimization.
Power gating is the circuit design technique that has been
most widely used in industrial products, means connecting
sleep transistor to combination of pull up pull down network
to reduce the subthreshold leakage current. A sleep
transistor is separating the pull up network from Vdd and
pull down network from Vss.

Fig-1: Circuit diagram of voltage level shifter [1]

2.1 EXTENSION OF LEVEL SHIFTER WITH
AUXILIARY CIRCUIT

In order to further reduction of power and delay as an

extension of voltage level shifter with auxiliary circuit is
used, shown in Fig.2. Auxiliary circuit turns only high to low
transition of input signal and to pull up the node Qc to a
value larger than VddL.
Transistor Mn6, Mn7 and Mp6 are turned on and nmos
transistor Mn5 turned off, therefore transition current flows
through Mn6, Mn7, Mp6 are mirrors to Mp7 and pull up the
node QC. Fig-3: Proposed Voltage level shifter

Sleep transistor SL separates transistor Mp4 from Vdd and

SL bar separates nmos transistor Mn5 from Vss. During
active mode SL=0, sleep transistor turns on and provide low
resistance in the conduction path. Circuit cut off from its
power supply in sleep mode SL=1 by means of current
switch.

4. SIMULATION RESULTS

The voltage level shifter design in fig.1 was implemented in

180 nm by using cadence virtuoso software. Then the
transient analysis is obtained as in fig.5.

Fig -2: Extension of voltage level shifter with auxiliary circuit

[1]

The strength of pull-up devices is significantly reduced when

the pull down device is pulling down the output node, but
the strength of pull down device is also increased using a low
power auxiliary circuit. Fig-4: Implementation of voltage level shifter

The power consumption of voltage level shifter can be

classified in two static power consumption and dynamic
power consumption. Static power dissipation caused from

2017, IRJET | Impact Factor value: 5.181 | ISO 9001:2008 Certified Journal | Page 549
 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 04 Issue: 05 | May -2017 www.irjet.net p-ISSN: 2395-0072

leakage current in the CMOS based integrated circuits.

Leakage power is minimized only in standby mode. This is
lower than dynamic power dissipation, which arises due to
charging and discharging of load capacitance. For 180 nm
technology the total power consumption of the voltage level
shifter was found to be 172.9nW. Delay of voltage level
shifter was found to be 62.1ns.

FIG-7: Implementation of Proposed Voltage Level Shifter

The simulation results were compared in table: 1.

Table-1: Comparison Results of Voltage Level shifters

Fig-5: Transient analysis of voltage level shifter
Designs(180nm) Average Delay(ns) Power
In order to further reduction of power and delay as an power(nW) Delay
extension of voltage level shifter with auxiliary circuit is Product
used [1]. Level shifter with auxiliary circuit was (nW.ns)
implemented in fig-6 and power and delay calculated. Existing voltage 172.9nW 62.1ns 10737.09
level Shifter
Level Shifter with 166.01nW 12.1ns 2008.721
Auxiliary circuit
Proposed Voltage 87.57nW 12.5ns 1094.625
Level Shifter

FIG-6: Extension of Level shifter with Auxiliary circuit

Power and delay of level shifter with auxiliary circuit was

found to be 166.01nW and 12.1ns respectively. The
simulation was done in 180nm technology by cadence
virtuoso software.
The new proposed power optimized voltage level shifter was
implemented in fig-6. The average power consumption was
found to be 87.57nW. Power is reduced to 50% compared to Chart-1: Bar Diagram Representation of Simulation Result
other level shifter designs. The leakage power was
compressed by power gating technology.

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 International Research Journal of Engineering and Technology (IRJET) e-ISSN: 2395 -0056
Volume: 04 Issue: 05 | May -2017 www.irjet.net p-ISSN: 2395-0072

[8] A.Wang and A. P. Chandrakasan, A 180-mV

subthreshold FFT processor using a minimum energy
design methodology, IEEE J. Solid-State Circuits, vol. 40,
no. 1, pp. 310319, Jan. 2005.

Fig-8: Layout implementation of proposed voltage

level shifter

6. CONCLUSION

In this brief, a fast and low power voltage level shifting

design was proposed which is able to convert
extremely low values of input voltages. Both existing
and proposed designs were simulated using cadence
virtuoso tools. Average power dissipation of the
proposed design was reduced to half as compared to
existing voltage level shifter. The average power
dissipation was found to be 87.5nW. PDP of both
designs are measured and it is observed to be
minimum in the case of proposed design.

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