SG1626/SG2626/SG3626

Dual High Speed Driver

Description Features
The SG1626 series is a dual inverting monolithic high speed  Pin-to-Pin Compatible with DS0026, TSC426
driver that is pin-to-pin compatible with the DS0026, and ICL7667.
TSC426 and ICL7667. This device utilizes high voltage
 Totem Pole Outputs with 3.0 A Peak
Schottky logic to convert TTL signals to high speed outputs
Current Capability.
up to 18 V. The totem pole outputs have 3 A peak current
capability, which enables them to drive 1000 pF loads in  Supply Voltage to 22 V.
typically less than 25 ns. These speeds make it ideal for  Rise and Fall times less than 25 ns.
driving power MOSFETs and other large capacitive loads  Propagation Delays less than 20 ns.
requiring high speed switching.
 Inverting High-Speed High-Voltage Schottky Logic.
In addition to the standard packages, the 16-pin SOIC (DW-  Efficient Operation at High Frequency.
package) is available for commercial and industrial  Available in:
applications. These packages offer improved thermal
8 - Pin Plastic and Ceramic DIP
performance for applications requiring high frequencies and/
16 - Pin Plastic SOIC
or high peak currents.
8 - Pin TO-99
20 - Pin Ceramic LCC

High Reliability Features

 Available to MIL-STD-883, ¶ 1.2.1
 MSC-AMS level “S” Processing Available

Block Diagram
VCC

6.5 V
VREG

2.5 k 3k

INV. INPUT OUTPUT

GND

June 2015 Rev. 1.2 www.microsemi.com 1

© 2015 Microsemi Corporation
Absolute Maximum Ratings (Note 1)
Supply Voltage (VCC) ........................................................... 22 V Operating Junction Temperature
Logic Input Voltage ............................................................... 7 V Hermetic (T, Y - Packages) ........................................ 150°C
Source/Sink Output Current (Each Output) Plastic (M, DW, L- Packages) .......................................150°C
Continuous ................................................................... ±0.5 A Storage Temperature Range ............................ -65°C to 150°C
Pulse, 500 ns ................................................................ ±3.0 A Lead Temperature (Soldering, 10 s) .............................. 300°C
RoHS Peak Package Solder Reflow Temp. (40 s max. exp.).......... 260°C (+0, -5)
Note 1.
Exceeding these ratings could cause damage to the device.
All voltages are with respect to ground.
All currents are positive into the specified terminal.

Thermal Data
Y Package:
Thermal Resistance-Junction to Case, θ JC .................. 50°C/W L Package:
Thermal Resistance-Junction to Ambient, θ JA ............ 130°C/W Thermal Resistance-Junction to Case, θJC .................. 35°C/W
M Package: Thermal Resistance-Junction to Ambient, θ JA ........... 120°C/W
Thermal Resistance-Junction to Case, θ JC .................. 60°C/W
Thermal Resistance-Junction to Ambient, θ JA ............. 95°C/W Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
DW Package: Note B. The above numbers for θJC are maximums for the limiting
Thermal Resistance-Junction to Case, θ JC .................. 40°C/W thermal resistance of the package in a standard mounting
configuration. The θJA numbers are meant to be guidelines for
Thermal Resistance-Junction to Ambient, θ JA .............. 95°C/W the thermal performance of the device/pc-board system. All of
T Package: the above assume no ambient airflow.
Thermal Resistance-Junction to Case, θ JC .................. 25°C/W
Thermal Resistance-Junction to Ambient, θ JA ........... 130°C/W

Recommended Operating Conditions (Note 2)

Supply Voltage (VCC) ..................................4.5 V to 20 V (Note 3) Operating Ambient Temperature Range (TJ)
Frequency Range ........................................... DC to 1.5 MHz SG1626 ......................................................... -55°C to 125°C
Peak Pulse Current ............................................................ ±3 A SG2626 ........................................................... -25°C to 85°C
Logic Input Voltage ................................................ -0.5 to 5.5 V SG3626 .............................................................. 0°C to 70°C

Note 2. Range over which the device is functional.

Note 3. AC performance has been optimized for VCC = 8 V to 20 V.

Electrical Characteristics
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1626 with
-55°C ≤ TA ≤ 125°C, SG2626 with - 25°C ≤ TA ≤ 85°C, SG3626 with 0°C ≤ TA ≤ 70°C, and VCC = 20 V. Low duty cycle pulse
testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.)
SG1626/2626/3626
Parameter Test Conditions Units
Min. Typ. Max.
Static Characteristics
Logic 1 Input Voltage 2.0 V
Logic 0 Input Voltage 0.7 V
Input High Current VIN = 2.4 V 500 µA
Input High Current VIN = 5.5 V 1.0 mA
Input Low Current VIN = 0 V -4 mA
Input Clamp Voltage IIN = -10 mA -1.5 V
Output High Voltage (Note 4) IOUT = -200 mA VCC-3 V
Output Low Voltage (Note 4) IOUT = 200 mA 1.0 V
Supply Current Outputs Low VIN = 2.4 V (both inputs) 18 27 mA
Supply Current Outputs High VIN = 0 V (both inputs) 7.5 12 mA
Note 4. VCC = 10 V to 20 V.

2
Electrical Characteristics (Continued)
SG1626/2626/3626 SG1626
Parameter Test Conditions (Figure 1) TA= 25°°C TA=-55°°C to 125°°C Units
Min. Typ. Max. Min. Typ. Max.
Dynamic Characteristics (Note 6)
Propagation Delay High-Low CL = 1000 pF (Note 5) 18 30 ns
(TPHL) CL = 2500 pF 17 25 40 ns
Propagation Delay Low-High CL = 1000 pF (Note 5) 25 40 ns
(TPLH) CL = 2500 pF 25 35 50 ns
Rise Time (TTLH) CL = 1000 pF (Note 5) 30 35 ns
CL = 2500 pF 30 40 50 ns
Fall Time (TTHL) CL = 1000 pF (Note 5) 20 30 ns
CL = 2500 pF 30 40 50 ns
Supply Current (ICC) CL = 2500 pF, Freq. = 200 kHz
(both outputs) Duty Cycle = 50% 30 35 40 mA

Note 5. These parameters, specified at 1000 pF, although guaranteed over recommended operating conditions, are not 100% tested in production.
Note 6. VCC = 15 V.

AC Test Circuit and Switching Time Waveforms (Figure 1)

15 V

3.5 V 3.5 V

4.7 µF 0.1 µF
200 kHz
50 Ω
SG1626
10 ns
15 V

1k

Figure 1 · AC Test Circuit and Switching Time Waveforms

Characteristics Curves

200 kHz 200 kHz

200 kHz

Figure 2 · Transition Times vs. Supply Voltage Figure 3 · Propagation Delay vs. Supply Voltage Figure 4 · Transition Times vs. Ambient Temperature

3
Characteristics Curves (Continued)

15 V

200 kHz 200 kHz

15 V

kHz

Figure 5 · Propagation Delay vs. Ambient Temperature Figure 6 · Transition Times vs. Capacitive Load Figure 7 · Supply Current vs. Capacitive Load

15 V 15 V

10 k 100 k

Figure 8 · High Side Saturation vs. Output Current Figure 9 · Low Side Saturation vs. Output Current Figure 10 · Supply Current vs. Frequency

15 V

10 V

15 V

10 k 100 k

Figure 11 · Supply Current vs. Frequency

4
Application Information
POWER DISSIPATION a CK05 or CK06 ceramic operator with a CSR-13 tantalum
The SG1626, while more energy-efficient than earlier gold-doped capacitor is an effective combination. For commercial applica-
driver IC’s, can still dissipate considerable power because of its tions, any low-inductance ceramic disk capacitor teamed with a
high peak current capability at high frequencies. Total power Sprague 150D or equivalent low ESR capacitor will work well.
dissipation in any specific application will be the sum of the DC or The capacitors must be located as close as physically possible to
steady-state power dissipation, and the AC dissipation caused by the VCC pin, with combined lead and pc board trace lengths held
driving capacitive loads. to less than 0.5 inches.
GROUNDING CONSIDERATIONS
The DC power dissipation is given by:
Since ground is both the reference potential for the driver logic
PDC = +VCC · ICC [1] and the return path for the high peak output currents of the
driver, use of a low-inductance ground system is essential. A
where ICC is a function of the driver state, and hence is duty-cycle ground plane is highly recommended for best performance. In
dependent. dense, high performance applications a 4-layer pc board works
best; the 2 inner planes are dedicated to power and ground
distribution, and signal traces are carried by the outside layers.
The AC power dissipation is proportional to the switching fre- For cost-sensitive designs a 2-layer board can be made to
quency, the load capacitance, and the square of the output work, with one layer dedicated completely to ground, and the
voltage. In most applications, the driver is constantly changing other to power and signal distribution. A great deal of attention
state, and the AC contribution becomes dominant when the to component layout and interconnect routing is required for this
frequency exceeds 100-200 kHz. approach.
The SG1626 driver family is available in a variety of packages to LOGIC INTERFACE
accommodate a wide range of operating temperatures and The logic input of the 1626 is designed to accept standard DC-
power dissipation requirements. The Absolute Maximums sec- coupled 5 V logic swings, with no speed-up capacitors required.
tion of the data sheet includes two graphs to aid the designer in If the input signal voltage exceeds 6 V, the input pin must be
choosing an appropriate package for his design. protected against the excessive voltage in the HIGH state.
The designer should first determine the actual power dissipation Either a high speed blocking diode must be used, or a resistive
of the driver by referring to the curves in the data sheet relating divider to attenuate the logic swing is necessary.
operating current to supply voltage, switching frequency, and LAYOUT FOR HIGH SPEED
capacitive load. These curves were generated from data taken
on actual devices. The designer can then refer to the Absolute The SG1626 can generate relatively large voltage excursions
Maximum Thermal Dissipation curves to choose a package type, with rise and fall times around 20-30 nanoseconds with light
and to determine if heat-sinking is required. capacitive loads. A Fourier analysis of these time domain signals
will indicate strong energy components at frequencies much
DESIGN EXAMPLE higher than the basic switching frequency. These high frequen-
cies can induce ringing on an otherwise ideal pulse if sufficient
Given: Two 2500 pF loads must be driven push-pull from a
inductance occurs in the signal path (either the positive signal
+15 V supply at 100 kHz. This is a commercial application
trace or the ground return). Overshoot on the rising edge is
where the maximum ambient temperature is +50°C, and cost is
undesirable because the excess drive voltage could rupture the
important.
gate oxide of a power MOSFET. Trailing edge undershoot is
dangerous because the negative voltage excursion can forward-
1. From Figure 11, the average driver current consumption
bias the parasitic PN substrate diode of the driver, potentially
under these conditions will be 18 mA, and the power
causing erratic operation or outright failure.
dissipation will be 15 V x 18 mA, or 270 mW.
Ringing can be reduced or eliminated by minimizing signal path
2. From the Ambient Thermal Characteristic curve, it can be
inductance, and by using a damping resistor between the drive
seen that the M package, which is an 8-pin plastic DIP with a
output and the capacitive load. Inductance can be reduced by
copper lead frame, has more than enough thermal conductance
keeping trace lengths short, trace widths wide, and by using
from junction to ambient to support operation at an ambient
2oz. copper if possible. The resistor value for critical damping
temperature of +50°C. The SG3626M driver would be specified
can be calculated from:
for this application.
SUPPLY BYPASSING RD = 2√L/CL [2]
Since the SG1626 can deliver peak currents above 3 A under
some load conditions, adequate supply bypassing is essential where L is the total signal line inductance, and CL is the load
for proper operation. Two capacitors in parallel are capacitance. Values between 10 and 100 Ω are usually
recommended to guarantee low supply impedance over a wide sufficient. Inexpensive carbon composition resistors are best
bandwidth: a 0.1 µF ceramic disk capacitor for high frequencies, because they have excellent high frequency characteristics.
and a 4.7 µF solid tantalum capacitor for energy storage. In They should be located as close as possible to the gate terminal
military applications, of the power MOSFET.

5
Typical Applications

165 V

15 V

4.7 µF 0.1 µF

Figure 12.
When the SG3626 is driven from a totem-pole source with a peak output greater than 6 V, a low-current, fast-switching blocking
diode is required at each logic input for protection. In this push-pull converter, the inverted logic outputs of the 3527A are
ideal control sources for the power driver.

165 V

15 V

0.1 µF
4.7 µF

Figure 13.
In this forward converter circuit, the control capabilities of the SG3524B PWM are combined with the powerful totem-pole
drivers found in the SG3626. This inexpensive configuration results in very fast charge and discharge of the power
MOSFET gate capacitance for efficient switching.

6
Typical Applications (Continued)

115 V

4.7 µF 0.1 µF

Figure 14.
In half or full-bridge power supplies, driving the isolation transformers directly from the PWM can cause excessive IC
temperatures, especially above 100 kHz. This circuit uses the high drive capacity of the SG3626 to solve the problem.

15 V

4.7 µF 0.1 µF

115 V

UC3847

LM324

Figure 15.
A low-impedance resistive divider network can also be used as the interface between the PWM high-voltage logic output and
the SG3626 power driver. In this 200 kHz current mode converter, the UC3847 provides control, while the SG3626 provides
high power drive and minimizes ground spiking in the control IC.

7
Connection Diagrams and Ordering Information (See Notes Below)
Ambient
Package Part Number Connection Diagram
Temperature Range

8-PIN CERAMIC DIP SG1626Y-883B -55°C to 125°C N.C. 1 8 N.C.

Y - PACKAGE SG1626Y-DESC -55°C to 125°C 7
IN A 2
SG1626Y -55°C to 125°C
OUT A

3 6
GROUND VCC

4 5
IN B OUT B

8-PIN PLASTIC DIP SG2626M -25°C to 85°C

M - PACKAGE SG3626M 0°C to 70°C M Package: RoHS Compliant / Pb-free Transition DC: 0503
M Package: RoHS / Pb-free 100% Matte Tin Lead Finish

N.C. 1 16 N.C.
16-PIN WIDE BODY SG2626DW -25°C to 85°C IN A 2 15 OUT A
PLASTIC SOIC SG3626DW 0°C to 70°C N.C. 3 14 VCC
DW - PACKAGE
GROUND 4 13 GROUND

GROUND 5 12 GROUND

N.C. 6 11 VCC

IN B 7 10 OUT B
N.C. 8 9 N.C.

DW Package: RoHS Compliant / Pb-free Transition DC: 0516

DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish

8-PIN TO-99 METAL CAN SG1626T-DESC -55°C to 125°C VCC

T - PACKAGE OUT A 8 OUT B
1 7

N.C. 2 6 N.C.

3 5
IN A 4 IN B

GND

20-PIN CERAMIC (LCC) SG1626L-883B -55°C to 125°C 1. N.C. 3 2 1 20 19 11. N.C.

2. GROUND 12. N.C.
LEADLESS CHIP CARRIER 3. N.C. 4 18 13. OUT B
L- PACKAGE 4. IN A 14. N.C.
5 17
5. N.C. 15. Vcc
6 16
6. GROUND 16. N.C.
7 15
7. N.C. 17. Vcc
8 14
8. IN B 18. N.C.
9. N.C. 19. OUT A
9 10 11 12 13
10. GROUND 20. N.C.

Note 1. Contact factory for DESC product availability.

2. All packages are viewed from the top.
3. Hermetic Packages Y, T, & L use Sn63/Pb37 hot solder lead finish, contact factory for availability of RoHS versions.

8
Package Outline Dimensions
Controlling dimensions are in inches, metric equivalents are shown for general information.

MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
D
A 4.32 5.08 0.170 0.200
8 5 b 0.38 0.51 0.015 0.020
b2 1.04 1.65 0.045 0.065
E
c 0.20 0.38 0.008 0.015
11 4 D 9.52 10.29 0.375 0.405
E 5.59 7.11 0.220 0.280
e 2.54 BSC 0.100 BSC
eA
b2
eA 7.37 7.87 0.290 0.310
H 0.63 1.78 0.025 0.070
A
L 3.18 4.06 0.125 0.160
θ - 15° - 15°
Q c
L
Q 0.51 1.02 0.020 0.040
H e SEATING θ Note:
PLANE
b Dimensions do not include protrusions; these shall not
exceed 0.155 mm (.006”) on any side. Lead dimension shall
not include solder coverage.

Figure 16 · Y 8-Pin CERDIP Package Dimensions

MILLIMETERS INCHES
D DIM
MIN MAX MIN MAX
8 A - 5.08 - 0.200
A2 3.30 Typ. 1.30 Typ.
E1
b 0.38 0.51 0.145 0.020
11 b2 0.76 1.65 0.030 0.065
c 0.20 0.38 0.008 0.015
D - 10.16 - 0.400
b2
E E 7.62 BSC 0.300 BSC
e 2.54 BSC 0.100 BSC
A2 E1 6.10 6.86 0.240 0.270
A
L 3.05 - 0.120 -
θ 0° 15° 0° 15°
c
L Note:

H e
θ Dimensions do not include mold flash or protrusions; these
shall not exceed 0.155 mm (.006”) on any side. Lead
b dimension shall not include solder coverage.

Figure 17 · M 8-Pin PDIP Package Dimensions

9
Package Outline Dimensions (continued)

MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
A 2.06 2.65 0.081 0.104
A1 0.10 0.30 0.004 0.012
A2 2.03 2.55 0.080 0.100
B 0.33 0.51 0.013 0.020
c 0.23 0.32 0.009 0.013
D 10.08 10.50 0.397 0.413
E 7.40 7.60 0.291 0.299
e 1.27 BSC 0.05 BSC
H 10.00 10.65 0.394 0.419
L 0.40 1.27 0.016 0.050
θ 0° 8° 0° 8°
*LC - 0.10 - 0.004

* Lead co planarity
Note:
Dimensions do not include protrusions; these shall
not exceed 0.155 mm (.006”) on any side. Lead
dimension shall not include solder coverage.

Figure 18 · DW 16-Pin SOWB Package Dimensions

D MILLIMETERS INCHES
DIM
D1 MIN MAX MIN MAX
e
D 8.89 9.40 0.350 0.370
D1 8.00 8.51 0.315 0.335
A A 4.191 4.699 0.165 0.185
F
e1
b1 0.406 0.533 0.016 0.021
1
D2 F - 1.016 - 0.040
L1
SEATLbD e1 2.54 TYP 0.100 TYP
PLAbE
e 5.08 TYP 0.200 TYP
α k 8
k 0.711 0.864 0.028 0.034
L k1 0.737 1.143 0.029 0.045
L 12.70 14.48 0.500 0.570
k1
α 45° TYP 45° TYP
b1 D2 3.556 4.064 0.140 0.160
L1 0.254 1.016 0.010 0.040

Note:
Dimensions do not include protrusions; these shall
not exceed 0.155 mm (.006”) on any side. Lead
dimension shall not include solder coverage.

Figure 19 · T 8-Pin Metal Can TO-99 Package Outline Dimensions

10
Package Outline Dimensions (continued)
E3
D
MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
D/E 8.64 9.14 0.340 0.360
E3 - 8.128 - 0.320
E
e 1.270 BSC 0.050 BSC
B1 0.635 TYP 0.025 TYP
L 1.02 1.52 0.040 0.060
A 1.626 2.286 0.064 0.090
A
h 1.016 TYP 0.040 TYP
L2 L
A1 8 A1 1.372 1.68 0.054 0.066
A2 - 1.168 - 0.046
3 L2 1.91 2.41 0.075 0.95
B3 0.203R 0.008R
1
Note:
All exposed metalized area shall be gold plated 60 micro-
inch minimum thickness over nickel plated unless
13
otherwise specified in purchase order.
h
A2 18
B3
e
B1

Figure 20 · L 20-Pin Ceramic LCC Package Outline Dimensions

11
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SG1626-1.2/06.15