SG1524/SG2524/SG3524

Regulating Pulse Width Modulator

Description Features
This monolithic integrated circuit contains all the control  8V to 40V Operation
circuitry for a regulating power supply inverter or switching  5V Reference
regulator. Included in a 16-pin dual-in-line package is the  Reference Line and Load Regulation of 0.4%
voltage reference, error amplifier, oscillator, pulse width  100Hz to 300kHz Oscillator Range
modulator, pulse steering flip-flop, dual alternating output  Excellent External Sync Capability
switches and current limiting and shut-down circuitry. This  Dual 50mA Output Transistors
device can be used for switching regulators of either  Current Limit Circuitry
polarity, transformer coupled DC to DC converters,  Complete PWM Power Control Circuitry
transformerless voltage doublers and polarity converters, as
 Single Ended or Push-Pull Outputs
well as other power applications. The SG1524 is specified  Total Supply Current less than 10mA
for operation over the full military ambient temperature
range of -55°C to +125°C, the SG2524 for -25°C to +85°C,
and the SG3524 is designed for commercial applications of
High Reliability Features
Following are the high reliability features of SG1524:
0°C to +70°C.
 Available to MIL-STD-883, ¶ 1.2.1
 MIL-M38510/12601BEA SG1524J-JAN
 MSC-AMS Level “S” Processing Available
 Available to DSCC - Standard Microcircuit
Drawing (SMD)
Block Diagram

Figure 1 · Block Diagram

February 2015 Rev. 1.2 www.microsemi.com 1

© 2015 Microsemi Corporation
Absolute Maximum Ratings (Note 1)
Input Voltage (+VIN ) ............................................................. 42V Oscillator Charging Current ................................................ 5mA
Collector Voltage ................................................................ 40V Operating Junction Temperature
Logic Inputs ........................................................... -0.3V to 5.5V Hermetic (J, L Packages) ................................................. 150°C
Current Limit Sense Inputs ................................... -0.3V to 0.3V Plastic (N, D Packages) ................................................... 150°C
Output Current (each transistor) .................................... 100mA Storage Temperature Range ..............................-65°C to 150°C
Reference Load Current .................................................. 50mA Lead Temperature (Soldering, 10 seconds).....................300°C
Pb-free / RoHS Peak Package Solder Reflow Temp (40 sec. max.
Note 1: Values beyond which damage may occur. exposure)... 260°C (+0, -5)

Thermal Data
J Package:
Thermal Resistance-Junction to Case, θJC ............... 30°C/W Note A. Junction Temperature Calculation: TJ = TA + (PD x θJA).
Thermal Resistance-Junction to Ambient, θJA ........... 80°C/W Note B. The above numbers for θJC are maximums for the limiting
N Package: thermal resistance of the package in a standard mounting
Thermal Resistance-Junction to Case, θJC ............... 40°C/W configuration. The θJA numbers are meant to be
guidelines for the thermal performance of the device/pc-
Thermal Resistance-Junction to Ambient, θJA ........... 65°C/W
board system. All of the above assume no ambient
D Package:
airflow.
Thermal Resistance-Junction to Case, θJC ............... 50°C/W
Thermal Resistance-Junction to Ambient, θJA ......... 120°C/W
L Package:
Thermal Resistance-Junction to Case, θJC ........... .... 35°C/W
Thermal Resistance-Junction to Ambient, θJA ......... 120°C/W

Recommended Operating Conditions (Note 2)

Input Voltage (+VIN) ................................................... 8V to 40V Oscillator Frequency Range ......................... 100Hz to 300kHz
Collector Voltage ....................................................... 0V to 40V Oscillator Timing Resistor (RT) ........................ 1.8kΩ to 100kΩ
Error Amp Common Mode Range ..........................1.8V to 3.4V Oscillator Timing Capacitor (CT) ............................ 1nF to 1.0µF
Current Limit Sense Common Mode Range ........ -0.3V to 0.3V Operating Ambient Temperature Range
Output Current (each transistor) ............................... 0 to 50mA SG1524 ......................................................... -55°C to 125°C
Reference Load Current ........................................... 0 to 20mA SG2524 ........................................................... -25°C to 85°C
Oscillator Charging Current .................................. 30µA to 2mA SG3524 ............................................................... 0°C to 70°C
Note 2: Range over which the device is functional and parameter limits are guaranteed.

Electrical Characteristics
(Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1524 with -55°C ≤ TA ≤ 125°C, SG2524 with
-25°C ≤ TA ≤ 85°C, SG3524 with 0°C ≤ TA ≤ 70°C, and +V IN = 20V. Low duty cycle pulse testing techniques are used which maintains junction and
case temperatures equal to the ambient temperature.)

SG1524/SG2524 SG3524
Parameter Test Conditions Units
Min. Typ. Max. Min. Typ. Max.
Reference Section (Note 3)
Output Voltage TJ = 25°C 4.80 5.00 5.20 4.60 5.00 5.40 V
Line Regulation VIN = 8V to 40V 20 30 mV
Load Regulation IL = 0 to 20mA 50 50 mV
Temperature Stability (Note 7) Total Over Operating Temperature Range 50 50 mV
Output Voltage Range (Note 7) Over Line, Load and Temperature 4.80 5.20 4.60 5.40 V
Short Circuit Current VREF = 0V 25 50 150 25 50 150 mA
Note 3. IL = 0mA

2
Electrical Characteristics (Continued)
SG1524/SG2524 SG3524
Parameter Test Conditions Units
Min. Typ. Max. Min. Typ. Max.
Oscillator Section (Note 4)
Initial Accuracy TJ = 25°C 36 40 44 36 40 44 kHz
MIN ≤ TJ ≤ MAX 34 46 34 46 kHz
Voltage Stability VIN = 8V to 40V 0.1 1 0.1 1 %
Maximum Frequency RT = 2kΩ, CT = 1nF 200 400 200 400 kHz
Sawtooth Peak Voltage VIN = 40V 3 3.8 3 3.8 V
Sawtooth Valley Voltage VIN = 8V 0.6 1 1.2 0.6 1 1.2 V
Clock Amplitude 3.2 3.2 V
Clock Pulse Width 0.3 1.5 0.3 1.5 µs
Error Amplifier Section (Note 5)
Input Offset Voltage RS ≤ 2kΩ 0.5 5 2 10 mV
Input Bias Current 1 10 1 10 µA
Input Offset Current 1 2 µA
DC Open Loop Gain RL ≥10MΩ, TJ = 25°C 72 60 dB
Output Low Level VPIN 1 - VPIN 2 ≥ 150mV 0.2 0.5 0.2 0.5 V
Output High Level VPIN 2 - VPIN 1 ≥150mV 3.8 4.2 3.8 4.2 V
Common Mode Rejection VCM = 1.8V to 3.4V 70 dB
Supply Voltage Rejection VIN = 8V to 40V 55 dB
Gain-Bandwidth Product (Note 7) TJ = 25°C 1 2 1 2 MHz
P.W.M. Comparator (Note 4)
Minimum Duty Cycle VCOMP = 0.5V 0 0 %
Maximum Duty Cycle VCOMP = 3.6V 45 49 45 49 %
Current Limit Amplifier Section (Note 6)
Sense Voltage TJ = 25°C 190 200 210 180 200 220 mV
Input Bias Current 200 200 µA
Shutdown Section
Threshold Voltage TJ = 25°C 0.5 0.8 1.2 0.5 0.8 1.2 V
MIN ≤ TJ ≤ MAX 0.2 1.8 0.2 1.8 V
Output Section (each transistor)
Collector Leakage Current VCE = 40V 50 50 µA
Collector Saturation Voltage IC = 50mA 2 2 V
Emitter Output Voltage IE = 50mA 17 17 V
Collector Voltage Rise Time RC = 2kΩ 0.4 0.4 µs
Collector Voltage Fall Time RC = 2kΩ 0.2 0.2 µs
Power Consumption
Standby Current VIN = 40V 7 10 7 10 mA
Note 4. FOSC = 40kHz (RT = 2.9kΩ, CT = .01µF)
Note 5. VCM = 2.5V
Note 6. VCM = 0V
Note 7. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production.

3
Application Notes
OSCILLATOR
The oscillator in the SG1524 uses an external resistor RT to Note that for buck regulator topologies, the two outputs can be
establish a constant charging current into an external capacitor wire-ORed for an effective 0-90% duty cycle range. With this
CT. While this uses more current than a series-connected RC, it connection, the output frequency is the same as the oscillator
provides a linear ramp voltage at CT which is used as a time- frequency. For push-pull applications, the outputs are used
dependent reference for the PWM comparator. The charging separately; the flip-flop limits the duty cycle range at each output
current is equal to 3.6V/RT, and should be restricted to between to 0-45%, and the effective switching frequency at the trans-
30µA and 2mA. The equivalent range for RT is 100k to 1.8k. former is 1/2 the oscillator frequency.

The range of values for CT also has limits, as the discharge time If it is desired to synchronize the SG1524 to an external clock, a
of CT determines the pulse width of the oscillator output pulse. positive pulse may be applied to the clock pin. The oscillator
The pulse is used (among other things) as a blanking pulse to should be programmed with RT and CT values that cause it to
both outputs to insure that there is no possibility of having both free-run at 90% of the external sync frequency. A sync pulse
outputs on simultaneously during transitions. This output with a maximum logic 0 of +0.3 volts and a minimum logic 1 of
deadtime relationship is shown in Figure 2. A pulse width below +2.4 volts applied to Pin 3 will lock the oscillator to the external
0.35 microseconds may cause failure of the internal flip-flop to source. The minimum sync pulsewidth should be 200
toggle. This restricts the minimum value of CT to 1000pF. (Note: nanoseconds, and the maximum is determined by the required
Although the oscillator output is a convenient oscilloscope sync deadtime. The clock pin should never be driven more negative
input, the probe capacitance will increase the pulse width and than -0.3 volts, nor more positive than +5.0 volts. The
decrease the oscillator frequency slightly.) Obviously, the upper nominal resistance to ground is 3.2k at the clock pin, ±25%
limit to the pulse width is determined by the modulation range over temperature.
required in the power supply at the chosen switching frequency.
Practical values of CT fall between 1000pF and 0.1µF, although If two or more SG1524's must be synchronized together, program
successful 120 Hz oscillators have been implemented with one master unit with RT and CT for the desired frequency.
values up to 5µF and a series surge limit resistor of 100 ohms. Leave the RT pins on the slaves open, connect the CT pins to
the CT of the master, and connect the clock pins to the clock pin
The oscillator frequency is approximately 1/RT•CT; where R is in of the master. Since CT is a high-impedance node, this sync
ohms, C is in microfarads, and the frequency is in Megahertz. technique works best when all devices are close together.
For greater accuracy, the chart in Figure 3 may be used for a
wide range of operating frequencies.

20 100k

10 50k

5 20k

2 10k

1 5k

0.5
2k

0.2 1k
.001 .002 .005 .01 .02 .05 0.1 500 1k 2k 5k 10k 20k 50k 100k 200k 500k

Figure 2 · Output Stage Deadtime vs. CT Figure 3 · Oscillator Frequency vs. RT and CT

4
Application Notes (Continued)
CURRENT LIMITING A second factor to consider is that the response time is
The current limiting circuitry of the SG1524 is shown in Figure 4. relatively slow. The current limit amplifier is internally
By matching the base-emitter voltages of Q1 and Q2, and compensated by R1, C1, and Q1, resulting in a roll-off pole at
assuming a negligible voltage drop across R1: approximately 300 Hz. A third factor to consider is the bias
current of the C.L. sense pins. A constant current of
C.L. Threshold = VBE(Q1) + I1• R2 - VBE(Q2) = I1• R 2 approximately 150µA flows out of Pin 4, and a variable current
~ 200 mV with a range of 0-150µA flows out of Pin 5. As a result, the
equivalent source impedance seen by the current sense pins
Although this circuit provides a relatively small threshold with a should be less than 50 ohms to keep the threshold error less
negligible temperature coefficient, there are some limitations to than 5%.
its use because of its simplicity.
Since the gain of this circuit is relatively low (42 dB), there is a
The most important of these is the limited common-mode voltage transition region as the current limit amplifier takes over pulse
range: ±0.3 volts around ground. This requires sensing in the width control from the error amplifier. For testing purposes,
ground or return line of the power supply. Also precautions threshold is defined as the input voltage required to get 25% duty
should be taken to not turn on the parasitic substrate diode of the cycle (+2 volts at the error amplifier output) with the error amplifier
integrated circuit, even under transient conditions. A Schottky signaling maximum duty cycle.
clamp diode at Pin 5 may be required in some configurations to
APPLICATION NOTE: If the current limit function is not used on
achieve this.
the SG1524, the common-mode voltage range restriction re-
quires both current sense pins to be grounded.

Figure 4 · Current Limiting Circuitry of the SG1524

1k 1k
5k 5k 5k
5k

5k
5k
5k 1k
5k
2k
1k
2k
3k

20k

50k

In this conventional single-ended regulator circuit, the two out- Push-pull outputs are used in this transformer-coupled DC-DC
puts of the SG1524 are connected in parallel for effective 0 - 90% regulating converter. Note that the oscillator must be set at twice
duty-cycle modulation. The use of an output inductor requires the desired output frequency as the SG1524's internal flip-flop
and R-C phase compensation network for loop stability. divides the frequency by 2 as it switches the PWM signal from
one output to the other. Current limiting is done here in the
primary so that the pulse width will be reduced should transformer
saturation occur.

5
Connection Diagrams and Ordering Information (See Notes Below)

Package Ambient Connection Diagram

Part No.
Temperature Range
16-PIN CERAMIC DIP SG1524J-883B -55°C to 125°C INV. INPUT 1 16 VREF
J - PACKAGE SG1524J-JAN -55°C to 125°C N.I. INPUT 2 15 +VIN
SG1524J-DESC -55°C to 125°C OSC. OUTPUT 3 14 EB
+C.L. SENSE 4 13 CB
SG1524J -55°C to 125°C
-C.L. SENSE 5 12 CA
SG2524J -25°C to 85°C RT 6 11 EA
SG3524J 0°C to 70°C CT 7 10 SHUTDOWN
GROUND 8 9 COMPENSATION

16-PIN PLASTIC DIP SG2524N -25°C to 85°C

N - PACKAGE SG3524N 0°C to 70°C N Package: RoHS / Pb-free Transition DC: 0503*. 100% Matte Tin Lead Finish

16-PIN NARROW BODY SG2524D -25°C to 85°C INV. INPUT 1 16 VREF

PLASTIC SOIC SG3524D 0°C to 70°C N.I. INPUT 2 15 +VIN
D - PACKAGE OSC. OUTPUT 3 14 EB
+C.L. SENSE 4 13 CB
-C.L. SENSE 5 12 CA
RT 6 11 EA
CT 7 10 SHUTDOWN
GROUND 8 9 COMPENSATION

RoHS / Pb-free transition DC:0440

Pb-free / RoHS 100% Matte Tin Lead Finish*

20-PIN CERAMIC SG1524L-883B -55°C to 125°C 1. N.C.

3 2 1 20 19
11. COMP
LEADLESS CHIP CARRIER SG1524L -55°C to 125°C 2. VREF 12. SHUTDOWN
L- PACKAGE 3. INV. INPUT 4 18 13. N.C.
4. N.I. INPUT 5 17 14. EA
5. OSC. OUTPUT 15. CA
6 16
6. + C.L. SENSE 16. N.C.
7. - C.L. SENSE 7 15 17. CB
8. RT 8 14 18. EB
9. CT 19. N.C.
10. GROUND 20. +VIN
9 10 11 12 13

*RoHS compliant

Note 1. Contact factory for JAN product availablity.

2. All packages are viewed from the top.
3. Hermetic Packages J & L use Pb37/Sn63 hot solder lead finish, contact factory for availability of RoHS versions.

6
 Package Outline Dimensions

Package Outline Dimensions

Controlling dimensions are in inches, metric equivalents are shown for general information.

MILLIMETERS INCHES
D DIM
MIN MAX MIN MAX
16 9 A - 5.08 - 0.200
b 0.38 0.51 0.015 0.020
E b2 1.04 1.65 0.045 0.065
1 8 c 0.20 0.38 0.008 0.015
b2 eA D 19.30 19.94 0.760 0.785
E 5.59 7.11 0.220 0.280
e 2.54 BSC 0.100 BSC
Q A
eA 7.37 7.87 0.290 0.310
H 0.63 1.78 0.025 0.070
Seating Plane
L c L 3.18 5.08 0.125 0.200
θ θ - 15° - 15°
H e b
Q 0.51 1.02 0.020 0.040

Note:
Dimensions do not include protrusions; these shall not
exceed 0.155mm (.006”) on any side. Lead dimension
shall not include solder coverage.

Figure 5 · J 16-Pin Ceramic Dip

MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
A - 5.33 - 0.210
D
A1 0.38 - 0.015 -
A2 3.30 Typ. 0.130 Typ.
E1
b 0.36 0.56 0.014 0.022
1 b1 1.14 1.78 0.045 0.070
b1 c 0.20 0.36 0.008 0.014
E D 18.67 19.69 0.735 0.775
e 2.54 BSC 0.100 BSC
A2
A
c
E 7.62 8.26 0.300 0.325
A1
E1 6.10 7.11 0.240 0.280
L
L 2.92 0.381 0.115 0.150
e
b
SEATING PLANE θ θ - 15° - 15°

Note:
Dimensions do not include protrusions; these shall not
exceed 0.155mm (.006”) on any side. Lead dimension
shall not include solder coverage.

Figure 6 · N 16-Pin Plastic Dual Inline Package Dimensions

7
Package Outline Dimensions(continued)
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 1.52 0.049 0.060
b 0.33 0.51 0.013 0.020
c 0.19 0.25 0.007 0.010
D 9.78 10.01 0.385 0.394
E 5.79 6.20 0.228 0.244
e 1.27 BSC 0.050 BSC
H 3.81 4.01 0.150 0.158
L 0.40 1.27 0.016 0.050
Θ 0 8 0 8
*LC - 0.10 - 0.004
*Lead Coplanarity
Note:
Dimensions do not include mold flash or protrusions;
these shall not exceed 0.155mm (.006”) on any side.
Lead dimension shall not include solder coverage.

Figure 7 · D 16-Pin Plastic SOIC

E3
D
MILLIMETERS INCHES
DIM
MIN MAX MIN MAX
D/E 8.64 9.14 0.340 0.360
E3 - 8.128 - 0.320
E
e 1.270 BSC 0.050 BSC
B1 0.635 TYP 0.025 TYP
L 1.02 1.52 0.040 0.060
A 1.626 2.286 0.064 0.090
A
h 1.016 TYP 0.040 TYP
L2 L
A1 8 A1 1.372 1.68 0.054 0.066
A2 - 1.168 - 0.046
3 L2 1.91 2.41 0.075 0.95
B3 0.203R 0.008R
1 Note:
All exposed metalized area shall be gold plated 60 micro-
inch minimum thickness over nickel plated unless
13 otherwise specified in purchase order.

h
A2 18
B3
e
B1

Figure 8 · L 20-Pin Ceramic LCC Package Outline Dimensions

8
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SG1524.1.2/02.15