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A
Project Report
ON

“build a circuit to implement 4 bit adder”

SUBMITTED TO

MAHARASHTRA STATE BORD OF TECHNICAL EDUCATIONS.

MUMBAI
BY

Mr. Yash Mahadeo Gaikwad

UNDER GUIDENCE OF

PROF:-Mule Madam
DEPARTMENT OF COMPUTER

A.C.S’S
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DIPLOMA IN ENGINEERING AND TECHNOLOGY, ASHTI

(2024-2025)

A.C.S.’S
DIPLOMA IN ENGINEERING AND TECHNOLOGY,
ASHTI – 414203

CERTIFICATE
This is certify that the project Report entitled

“Build a Circuit to implement 4 Bit Adder

Submitted by
1.Yash Mahadeo Gaikwad (24512010129)
2.Sagar Santosh khade (24512010133)
3.satish dilip sapte (24512010130)

In The Academic Year 2024-2025 In The Partial Fulfilment Of Second Year Diploma
Engineering It Is Certified That All Suggestions Indicated For Internal Assessment Have Been Incorporated
In report . The Project Has Been Approved As It Satisfies The Academic Requirement In Respect Work
Prescribed For The Said Degree .

Mrs.Solse.S. .Dhonde S. A Bodkhe.S.C.

(Guide) (H.O.D.) Principle

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Results of the comparison can be clearly summarized in the following tables.

K TA

RCA 2*n 7*n+2

CSKA (n – 1)^0.5 4*k 8*n+6*k-6

CSLA 0.5*(8*n – 7)^0.5-0.5 2*k+2 14n-5k-5

CLA 2*log(n)+4 1.5*n*log(n)+4*n+5

Equations for Time delay (T) and Area (A) complexity of each architecture.

RCA CSKA CSLA CLA

T A T*A K T A T*A K T A T*A T A T*A

2 4 16 64 1 4 16 64 1.621 5.243 14.89 78.08 6 16 96

4 8 30 240 1.732 6.928 36.39 252.1 3.036 8.071 35.82 289.1 8 33 264

8 16 58 928 2.646 10.58 73.87 781.8 4.839 11.68 82.81 966.9 10 73 730

16 32 114 3648 3.873 15.49 145.2 2250 7.278 16.56 182.6 3023 12 165 1980

32 64 226 14464 5.568 22.27 283.4 6312 10.66 23.32 389.7 9086 14 373 5222

Different architectures delay (T) and area (A) for different number of bits (n).

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phase and the simulation phase.

In the research phase, the team had to compare different adder

architectures clearly defining the

advantages and disadvantages of each one in terms of area and delay to

be able to choose what

could be the most efficient adder architecture for the design of a 4-bit
adder. Another essential

task in the research phase was to decide on the gate level

implementation of the circuit, compare

the different logic families’implementations for each gate, and finally

decide on the proper logic

family implementation for each gate in light of the project objectives

stated beforehand.

Once the research phase was accomplished, the team had to move on to
the simulation phase. In

the simulation phase, the team had to design each gate separately and
optimize it to achieve the

optimum delay and powerconsumption,thensimulate a 1-bit full adder,

and finally simulate the

whole 4-bit adder. The simulation phase concludes the project by

estimating the worst case delay

of the 4-bit adder design and the average power consumption of the
circuit.

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Assumptions Design Criteria The group members are not

designing this adder for a very specific application that
dictates certain design criteria or puts different weights
on timedelay or circuit area, that is why group members
assumed it is better to implement a design that balances
between time delay, power consumption and area used
in the implementation of the 4-bit adder without giving
different weights to any of the design criteria. Therefore,
the design criteria will be [A*(T^2)*(P^2)] (T: time delay,
A: area, P: power) not T^2*A or T*A^2. Half Adder As the
project description is to design a 4 bit adder, group
members assumed they have 8 inputs which are the 2
sets of 4 bi Assumptions Design Criteria The group
members are not designing this adder for a very specific
application that dictates certain design criteria or puts
different weights on timedelay or circuit area, that is why
group members assumed it is better to implement a
design that balances between time delay, power
consumption and area used in the implementation of the
4-bit adder without giving different weights to any of the
design criteria. Therefore, the design criteria will be
[A*(T^2)*(P^2)] (T: time delay, A: area, P: power) not
T^2*A or T*A^2. Half Adder As the project description is
to design a 4 bit adder, group members assumed they
have 8 inputs which are the 2 sets of 4 bits to be
added, so in the design it is more efficient in
Research Phase
“Research is formalized curiosity.” In this section,
the team presents the results of the research
phase which was an integral part of the project.
Research phase was divided into 3 sub phases:

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adder architectures comparison, gate level

implementation of the chosen architecture, and
logic
families’ comparison for gates of the chosen gate
level implementation. The results the team
came up with from each sub phase is of paramount
importance for the 4-bit adder design.
Adder Architectures Comparison
In this section, a short description of the adder
architecture and the exact time delay (T) and area
(A) complexity based on unit gate model is
presented. In the unit gate model each gate has a
gate-count of one and a gate-delay of one
excluding XOR and XNOR gates having gate counts
and gate delays of two, while the gates with more
than 2 inputs, the gate-counts and gate-delays
can be computed in terms of the ones given for the
gates with two inputs; also, inverters and
buffers are ignored.
Ripple Carry Adder (RCA)is the simplest carry-
propagate adder.Its time delay and area
complexity are as followsforan n-bit RCA adder:
T = 2n
A = 7n + 2
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Carry Skip Adder (CSKA) is the concatenation

scheme with a carry-skip scheme. Its time delay
and area complexity are as follows for an n-bit
CSKA adder:
K= (n – 1) ½
T = 4k
A = 8n + 6k – 6
Carry Select Adder (CSLA) is the concatenation
scheme with a selection scheme. Its time delay
and area complexity are as follows for an n-bit
CSLA adder:
K = 1/2*(8n – 7)½
–½
T = 2k + 2
A = 14n – 5k – 5
Carry Look Ahead Adder (CLA) uses direct parallel-
prefix scheme for carry computation. Its
time delay and area complexity are as follows for
an n-bit CLA adder:
T = 2 log(n) + 4
A = 3/2*n*log(n) + 4n + 5 terms of delay, area, and
power to design a half bit adder for the first bit
adder as there is no carry-in bit for the first adder.
This will show great performance improvement
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because the Cout bit will be result of 2 gate delays

instead of 3.ts to be added, so in the design it is
more efficient in terms of delay, area, and power
to design a half bit adder for the first bit adder as
there is no carry-in bit for the first adder. This will
show great performance improvement because the
Cout bit will be result of 2 gate delays instead of 3.

Gate Level Implementation of the Full Adder In this

section, a description of the gate level
implementation of the 4-bit ripple carry adder is
presented. After the group agreed on
implementing ripple carry adder, it was crucial to
research what available gate level implementation
are there for the full adder, and mainly 3
implementations were compared. Implementation
1 uses only NAND gates to implement the logic of
the full adder. Implementation 2 uses 2 XOR gates
and 3 NAND to implement the logic.
Implementation 3 uses 2 XOR, 2 AND and 1 OR to
implement the

Research Phase “Research is formalized curiosity.” In this

section, the team presents the results of the research phase
which was an integral part of the project. Research phase
was divided into 3 sub phases: adder architectures
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comparison, gate level implementation of the chosen

architecture, and logic families’ comparison for gates of the
chosen gate level implementation. The results the team
came up with from each sub phase is of paramount
importance for the 4-bit adder design. Adder Architectures
Comparison In this section, a short description of the adder
architecture and the exact time delay (T) and area (A)
complexity based on unit gate model is presented. In the
unit gate model each gate has a gate-count of one and a
gate-delay of one excluding XOR and XNOR gates having
gate counts and gate delays of two, while the gates with
more than 2 inputs, the gate-counts and gate-delays can be
computed in terms of the ones given for the gates with two
inputs; also, inverters and buffers are ignored. Ripple Carry
Adder (RCA)is the simplest carry-propagate adder.Its time
delay and area complexity are as followsforan n-bit RCA
adder: T = 2n A = 7n + 2 Carry Skip Adder (CSKA) is the
concatenation scheme with a carry-skip scheme. Its time
delay and area complexity are as follows for an n-bit CSKA
adder: K= (n – 1) ½ T = 4k A = 8n + 6k – 6 Carry Select Adder
(CSLA) is the concatenation scheme with a selection scheme.
Its time delay and area complexity are as follows for an n-bit
CSLA adder: K = 1/2*(8n – 7)½ – ½ T = 2k + 2 A = 14n – 5k – 5
Carry Look Ahead Adder (CLA) uses direct parallel-prefix
scheme for carry computation. Its time delay and area
complexity are as follows for an n-bit CLA adder: T = 2 log(n)
+ 4 A = 3/2*n*log(n) + 4n + 5

Logic Families Comparison for XOR and NAND of full adder

In this section, a description for the different logic families to implement XOR
and NAND gates
of the full adder gate level implementation that was agreed upon in the
previous section.
XOR gate has mainly 3 implementations:
Complementary Pass-transistor Logic XOR
(CPL)
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The main advantage of the CPL logic family

is that it uses few numbers of transistors so
in terms of area it has an edge over other
implementations. However, CPL has a
reduced swing so it cannot be used as the
output of any adder since according to
project description; reduced swing at the
output is unacceptable.
Schematic: XOR CPL implementation
Double Pass-transistor LogicXOR(DPL)
The main advantages of the DPL logic
family is that its delay is low since always 2
transistors are ON in any charging or
discharging input combinations.Also it has
an advantage over the CPL that it has a full
swing at the output and uses a reasonable
number of gates.
Schematic: XOR DPL implementation
Transmission gateXOR(TG)
Transmission gate is another implementation
for the XOR function. However, its worst
case delay is probably higher that the DPL
since when A is HIGH only 1 transistor is
charging or discharging the output compared
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to two in the DPL implementation. So in

terms of delay DPL has an edge over
transmission gate. However, it uses less
number of transistors than DPL.

 NAND gate has mainly 3 implementations: CPL NAND Schematic: NANDCPL

implementation NAND DPL Schematic: NANDDPL implementation CMOS
NAND CMOS logic family has an advantage over DPL that it uses less number of
transistors (no need for inverters), and has an edge over CPL that its output is
full swing. Schematic: NANDCMOS implementation

 Testing Circuit Logic Output To prove that the adder is working and producing
correct logic, we did some waveform tests: We put these input combinations, and
monitor the output form: 0101+ xy01where x is a pulse from 0 to 1 For instance
when x=0 & y=1, output should be 1010 When x=0 & y=0, output should be 0110
When x=1 & y=0, output should be 1110 And the output waveform figure below
proves that the adder produces the expected output Note: x resembles B3, y
resembles B2, MSB for sum=S3, then S2 The following graph shows the output of
the adder.
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 After comparing the different logic families in the different logic families in terms
of swing, delay, and area, the team made some educated assumptions. First of all
for the XOR, the CPL was excluded since the project description a full swing
output. So, comparing DPL and transmission gate, the group assumed it is more
efficient to use DPLXORas XOR gatesmust be very fast since it is on the track of
propagation of the delay. As for the NAND gate, it is also important for it to be
fast but still we need the output to be full swing, so the team assumed it is more
efficient to implement 2 CPL NAND gates which outputs are input to a CMOS
NAND to ensure full swing at the output (thanks to its Pull-Up Network).
Another reason for choosing CMOS NAND to calculate the carry-out is that it
uses only 4 transistors compared to DPL that needs 8 because it requires
inverters at the inputs. The following schematic shows the logic family of each
gate in the project

 Simulation Phase “Simplicity is the ultimate sophistication”. In this section, the

team presents results of the simulation for the 4-bit adder. Since optimization is a
very complex task as delay, area, and power are all affected whenever size of
transistors are changed, the team decided to simply design each gate separately
first to ensure the logic is correct, then optimize it to find the size that gives the
lowest worst case delay and lowest power consumption for each gate. Then,
concatenate gates together to form the 1-bit full adder and 1-bit half adder,
before actually implementing the whole 4-bit adder and estimating the worst case
delay and the average power consumption of the adder. As the project objective
is to balance area, power and delay, and since the group has chosen Ripple Carry
Adder Architecture that has an edge over other architectures that it requires less
area, the group decided that during optimization they will give higher weight to
time delay and power over area to ensure this balance(because it is know that
RCA is disadvantageous when it comes to speed). Optimization of the logic gates
Optimization is finding optimum values of transistor W/L that would achieve the
desired performance balance between area, power and delay. Note: during
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optimization and simulation of individual gates, a 40fF capacitor was put at the
output terminal (CL) and frequency pulse used was 10 MHz. Also, higher weights
was given to power and delay as the team’s decision to use ripple carry adder
gives the adder an edge in terms of area, so it can give away part of this
advantage to ensure low delay and power consumption. However, in the overall
balance is the ultimate goal of the design.

This proves that using the CMOS NAND instead of the CPL NAND is actually a better
option. Measuring
our cost functionA*T*Pfor:
4-bit RCA using CPL NAND: cost function= 524.86
4-bit RCA using CMOS NAND: cost function= 174.98
It is obvious that using CMOS NAND is a great and major improvement in the
performance of the adder,
and is surely considered instead of the CPL NAND.

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