FPGA Based Implementation of 2D Discrete Cosine Transform Algorithm

FPGA Based Implementation Of 2D
Discrete Cosine Transform Algorithm

CONTENT
Introduction
DCT
2D DCT
Literature survey
Limitations
Proposed method
INTRODUCTION
Main reason for development key technique in image
and video compression standards viz. JPEG and MPEG.
DCT Converts Spatial domain frequency domain
Efficient hardware implementations requires low
complexity design.
The reason for its use in image compression is because of
its energy compaction characteristics.
Its performance is closely related to that of KLT (Karhunen-
Loeve Transform) which is known to be optimal.
DCT
Purpose-to remove inter-pixel redundancy.2 types :
Spatial redundancy
Spectral redundancy
DCT expresses data points as a sum of cosine
functions oscillating at different frequencies.
General approach used in DCT:
Image pixel values blocks 8x8 apply DCT
Block size of 8x8 is preferred as larger block sizes
increases the computational complexity.
2D DCT
The 2D DCT of 8X8 is defined as:
Where c(u) = c(v) = 1/2 for u = v = 0;

c(u) = c(v) = 1 for u, v = 1 to 7.
Two approaches to compute 2D DCT:
Row column decomposition method
Direct computation method
Literature survey
1. K. R. Rao [1] presented an algorithm to compute DCT
using Fast Fourier Transform (FFT) is developed.
2. N. I. Cho [2] presented a new algorithm for the fast
computation of a 2-D discrete cosine transform (DCT)
is by directly working on 2D DCT data set and using
direct polynomial approach.
3. In [3] Paris Kitsos and Nikolaos S. Voros paper
presents two high performance FPGA architectures
for the computation of 2D DCT. The two architectures
are 2D_DCT_2ROM and 2D_DCT_4ROM.
Conti
4. In [20] R. Uma presented a linear, highly pipelined
direct polynomial fast 2-D DCT algorithm for hardware
implementation.
5. A linear, highly pipelined, parallel algorithm and
architecture have been proposed and implemented by
S. Ramachandran [5] for 2D-DCT and Quantization
but it was an EPLD based architecture. The algorithm
was based on parallel matrix multiplication method.
6. E. Aggarawal [6] implemented an architecture based
on algorithm in [5] for Two Dimensional Discrete
Cosine Transform on FPGA.
Limitations
1. Direct 2D DCT approach has higher control
complexity than row column decomposition therefore
later gives advantage of regularity and modularity in
the architecture.
2. The architecture in which DA is used, all multipliers
are replaced by ROMs and adders therefore requires
a large number of ROMs
3. A heavy pipelined architecture results in latency in
the output.
Proposed method
In the algorithm used the 2D DCT is defined as
Z=
Where X is input image matrix, C is the cosine
coefficient and is its transpose. It can be expressed in
expanded form as in (2)
Conti.
In the proposed work row column method for
implementing 2D DCT will be used based on parallel
matrix multiplication.
A parallel architecture will be implemented in which the
eight partial products, which are the row vectors of CX
generated in the first stage, are fed to the next stage
Computation of(i+l) th partial products of CX and the i
th row DCT coefficients can be done simultaneously since
the i th partial products of CX are already available.
Pipelining and optimization of arithmetic operators will be
performed for high throughput and reduced latency
Schedule
No. Target Months/ days
1. Studying Verilog coding 31st January
2. Basic design implementation 20th February
3. Working on pipelined architecture and 10th March

analysis of different adders and
multipliers
4. Implementation of the improved design 25th March

and Paper writing
5. Result analysis 31st March
6. Thesis writing 25th April

References
1. N. Ahmed, T.Natarajan, and K.R. Rao, Discrete Cosine Transform, IEEE Trans.
Commun., vol, COM-23, pp. 90-93, Jan. 1974
2. Nam Ik Cho, Sang Uk Lee Fast Algorithm and Implementation of 2-D Discrete Cosine
Transform, IEEE Transaction on Circuits and Systems, Vol.38,No.3, March 1991
3. Paris Kitsos and Nikolaos S. Voros, A High Speed FPGA Implementation of the 2D DCT
for Ultra High Definition Video Coding Digital Signal Processing (DSP), 18th
International Conference on Digital Signal Processing, DSP 2013
4. R. Uma, Fpga implementation of 2d-dct for jpeg image compression, International
Journal of Advanced Engineering Sciences and Technologies (IJAEST), vol. 7, no. 1,
2011.
5. S. Ramachandran, S. Srinivasan and R. Chen, "EPLD-based Architecture of Real Time
2D-Discrete Cosine Transform and Quantization for Image Compression", IEEE
International Symposium on Circuits and Systems (ISCAS '99), Orlando, Florida, May-
June 1999
6. Ekta Aggrawal, Nishant Kumar High throughput pipelined 2D Discrete cosine
transform for video compression, IEEE Internationai Conference on Issues and
Challenges in Intelligent Computing Techniques (ICICT), 2014
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FPGA Based Implementation Of 2D

Discrete Cosine Transform Algorithm

Where c(u) = c(v) = 1/2 for u = v = 0;

1. Studying Verilog coding 31st January

2. Basic design implementation 20th February

3. Working on pipelined architecture and 10th March

4. Implementation of the improved design 25th March

5. Result analysis 31st March

6. Thesis writing 25th April

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