Report A4

Assignment 4
Sudhanva Joshi - 202310202022

20-10-2024
1 Pass Transistor based MUX, Sizing

To minimize the average delay from input (A or B) to output (Y) in a pass-transistor
logic-based MUX, we size the transistors as follows with transistor length L = 0.18 µm.
Given:
Cout
H= =2
Cin
To achieve optimal performance, the widths are chosen in the following ratios:
NMOS width = Wn , PMOS width = Wp
Note: Voltage levels are adjusted for clarity. We observed rise and fall times on our
waveforms, corroborating with printed values for time instances.
(a) Ratio, Wp = 4, Wn = 2 (b) Ratio, Wp = 5, Wn = 1
Figure 1: Wp > Wn
(a) Ratio, Wp = 2, Wn = 4 (b) Ratio, Wp = 1, Wn = 5
Figure 2: Wp < Wn
1
The netlist used is given below (netlist given in folder).
Figure 3: Q1 Netlist
2
The following readings are observed:
Figure 4: Wp = 3, Wn = 3
Our optimal ratio is approximately when ratios are Wp = 1W & Wn = 5W .

Note: This is calculated by trial and error substitution of various width ratios, & as a
result is only an approximation. This can be verified by observing our waveform curve
falloffs.
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2 Pass Transistor MUX, Shannon’s Expansion
We know Shannon’s Expansion for given boolean function with n inputs is:
f (x1 , x2 , . . . , xn ) = xi · f (1, x2 , . . . , xn ) + x′i · f (0, x2 , . . . , xn )
The given function which we will expand is as follows.
f (x1 , x2 , x3 , x4 ) = x1 · x2 + x1 · x3 + x1 · x4 + x2 · x3 + x3 · x4 + x2 · x4
Expanding our function:
f (x1 , x2 , x3 , x4 ) = x1 · (x2 + x3 + x4 ) + x′1 · (x2 x3 + x2 x4 + x3 x4 )
f (x2 , x3 , x4 ) = x2 · (x3 + x4 ) + x′2 · (x3 x4 )
f = x1 · (x2 + x3 + x4 ) + x′1 · (x2 · (x3 + x4 ) + x′2 · (x3 · x4 ))
Converting MUX into OR & AND Gates as:
Figure 9: MUX Gate Conversions
2.1 Circuit Diagram

Given below is the Circuit Diagram for our expanded function.
Figure 10: Circuit Diagram
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2.2 NGSpice Netlist
Note: We use 2 inverter chains as repeaters to get clean proper voltage levels for our
signals (Complete netlist is in folder).
Figure 11: Q2 Netlist
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Our Input Signals are run as follows (Voltages adjusted for clarity).
(a) Input Signals

(b) Truth Table
This can also be verified by a quick Verilog Simulation.
Figure 13: Verilog Cross-Check
2.3 Minimum Transition Time

Assuming we have taken the following definitions:
Rise Time (trise ): Time taken for a signal to transition from 10% to 90% of its
maximum value.
Fall Time (tf all ): Time taken for a signal to transition from 90% to 10% of its
maximum value.
We’ll analyze our graphs with respect to the corresponding co-ordinates for the given
voltage levels.
10% of 1.8V = 0.18V
90% of 1.8V = 1.62V
Figure 15: Rise Time Values
Figure 16: Fall Time Values
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(a) Time Rise (b) Time Fall
Figure 14: Comparison of Rise and Fall Times
Our minimum trise & tf all (approximately) are:
trise ≈ 4.309 · 10−11 s
tf all ≈ 2.577 · 10−10 s

The I/O combinations corresponding to these readings are:
Inputs, Minimum Rise Time:
f (x1 = 1, x2 , x3 , x4 )
Inputs, Minimum Rise Time:
f (x1 = 0, x2 , x3 , x4 )
Paths for charging and discharging the circuit output are observed in the initial circuit
diagram.
2.4 Equalizing Transition Times

To ensure balanced charging and discharging paths, the circuit design requires:
Equal Transistor Count: Charging path (VDD to output) and discharging path
(output to ground) should have an equal number of transistors of the same size.
Repeaters: Insert inverters at appropriate nodes to maintain signal integrity and
drive strength.
This setup helps achieve minimal delay by balancing the pull-up and pull-down strengths
effectively.
7
3 GCD Design
Initialize Registers: On reset, both registers for A and B are set to zero.
Load Inputs: When the load signals are active, inputs A and B are loaded into
their respective registers.
Swap Operation: If the swap signal is high, the values in registers A and B are
exchanged.
Subtraction Operation: If the subtract signal is active, the value of B is sub-
tracted from A, and the result is stored in A.
Output Result: The result Z is updated based on the current values of A and
B; if either register is zero or if A = B, Z holds the non-zero or equal value.
3.1 State Diagram

Our states are defined as follows.
S0 → Begin (Initial)
S1 → Swap
S2 → Subtract
S3 → End
Given conditions and outputs are described here.
X>0 (if X > 0)
X≥Y (if X ≥ Y )
Subtract: X = X − Y
Swap: X, Y if X < Y
Load: Load X, Load Y
Figure 17: State Diagram
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3.2 Circuit Diagram
The next state expressions can be defined as follows:
N S1 = (S0 ∧ (XR > 0) ∧ (XR ≥ Y R)) ∨ (S2 ∧ (XR > 0))
N S0 = (S0 ∧ (XR > 0) ∧ (XR < Y R)) ∨ (S1 ∧ (XR > 0))
where:
S0 , S1 , S2 , and S3 represent the current states.
XR > 0 and XR ≥ Y R are input conditions guiding state transitions.
The logical operations are denoted as:
∧ for AND
∨ for OR
Given below is the Circuit Diagram related to Control Unit.
Figure 18: Circuit Diagram
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3.3 Control Unit Implementation
Given below is the FSM implementation related to Control Unit.
Figure 19: FSM Module
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3.4 Datapath Unit Implementation
Given below is the FSM implementation related to Datapath Unit.
Figure 20: Datapath Module
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We use the following testbench for both c. and d.
Figure 21: Testbench Module
12
3.5 GCD Compute
Figure 22: GCD Solution
Figure 23: Testbench Readings
13

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Assignment 4

Sudhanva Joshi - 202310202022

1 Pass Transistor based MUX, Sizing

(a) Ratio, Wp = 4, Wn = 2 (b) Ratio, Wp = 5, Wn = 1

(a) Ratio, Wp = 2, Wn = 4 (b) Ratio, Wp = 1, Wn = 5

Our optimal ratio is approximately when ratios are Wp = 1W & Wn = 5W .

f (x1 , x2 , . . . , xn ) = xi · f (1, x2 , . . . , xn ) + x′i · f (0, x2 , . . . , xn )

The given function which we will expand is as follows.

Expanding our function:

f (x1 , x2 , x3 , x4 ) = x1 · (x2 + x3 + x4 ) + x′1 · (x2 x3 + x2 x4 + x3 x4 )

f (x2 , x3 , x4 ) = x2 · (x3 + x4 ) + x′2 · (x3 x4 )

f = x1 · (x2 + x3 + x4 ) + x′1 · (x2 · (x3 + x4 ) + x′2 · (x3 · x4 ))

Converting MUX into OR & AND Gates as:

Figure 9: MUX Gate Conversions

2.1 Circuit Diagram

Figure 10: Circuit Diagram

Figure 11: Q2 Netlist

(a) Input Signals

This can also be verified by a quick Verilog Simulation.

Figure 13: Verilog Cross-Check

2.3 Minimum Transition Time

Figure 15: Rise Time Values

Figure 16: Fall Time Values

Figure 14: Comparison of Rise and Fall Times

Our minimum trise & tf all (approximately) are:

trise ≈ 4.309 · 10−11 s

tf all ≈ 2.577 · 10−10 s

Inputs, Minimum Rise Time:

2.4 Equalizing Transition Times

3.1 State Diagram

Figure 17: State Diagram

N S1 = (S0 ∧ (XR > 0) ∧ (XR ≥ Y R)) ∨ (S2 ∧ (XR > 0))

 XR > 0 and XR ≥ Y R are input conditions guiding state transitions.

The logical operations are denoted as:

Given below is the Circuit Diagram related to Control Unit.

Figure 18: Circuit Diagram

Figure 19: FSM Module

Figure 20: Datapath Module

Figure 21: Testbench Module

Figure 22: GCD Solution

Figure 23: Testbench Readings

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XR > 0 and XR ≥ Y R are input conditions guiding state transitions.