Soumen Ghosh

SOUMEN GHOSH
Dublin, CA 94568 [email protected]

https://www.linkedin.com/soumenghosh
(650) 861-7407
• 20+ years of EDA experience in Synopsys, Cadence Design Systems

• Developed multiple core EDA products and functionalities from scratch, delivered high impact solutions,
resulting revenue growth
• Refactored and re-architected legacy code to improve performance, reduce functional issues and thus
significantly improved product quality
• Applied ML, Deep Neural Network and MLOps technologies to solve complex EDA problems
Experience
Senior Manager, ML
Synopsys Inc., Sunnyvale, CA February 2022 - Current
• Leading Machine Learning team, comprising 6 cross-geographic engineers, collaborates horizontally with
BU teams to build ML models for ML based product feature deployments for revenue growth of the
products
• Maintained frequent interactions with stakeholders on project objectives, KPIs, project status, risk
mitigation, priorities, resources etc.
• Evaluated MLOps solutions from vendors and created reports for management review and decision
• Coordinated with management and recruitment team to grow the team size from 3 to 6 to deliver
successfully on multiple, concurrent collaborations with product teams
• Delivered and deployed 4 different regression models with less than 5% MAPE and less than 3% under
prediction for PrimeSim and VCS products for ML based proprietary product features
• Applied EDA domain specific knowledge for model tuning through custom feature engineering for
deployment ML based solutions for Synopsys's EDA tools (VCS and PrimeSim).
• Improved F1-score by 2X and recall by 3.5X (with minor improvement in accuracy) by tuning architecture
and other training parameters of CNN based deep neural network model, trained on highly imbalanced,
public dataset for wafer map data, for inference on customer data. Adopted traditional data augmentation
techniques to address class imbalances
• Developed CNN model using transfer learning techniques with Inception network on wafer map data and
delivered to the product team as alternate solution to the custom model
• Delivered C++ integration of Python ML models using ONNX-RT, M2CGEN
Principal Engineer, ML
Synopsys Inc., Sunnyvale, CA May 2021 - January 2022
• Optimized and fine-tuned TensorFlow CNN models for classifying semiconductor manufacturing defects
(e.g., extra-patterns, micro-scratches, surface particles), resulting in a ~10% improvement in F1-score
• Developed the initial version of a Kubeflow and Airflow-based ML pipeline for training and inference
focused on semiconductor manufacturing defects and successfully delivered it to product team
• Mentored junior members from product team to enhance ML pipelines to use async-io in the REST API for
inference service to increase throughput
Principal Engineer, R&D

Synopsys Inc., Sunnyvale, CA November 2018 - April 2021
• Led cross-functional teams, comprising R&D, PV and AE engineers, to deliver Static Abstract Model (SAM)
based and constraint based hierarchical flow for VC Spyglass Clock Domain Crossing (CDC) and VC Low
Power
• Drove closure of SAM hierarchical flow deployment issues at customer site and achieved competitive wins
at 3 key customers resulting in revenue growth
• Delivered 3-7X performance gain through SAM based hierarchical flow against flat run
• Delivered up to 16X performance improvements through TBB based multi-threaded implementations for
block abstractions
Sr Staff, R&D
Synopsys India Pvt. Ltd, Bangalore, Karnataka December 2013 - October 2018
• Developed constant propagation engine for VC Static platform for Low Power, Clock Domain Crossing (CDC)
solutions
• Developed BDD based, propagated constant-aware functional checks for VC Low Power
• Developed constant-aware structural checks for VC Spyglass CDC
• Resolved deployment issues (performance and functional) at customer site
• Managed 2014.03 and 2014.12 VC Static releases for Low Power, CDC and Lint solutions for successful
adoption of those releases
Staff, R&D
Synopsys India Pvt. Ltd, Bangalore, Karnataka February 2008 - November 2013
• Developed key set of initial structural and functional checks for VC Low Power and resolved deployment
issues (functional and performance) at customer site
• Delivered multiple performance improvements (up to 10X) in the legacy tool for Low Power Static Analysis
• Delivered MVP for transistor level low-power checks
Senior Member of Technical Staff

Cadence India Pvt Ltd, NOIDA, Uttar Pradesh August 2004 - January 2008
• Developed power structure and layout blockage push-down feature with rectilinear block support in
Virtuoso Floorplanner
• Developed new features and resolved in coming customer issues in Virtuoso Stream (GDS II) translators on
OpenAccess Design DB
Skills
C++, Python, Object Oriented Design, Multi-threading, multi-processing, Machine Learning, Deep Neural
Network (CNN), Transfer Learning, GAN, ONNX-RT, Fast-API, Docker, Kubernetes, Microservice, Airflow,
Kubeflow, Project and Resource Planning, Agile Development, Team Development, Performance Management,
Cross-Functional Collaboration
Publications
• https://dvcon-proceedings.org/document/static-power-intent-verificationof-power-state-switching-
expressions-poster/
• https://dl.acm.org/doi/10.5555/2485288.2485414
Awards
• Customer success team award for competitive win at key customer
• Customer delight individual award for catching bias related low-power issues on live design
Education
MS in VLSI CAD, Manipal Academy of Higher Education at Karnataka, India
Bachelor of Technology in Electronics and Telecommunication Engineering, Kalyani University at West

Bengal, India

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Soumen Ghosh

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SOUMEN GHOSH

Dublin, CA 94568 [email protected]

• 20+ years of EDA experience in Synopsys, Cadence Design Systems

Principal Engineer, R&D

Senior Member of Technical Staff

Bachelor of Technology in Electronics and Telecommunication Engineering, Kalyani University at West

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