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    Praveenkumar Yethirajula

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    Praveenkumar Yethirajula

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    of 3

    PRAVEEN KUMAR YETHIRAJULA

    Staff Application Engineer @ Synopsys | M.Tech from NIT Kurukshetra | : linkedin.com/in/praveen-kumar-


    yethirajula-331369167/ | Mail: [email protected] | Ph : 9398731228

    SUMMARY
    Dedicated professional with 5+ years of Industrial experience in complete RTL to GDSII flow,
    power analysis and tool validation, complemented with the knowledge of scripting and automation. I
    have a zeal to succeed in a stimulating and challenging environment, building success of the
    company while I experience advancement opportunities.

    EXPERIENCE
    Staff Application Engineer, Synopsys, Hyderabad (2020 onwards) 3 year 10 months*
    • Good knowledge on DC, FC, RTLA, PP-RTL tool features and design flow.
    • Handling FC Regression to measure and analyze the performance of latest builds and
    communicates with R&D if there is any degradation.
    • Debugged issues, corner scenarios to achieve the target PPA metrics.
    • Supporting NVIDIA account for P&R issues at multiple stages- placement, floorplan and router.
    • Dedicatedly supporting Samsung client to improve the flow, tool usage, resolved critical issues in
    all projects across Synopsys tools for a smooth tapeout.
    • Worked on design migration to lower nodes with promising PPA results.
    • Worked on Design planning and Auto floorplan features.
    • Performed Pre-STA for validating the timing performance of the design and fixed violating paths.
    • Created scripts using TCL & Python for better result analysis and automation work.
    • Created GUI for better user debugging to quickly resolve the issues.
    • Delivered Product trainings to Samsung, HCL, Google and other clients.
    • Supported global clients to resolve the queries related tool usage and meeting targeted PPA.
    • Through global support, identified the key business areas to migrate customer to Synopsys tools,
    increase licenses usage based on the project, extending license support etc.,
    • Experience in training juniors on Synthesis tools and scripting.

    Technical Intern, PowerPro Product Validation, Siemens-Noida (2019-2020) 1year 6 months


    • Developed Supervised Machine Learning model to replace one of the existing optimization
    techniques for run-time enhancement in PowerPro tool.
    • Converted complex data into excel and graph representation on customer requirement.
    • Automated tasks for runtime enhancement.
    • Created TCL/Python scripts for Visualization of metrics from complex log files.
    • Tested tool enhancements by creating unit testcases to exactly impact the implemented feature.
    • Written RTL testcases using System Verilog and Verilog HDL.

    TECHNICAL SKILLS

    Synthesis Tools : Design Compiler, Fusion Compiler, RTL Architect


    Low Power tools : Power Compiler, PrimePower, PP-RTL, PowerPro
    Programming/Scripting : Python, TCL, Machine Learning, Data mining and
    Visualization, Shell scripting, HTML
    LEC : Formality
    Layout : Virtuoso
    Simulators : Vivado, VCS
    HDL : System Verilog, Verilog
    Others : Salesforce, JIRA, Perforce
    PROJECTS

    1. DCNXT Migration for Samsung Mobile project(5nm)


    • This project aimed at migrating the customer from DC to DCXNT to achieve better PPA at lower
    technology nodes. Ported customer design to DCNXT.
    • Gained customer trust on DCNXT with promising results and PPA improvement compared to DC.

    2. RTL Architect – FC Multi Hierarchical Synthesis Flow


    • Generated RTLA auto partition solutions with constraints like cell count, pin count, congestion
    aware for design with 6M instances.
    • Combined each solution with FC for synthesis till CTS stage.
    • Automated the RTLA-FC setup for all partition solutions.
    • Analyzed the QOR summary of each run and picked the best solution out of it.

    3. FC/DC MUSE and AMUSE activity for Samsung


    • Developed MUSE & AMUSE setup for Samsung 5nm and 4nm projects.
    • It is a structural setup to easily integrate design setup and run design by updating single setup file
    and run complete synthesis flow using make file.
    • This setup enables easy to analyze and debug in intermediate stages like mapping, optimization,
    DFT, coarse placement for best PPA.

    4. FC-FE Regression Activity for Samsung


    • Owned the regression suite and handled 12 regression cycles in a span of one year and ongoing.
    • Running complex designs with different QOR strategy for each regression cycle.
    • Collect the regression data using perl scripts runs and compare with previous regression runs.
    • Analyze the QOR trend using python scripts and report the degradations using JIRA system.
    • Send a regression summary to Samsung to enable them choose regression based on the project
    goals.

    5. Analyzed and fixed timing violations on multiple blocks


    • Analyzed the slack violating paths and debugged the reason and fixed it which include fixing max
    transition on nets, high fanout paths, high logic depth and complex low drive strength cells.

    6. Regression setup for Samsung R*E & R*D block


    • Shipped the complex design setups from customer network to in house.Tested the design setup
    iteratively to identify the missing NDMS, SDC constraints, UPF, DFT constraints etc.,
    • Worked with DFT, Formality cross teams to successfully finish the Design Compiler-Formality
    setup and Fusion Compiler setup to PV team for regression activity.

    7. Python Graph Visualization for Prime ECO Scenario coverage

    • Created python script using matplotlib, pandas and other supportive packages for analyzing the
    metrics in Prime ECO scenario runs using graphs and trend.
    • This graphical data analysis helps the Engineer to easily identify the best ECO coverage scenario
    out of multiple ECO runs.

    8. Virtual debugger for fixing the DRC shorts

    • Developed GUI using python and tkinter to debug and clean the shorts in the design.
    • This enables the user to load the run the predefined fixes on the design automatically to clean
    the shorts.
    EDUCATION

    2020 M.Tech (VLSI Design) 2014 10+2 (MPC)


    NIT Kurukshetra A.P.R.J.C-Venkatagiri
    8.95 CGPA 96.9%

    2018 B.E (ECE) 2012 SSC


    Anil Neerukonda Institute of Sri Thanus Vidyanikethan
    Technology and Sciences 9.5 CGPA
    8.61 CGPA

    CERTIFICATION COURSES

    “Joy of Computing Using Python” from IIT Ropar.


    “Hardware Modeling Using Verilog” from IIT Kharagpur.

    ACHIEVEMENTS & AWARDS

    • Reached Semifinals in the Synopsys Global Pitch Fest challenge for Innovation.
    • Won Synopsys quarterly award thrice for best performance on the projects FC-Regression &
    DCXNT migration 5nm mobile project.
    • Won Runner-Up award in customer focus & support category in Synopys Annual awards 2021.
    • Won 3rd place in Hardware Expo in National technical symposium ePROBE 2k17 held in ANITS
    Engineering College. Won Consolation prize in Model Presentation in 15th ANITS College Day
    Celebrations.
    • Stood Second in Dance Competition (Boys Solo dance) twice in ANITS College Day
    Celebrations. Stood First in Zonal level Quiz Competition held in Venkatagiri,SPSR Nellore.
    • Stood 10th position in District level Master Minds Mega talent test.

    PUBLICATION

    Yethirajula Praveen Kumar, Trailokya Nath Sasamal and Divya Parihar, “Machine Learning-Based
    Efficiency and Power Estimation of Circular Buffer”, 2020 1st International Conference on Green
    Technology for Smart City and Society (GTSCS-2020), Springer Publications, August 2020
    Machine Learning Based Efficiency and Power Estimation of Circular Buffer | SpringerLink

    PERSONAL STRENGTHS
    • Good at problem analyzing and debugging.
    • Quick learner.
    • Looks forward for challenging tasks.

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