Engrg1060 Ece Lecture
Engrg1060 Ece Lecture
Engrg1060 Ece Lecture
Telecomm Computer
Engineering
Information Theory Robotics
Network Protocols Computer-Aided
and Optimization
ECE Design
Signal Electrical
Processing Circuits
ECE is everywhere!
Data Centers
Game
Consoles
Computing: From Handhelds to Servers
Internet Routers
Digital GPS Devices
Cameras and Satellites
Humanoid Robots
Unmanned Vehicles
Electric and
Hybrid Vehicles
Automobiles
"What hath
God wrought?"
“Optional Homework”
Talk Outline
ECE Overview
Application
Technology
Programming Language
Insertion sort algorithm
Operating System
1. Find minimum number in input array
Instruction Set Architecture 2. Move minimum number into output array
Microarchitecture 3. Repeat steps 1 and 2 until finished
Register-Transfer Level
C implementation of insertion sort
Gate Level void isort( int b[], int a[], int n ) {
Circuits for ( int idx, k = 0; k < n; k++ ) {
int min = 100;
Devices for ( int i = 0; i < n; i++ ) {
Technology if ( a[i] < min ) {
min = a[i];
idx = i;
}
}
b[k] = min;
a[idx] = 100;
}
}
Programming Language
Operating System
Instruction Set Architecture
Microarchitecture
Register-Transfer Level MIPS32 Instruction Set
Gate Level Instructions that machine executes
Circuits blez $a2, done
move $a7, $zero
Devices li $t4, 99
Technology move $a4, $a1
move $v1, $zero
li $a3, 99
lw $a5, 0($a4)
addiu $a4, $a4, 4
slt $a6, $a5, $a3
movn $v0, $v1, $a6
addiu $v1, $v1, 1
movn $a3, $a5, $a6
Application
How data flows
Algorithm through system
Computer Engineering
Programming Language
Operating System
Instruction Set Architecture Boolean logic gates
Microarchitecture and functions
Register-Transfer Level
Gate Level Combining devices
Circuits to do useful work
Devices
Technology Transistors and wires
Si Si Si
Silicon process
technology Si Si Si
Application
Algorithm Traditional
Computer Engineering
Application Lab 4
Algorithm Software pushing
Computer Engineering
Application
Algorithm Application Requirements
Computer Engineering
Application
Algorithm
Compute
Computer Engineering
Talk Outline
ECE Overview
Application
Algorithm Traditional
Computer Engineering
MIPS
3
10 R2K
2
10
1
10
0
10
1G
Memory Capacity per Chip
64M
SRAM
4M
FLASH
256K
16K
1K
Network Peak Bisection Bandwidth (MB/s) Exponential Scaling for Network Bandwidth
7
10
6
10
5
10
Multi-Stage
4
Interconnection
10 Networks
(100-1000's Nodes)
10
3 Bus-Based
Interconnection
Networks
2
10 (10's Nodes)
8 12
10 10 Minicomputers
Supercomputers
7 10
10 10
Mainframes
Personal
6 8 Computers
10 10 Mainframes
Scalable
Volume in mm3
Price in Dollars
Clusters
5 Minicomputers 6 Handhelds
10 Cloud 10
Computing
4 Workstations 4
10 10
Workstations
Laptops
3 2
10 Personal 10
Computers
Handhelds Laptops
2 0
10 G. Bell. "Bell's Law for the Birth and 10 Y. Lee et al. "Modular 1mm3 Die-
Death of Computer Classes." Internet of Things Stacked Sensing Platform ..."
CACM, Jan 2008. JSSC, Jan 2013. IoT
1950 1960 1970 1980 1990 2000 2010 2020 1950 1960 1970 1980 1990 2000 2010 2020
Data Centers
Game
Consoles
Computing: From Handhelds to Servers
Internet Routers
Digital GPS Devices
Cameras and Satellites
Humanoid Robots
Unmanned Vehicles
Automobiles
Wearable
Computing
Sensor
Networks Medical
Smart Home Devices Wearable Activity Monitors
Typical
2
10 Power (W)
1
10
0
10
P P P P
N N
M M M M
P P P P
AMD Quad-Core Opteron
Four cores on the same die N
P P P P M M M M
Typical
2
10 Power (W)
Number
1
10 of Cores
0
10
?
Vertical MOSFETs
Graphene
Carbon Nanotubes
Nanorelays
Quantum Computing
Molecular Computing
Memristers
Phase-Change Mem
Spintronics
3D Integration
Nanophotonics
`10 `20 `30 `40 `50 `60 `70 `80 `90 `10
Adapted from R. Kurzweil. “The Singularity is Near.” Penguin Books, 2006.
Distribute
Network
Network
Merge Phase 1
Proc/Mem > merge 4+4 = 8
Network
Merge Phase 2
Proc/Mem > merge 8+8 = 16
Algorithm
Network Communication
Load Balancing Merge Phase 3
Proc/Mem Fault Tolerance > merge 16+16 = 32
Dataset Size
Network sorted
Talk Outline
ECE Overview
Computer Engineering
Explore design space
for a new system
Design and model
baseline system
Ask question
about system
Test with
experiment
I Design Principles
. Modularity – Decompose into components with well-defined interfaces
. Hierarchy – Recursively apply modularity principle
. Encapsulation – Hide implementation details from interfaces
. Regularity – Leverage structure at various levels of abstraction
. Extensibility – Include mechanisms/hooks to simplify future changes
I Design Patterns
. Processors, Memories, Networks
. Control/Datapath Split
. Single-Cycle, FSM, Pipelined Control
. Raw Port, Message, Method Interfaces
I Design Methodologies
. Agile Hardware Development
. Test-driven Development
. Incremental Development
Take-Away Points
I ECE is a broad field focused on the study
and application of electricity, micro-
electronics, and electro-magnetism
I Computer engineering is the process of
designing abstraction and implementation
layers to meet application requirements
within physical technology constraints
I We are entering an exciting new era of
computer engineering with emerging
applications and systems, a remarkable shift
towards mainstream parallel processing,
and significant technology challenges