Birla Institute of Technology and Science, Pilani

Work-Integrated Learning Programmes Division

Second Semester 2013-2014

Course Handout

Course Number : SS ZG516

Course Title : Computer Organization and Software Systems

Instructors : Lucy Gudino

Course Description:

Programmer model of CPU; Basic concept of buses and interrupts; Memory subsystem organization; I/O
organization; Instruction Set and its characteristics; Processor Structure and its functions, Instruction cycle,
Instruction Pipeline; Concept of assembler, linker & loader; Types of operating systems; Concept of process;
OS functions: Process scheduling, Memory Management, I/O management and related issues.

Scope and Learning Objectives of the Course:

This course introduces the students to systems aspects involved in software development. In particular, it
focuses on basic hardware architectural issues that affect the nature and performance of software as well as
those features of an operating system with which most systems software have to interact.
At the end of this course, a student must not only be aware of various aspects of architecture and operating
systems but also must be in a position to evaluate the effects of the same on high level software. In particular,
students must be able to correlate environmental and performance related issues of high-level software with
system level features of the architecture or an operating system.

Prescribed Text Book (S)

T1. Stallings William, Computer Organization & Architecture, Pearson Education, 8 th Ed., 2010
T2. A. Silberschatz, Abraham and others, Operating Systems Concepts, Wiley Student Edition, 8 th
Edition, 2008.

Reference Book (S)

R1. J. Hennessy and D. Patterson. Computer Architecture – A Quantitative Approach, Morgan Kaufman,
1990.
R2. William Stallings, Operating Systems – Internals and Design Principles. Prentice Hall of India, 2001.

Reference Books from 24x7

R3. C. Madana Kumar Reddy, Operating Systems Made Easy – Laxmi Publications, India, 2009
R4. Nirmala Sharma, Computer Architecture – Laxmi Publications, India, 2009
SS ZG516 (Course Handout) Second Semester 2013-2014 Page 2
Plan of Self-Study
S.No. Topics Learning Objectives Chapter/
Section
Reference to
Text Book(s)
1 Introduction: Computer To understand a general purpose T1. Sec. 1.1-1.2,
Components, Functions, computer’s organization and architecture 3.1-3.5
Interconnection Structures and the interconnection among those
components this facilitates the information
and control exchange.
2-3 Computer Memory System Learn the hierarchy of memory subsystems
Overview, Cache Memory with an overview of type, technology, T1. Ch. 4.1-4.4
Principles, Cache memory performance and cost factors. Cache,
Design Considerations Internal and External memory are
4 Internal Memory Characteristics discussed in sequence. T1. Sec. 5.1, 5.3,
and Design (e.g. DRAM), Read/Write performance improvement 6.1-6.2
External Memory (e.g. using multiple memory banks (i.e.
Magnetic Disk), RAID Memory Interleaving). Secondary memory
types with emphasis on Magnetic Disk and
its performance parameters.
5 Input/Output: I/O Modules, Learn various I/O Techniques, along with T1. Sec. 7.1-7.5
Programmed I/O, Interrupt the interface requirements from OS and the
driven I/O, DMA external world
6 Instruction Sets – Learn the designers and programmers view T1. Sec. 10.1-
Characteristics and Functions: of the computer system with the help of 10.5, 11.1-11.4
Types of operands, Data Types, machines instruction set and to discuss
Type of Operations, characteristics of instruction sets. Types of
Instruction Sets – Addressing possible operations, addressing modes are
modes and Formats: discussed here. x86 Operation Types and
Addressing, Addressing modes, Addressing modes will serve as an
Instruction formats example.
Intel x86 will be an example
7 Processor Structure and Learn the processor organization in detail T1. Sec.12.1-
Function: Processor and with detail register organization, 12.4
Register Organization, instruction cycle. Learn the common
Instruction Cycle, Instruction technique used in the speed up of
pipelining instruction execution known as
Pipelining’ along with the associated
issues w.r.t. implementation
Micro operations and Micro To understand the sequence of sub-steps T1.Sec. 15.1-
8 Instructions, Control Unit (known as cycles) that the computer go 15.3,16.1-16.3
Design: Micro-programmed through in executing an instruction and to
Control, Hardwired Control get into details of implementing them
using hardwired and micro programmed
approaches.
9 Review Session
Syllabus for Mid-Semester Test (Closed Book): Topics covered in S. No. 1 to 9
10 Structure of an Operating To understand the basic structure of a system, T2. Ch. 1 and 2
System need of operating system for a computing
machine and the structure of an OS.
11 Processes & Threads To understand the notion of a process and to T2. Ch. 3 and 4
understand the view of the system as if
consisting of OS processes. Also benefits of
having Multithreaded process and various
multi threading models.
SS ZG516 (Course Handout) Second Semester 2013-2014 Page 3

Plan of Self-Study

S.No. Topics Learning Objectives Chapter/

Section
Reference to
Text Book(s)
12 Process Scheduling Basic concepts in CPU scheduling, and algorithms T2. Ch. 5
are discussed
13 Process To learn various mechanisms to ensure the orderly T2. Ch. 6
Synchronization execution of cooperating processes that share logical
address space. Critical section problem and various
software and hardware solutions to it are discussed
here.
14-15 Deadlocks Various methods to deal with deadlock viz deadlock T2. Ch. 7
prevention, deadlock avoidance & deadlock
detection are discussed.
16 Memory Management To understand various ways of managing the T2. Ch. 8 and
& Virtual Memory memory along with the hardware support and to 9
understand virtual memory systems which allows the
execution of a process which is completely not in the
memory.
17 Mass Storage To understand the physical structure of mass storage, T2. Ch.12
disk scheduling mechanisms and it’s management.
18 Review Session
Syllabus for Comprehensive Exam (Open Book): All topics given in the Plan of Self Study

Evaluation Scheme:

EC Evaluation Duration Weigh- Day, Date, Session,Time

No. Component & tage
Type of Examination
EC-1 Assignment/Quiz ** Details to be announced 15% ** Details to be announced on
on LMS Taxila website by LMS Taxila website by
Instructor Instructor
EC-2 Mid-Semester Test 2 Hours 35% Saturday, 15/02/2014 (FN)*
(Closed Book)* 10 AM – 12 Noon
EC-3 Comprehensive Exam 3 Hours 50% Saturday, 05/04/2014 (FN)*
(Open Book)* 9 AM – 12 Noon
SS ZG516 (Course Handout) Second Semester 2013-2014 Page 4

** Please check the details by January 10, 2014 on LMS Taxila web site.

AN: AfterNoon Session; FN: ForeNoon Session

Closed Book Test: No reference material of any kind will be permitted inside the exam hall.
Open Book Exam: Use of any printed / written reference material (books and notebooks) will be permitted
inside the exam hall. Loose sheets of paper will not be permitted. Computers of any kind will not be allowed
inside the exam hall. Use of calculators will be allowed in all exams. No exchange of any material will be
allowed.

Note:
It shall be the responsibility of the individual student to be regular in maintaining the self study
schedule as given in the course handout, attend the online/on demand lectures as per details that
would be put up in the BITS LMS Taxila website www.taxila.bits-pilani.ac.in and take all the
prescribed components of the evaluation such as Assignment (Course Page on LMS Taxila), Mid
Semester Test and Comprehensive Examination according to the Evaluation Scheme given in the
respective Course Handout. If the student is unable to appear for the Regular Test/Examination due
to genuine exigencies, the student must refer to the procedure for applying for Make-up
Test/Examination, which will be available through the Important Information link on the BITS
LMS Taxila website www.taxila.bits-pilani.ac.in on the date of the Regular Test/Examination.
The Make-up Tests/Exams will be conducted only at selected exam centres on the dates to be
announced later.

Instructor-in-Charge