Tessent Command Study Notes 3

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Tessent Command Study Notes 3
1. set_test_point_analysis_options: sets the maximum number of test points , the faults of

control and observation points, the target fault coverage and the number of pseudo-
random patterns to be applied, as well as some other parameters considered during test
point analysis.
2. set_test_point_type: the type of test point to be inserted into the design;

edt_pattern_count, specifies that the test points to be inserted are to reduce the number
of deterministic patterns.
3. write_test_point_dofile: writes out a dofile containing a test point.
4. report_drc_rules: Reports overall DRC violations, or information about violations that

occurred.
5. register_attribute: Register a new user-defined attribute.
6. add_notest_points: Prevents test logic from being inserted into the specified area.
7. set_simulation_options: Controls the behavior of the tool when generating patterns and
simulating.
8. add_core_instances: Add a core instance to the design by associating the core

description in the current mem with the specified core instances.
9. add_nofaults: Set no faults on the pin pathnames and pin names of the specified
instance or modules; for some instances that do not need to be tested, or other tests
can cover this instance.
10. set_static_dft_signal_values: Set the static DFT signal in the design. Such a signal can
be used as test_setup.
11. set_simulation_options: controls the behavior of the tool during pattern generation and
simulation; -C6_mask_taces, turns on pessimistic simulation and masked capture
values of the state elements of C6 violations only when the data port transition and the
clock port are captured in the same frame. When simulation should be performed, it is
believed that the violation will bring more serious consequences; -set_reset, when
multiple ports of the storage unit are opened at the same time, if this option is set to on,
the clock value is determined by set or reset. If it is set to off, the estimated value
depends on all enabled ports. If the enabled ports point to the same value, the state
element ( ? ) is set to the value, otherwise it is indeterminate; -mux_select, specifies
whether the initial value of model_mux (copy mux, insert many muxes, and copy the
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same mux) in the design is consistent. By default, the tool will models_mux as the same
(mux has a selection terminal, which should be the value selected to make the selection
terminal consistent at the beginning).
12. set_xclock_handiling: Specifies that when any clock input of the sequential cell changes
to X (indeterminate state), the output is X; by default, when the clock value changes to X,
as long as other input values do not cause the stored output value to change, regardless
of whether the clock is 0 or 1; set_xclock_handling x -pessimistic_simulation on, the
output of the edge-triggered sequential cell is set to X unless the clock input changes
from x to 0.
13. report_dft_signals: reports all DFT signals added and created.
14. set_parallel_load_subchains: specifies whether to use the parallel access function

(which can save the size of runtime and parallel test bench file); when enabled, when the
netlist contains subchain, data can be loaded in parallel shift; when the pin name in
Verilogku cannot match the cell library in Tessent, parallel loading cannot be used.
15. T24: In the scan path, for two asynchronously clocked memory cells, the sink cannot
capture data from the source when the source changes the data. Failure to meet this
rule may result in unnecessary shoot-through during the scan chain shift process when
there is clock skew between different shift clocks, which can lead to mismatches or
potentially bad chips.
16. D5: All mem elements (units that can store data should be mem elements, such as
latches and flip-flops) must be scannable. Check whether there are unscannable mem
elements. Unscannable mem elements are considered violations.
17. add_nofalut: prevent nofault setting in the pin pathname or pin names of the specified
module or instance; -module, the module name parameter is translated into the
pathname of the module.
18. report_input_constraints: Displays the current constraint status of PI pins.
19. set_fault_sampling: Specifies the sampling percentage of faults for circuit evaluation
and scan identification; fault sampling can use a portion of the total faults, thereby
reducing the processing time for evaluating large circuits.
20. add_processors: Enables the tool to run multiple processors in parallel on multiple
machines to reduce running time.
21. analyze_wrapper_cells: Identify shared and dedicated wrapper cells for Primary I/O
ports.
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 This command uses the identification of shared wrapper cells for the primary I/O ports
that can be controlled by set_wrapper_analysis_options. User-specified clocks and scan
-related I/O ports are automatically excluded from identification. Identified wrapper cells
are stitched to the wrapper chains for the primary I/O ports. If
set_wrapper_analysis_options is not executed, analyze_wrapper_cells performs the
default wrapper cell identification similar to the execution of
set_wrapper_analysis_option without parameters.
 When the analyze_wrapper_cells command is used in conjunction with the

set_dedicated_wrapper_cell_options command, the wrapper analysis will result in the
registration of the primary I/O ports or the primary I/O being marked as wrapper cells to
ensure the best circuit coverage . This means that during scan insertion, new scan cells
are added to all designated Primary I/O ports, depending on certain design
considerations. The dedicated wrapper cells added to the primary I/O are stitched into
the wrapper chain (the tool analyzes which ports can directly use shared wrapper cells,
and if shared wrapper cells cannot be used, new scan cells will be inserted as dedicated
wrapper cells).
 When using the set_wrapper_analysis_options command, regardless of whether the

set_dedicated_wrapper_cell_options command is used, the identification includes the
identification of the combined existing timing elements (shared wrapper cells) that can
be accessed from the PI or PO through the combinational logic. Therefore, the shared
wrapper cell provides functional mode and control and observe functions during testing.
The advantage of shared wrapper cells is that less logic is added, and the external test
mode can test the timing of the actual path (functional path, dedicated wrapper cell is to
control PI and observe PO).
 analyze_wrapper_cells may invalidate data from other analysis phases. Use this
command before doing scan chain analysis. If scan chain analysis has already been
completed when entering the analyze_wrapper_cells command, it will result in an error.
You can use the -force switch to overwrite it. In this case, the results of the scan chain
analysis will be reset and the scan chain analysis must be repeated to recreate the
desired scan patterns and scan chain families.
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Tessent Command Study Notes 3

1. set_test_point_analysis_options: sets the maximum number of test points , the faults of

2. set_test_point_type: the type of test point to be inserted into the design;

3. write_test_point_dofile: writes out a dofile containing a test point.

4. report_drc_rules: Reports overall DRC violations, or information about violations that

5. register_attribute: Register a new user-defined attribute.

8. add_core_instances: Add a core instance to the design by associating the core

13. report_dft_signals: reports all DFT signals added and created.

14. set_parallel_load_subchains: specifies whether to use the parallel access function

18. report_input_constraints: Displays the current constraint status of PI pins.

 When the analyze_wrapper_cells command is used in conjunction with the

 When using the set_wrapper_analysis_options command, regardless of whether the

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