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TPS2069D
SLVSDQ5 – DECEMBER 2016

TPS2069D Current Limited, Power-Distribution Switches

1 Features 3 Description
•
1 Single Power Switch Family The TPS2069D power-distribution switch family is
intended for applications such as USB where heavy
• Rated currents of 1.5 A capacitive loads and short circuits are likely to be
• ±20% Accurate, Fixed, Constant Current Limit encountered. The device can continuously deliver up
• Fast Overcurrent Response: 2 µs to 1.5 A output current.
• Deglitched Fault Reporting The TPS2069D limits the output current to a safe
• Output Discharge level by operating in a constant-current mode when
the output load exceeds the current limit threshold.
• Reverse Current Blocking
This provides a predictable fault current under all
• Built-in Soft Start conditions. The fast overload response time eases
• Ambient Temperature Range: –40°C to 85°C the burden on the main 5-V supply to provide
• UL Listed and CB-File No. E169910 regulated power when the output is shorted. The
power-switch rise and fall times are controlled to
minimize current surges during turnon and turnoff.
2 Applications
• USB Ports/Hubs, Laptops, Desktops Device Information(1)
• High-Definition Digital TVs PART NUMBER PACKAGE BODY SIZE (NOM)
• Set Top Boxes TPS2069D SOT-23 (5) 2.90 mm × 1.60 mm

• Short Circuit Protection (1) For all available packages, see the orderable addendum at
the end of the data sheet.

Spacer
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Typical Application Diagram

VIN IN OUT VOUT

0.1 mF

RFLT
10 kW 150 mF

Fault Signal FLT GND

Control Signal EN

Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 11
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 13
3 Description ............................................................. 1 9 Application and Implementation ........................ 14
4 Revision History..................................................... 2 9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
5 Device Comparison Table..................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 17
7 Specifications......................................................... 4 11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 17
7.2 ESD Ratings.............................................................. 4
11.3 Power Dissipation and Junction Temperature ...... 17
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information .................................................. 4 12 Device and Documentation Support ................. 19
7.5 Electrical Characteristics: TJ = TA = 25°C................. 5 12.1 Receiving Notification of Documentation Updates 19
7.6 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C......... 6 12.2 Community Resources.......................................... 19
7.7 Timing Requirements: –40°C ≤ TJ ≤ 125°C .............. 6 12.3 Trademarks ........................................................... 19
7.8 Typical Characteristics .............................................. 8 12.4 Electrostatic Discharge Caution ............................ 19
12.5 Glossary ................................................................ 19
8 Detailed Description ............................................ 11
8.1 Overview ................................................................. 11 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagrams ..................................... 11
Information ........................................................... 19

4 Revision History
DATE REVISION NOTES
December 2016 * Initial release.

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5 Device Comparison Table

MAXIMUM OPERATING
OUTPUT DISCHARGE ENABLE
CURRENT
1.5 A Y High

6 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View

OUT 1 5 IN
GND 2
FLT 3 4 EN

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
EN 4 I Enable input, logic high turns on power switch
GND 2 — Ground connection
Input voltage and power-switch drain; connect a 0.1-µF or greater ceramic capacitor from IN to GND
IN 5 PWR
close to the IC
FLT 3 O Active-low open-drain output, asserted during overcurrent, or overtemperature conditions
OUT 1 PWR Power-switch output, connect to load.

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
(4)
Voltage range on IN, OUT, EN, FLT –0.3 6 V
Voltage range from IN to OUT –6 6 V
Maximum junction temperature, TJ Internally Limited
Storage temperature, Tstg –60 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Absolute maximum ratings apply over recommended junction temperature range.
(3) Voltages are with respect to GND unless otherwise noted.
(4) See Input and Output Capacitance .

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
V(ESD) Electrostatic discharge (3)
V
IEC 61000-4-2 contact discharge ±8000
IEC 61000-4-2 air-gap discharge ±15000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) VOUT was surged on a pcb with input and output bypassing per Input and Output Capacitance (except input capacitor was 22 µF) with
no device failures.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Input voltage, IN 4.5 5.5 V
VEN Input voltage, EN 0 5.5 V
VIH High-level input voltage, EN 2 V
VIL Low-level input voltage, EN 0.7 V
IOUT Continuous output current, OUT (1) 1.5 A A
TJ Operating junction temperature –40 125 °C
IFLT Sink current into FLT 0 5 mA

(1) Some package and current rating may request an ambient temperature derating of 85°C.

7.4 Thermal Information

TPS2069D
THERMAL METRIC (1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 220.4 °C/W
RθJCtop Junction-to-case (top) thermal resistance 89.7 °C/W
RθJB Junction-to-board thermal resistance 46.9 °C/W
ψJT Junction-to-top characterization parameter 5.2 °C/W
ψJB Junction-to-board characterization parameter 46.2 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A °C/W
RθJACustom See Power DIssipation and Junction Temperature 134.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics: TJ = TA = 25°C (1)

Unless otherwise noted: VIN = 5 V, VEN = VIN, IOUT = 0 A. See Device Comparison Table for the rated current of each part
number. Parametrics over a wider operational range are shown in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
POWER SWITCH
1.5-A rated output, 25°C DBV 76 91 mΩ
RDS(on) Input – output resistance 1.5-A rated output,
DBV 76 106 mΩ
–40°C ≤ (TJ , TA) ≤ 85°C
CURRENT LIMIT
IOS (2) Current limit, See Figure 6 1.5-A rated output 1.7 2.15 2.5 A
SUPPLY CURRENT
IOUT = 0 A 0.01 1
ISD Supply current, switch disabled µA
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 2
IOUT = 0 A 60 70
ISE Supply current, switch enabled µA
–40°C ≤ (TJ , TA) ≤ 85°C, VIN = 5.5 V, IOUT = 0 A 85
VOUT = 5 V, VIN = 0 V, measure IVOUT 0.1 1
IREV Reverse leakage current –40°C ≤ (TJ , TA) ≤ 85°C, VOUT = 5 V, VIN = 0 V, measure µA
5
IVOUT
OUTPUT DISCHARGE
RPD Output pulldown resistance (3) VIN = VOUT = 5 V, disabled 400 470 600 Ω

(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) See Current Limit section for explanation of this parameter.
(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.

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7.6 Electrical Characteristics: –40°C ≤ TJ ≤ 125°C

Unless otherwise noted:4.5 V ≤ VIN ≤ 5.5 V, VEN = VIN, IOUT = 0 A, typical values are at 5 V and 25°C. See Device Comparison
Table for the rated current of each part number.
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
POWER SWITCH
RDS(ON) Input – output resistance 1.5-A rated output DBV 76 121 mΩ
ENABLE INPUT (EN)
Threshold Input rising 1 1.45 2 V
Hysteresis 0.07 0.13 0.20 V
Leakage current (VEN) = 0 V –1 0 1 µA
CURRENT LIMIT
IOS (2) Current limit, See Figure 22 1.5-A rated output 1.6 2.15 2.7 A
VIN = 5 V (see Figure 6),
One-half full load → RSHORT = 50 mΩ,
tIOS Short circuit response time (3) 2 µs
Measure from application to when current falls below 120% of
final value
SUPPLY CURRENT
ISD Supply current, switch disabled IOUT = 0 A 0.01 10 µA
ISE Supply current, switch enabled IOUT = 0 A 65 90 µA
IREV Reverse leakage current VOUT = 5.5 V, VIN = 0 V, measure IVOUT 0.2 20 µA
UNDERVOLTAGE LOCKOUT
VUVLO Rising threshold VIN↑ 3.5 3.75 4 V
Hysteresis (3) VIN↓ 0.14 V
FLT
Output low voltage, FLT IFLT = 1 mA 0.2 V
Off-state leakage VFLT = 5.5 V 1 µA
tFLT FLT deglitch FLT assertion or deassertion deglitch 6 9 12 ms
OUTPUT DISCHARGE
VIN = 4 V, VOUT = 5 V, disabled 350 560 1200
RPD Output pulldown resistance Ω
VIN = 5 V, VOUT = 5 V, disabled 300 470 800
THERMAL SHUTDOWN
In current limit 135
Rising threshold (TJ)
Not in current limit 155 °C
(3)
Hysteresis 20

(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
(2) See Current Limit for explanation of this parameter.
(3) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purposes of TI's
product warranty.

7.7 Timing Requirements: –40°C ≤ TJ ≤ 125°C

MIN NOM MAX UNIT
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↑ or EN ↓.
tON Turnon time See Figure 1, Figure 3, and Figure 4 1.2 1.7 2.2 ms
1.5 A Rated
VIN = 5 V, CL = 1 µF, RL = 100 Ω, EN ↓ or EN ↑.
tOFF Turnoff time See Figure 1, Figure 3, and Figure 4 1.7 2.1 2.5 ms
1.5 A Rated
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2
tR Rise time, output 0.5 0.7 1 ms
1.5 A Rated
CL = 1 µF, RL = 100 Ω, VIN = 5 V. See Figure 2
tF Fall time, output 0.3 0.43 0.55 ms
1.5 A Rated

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OUT

RL CL

Figure 1. Output Rise and Fall Test Load

90%
tR tF
VOUT
10%

Figure 2. Power-On and Power-Off Timing

VEN 50% 50%

tON
tOFF
90%
VOUT
10%

Figure 3. Enable Timing, Active High Enable

V/EN
50% 50%
tOFF

tON 90%
VOUT
10%

Figure 4. Enable Timing, Active Low Enable

IOUT 120% x IOS

IOS
0A
tIOS

Figure 5. Output Short Circuit Parameters

VIN Decreasing
Load
Slope = -RDS(ON) Resistance
VOUT

0V
0A IOUT
IOS
Figure 6. Output Characteristic Showing Current Limit

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7.8 Typical Characteristics

9.3 14
85°C
12
9.2
25°C
10

IOUT sinking (mA)

9.1
tFLT (ms)

8 −40°C

6
9.0

4 125°C
8.9
2

8.8 0
−40 −20 0 20 40 60 80 100 120 140 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Junction Temperature (°C) G019
Output Voltage (V) G020

All Versions, 5 V VIN = 5 V

Figure 7. Deglitch Period (TFLT) vs Temperature Figure 8. Output Discharge Current vs Output Voltage
3.5 7

6
3.0
5
2.5 1.5-A Rated
4
IREV (µA)
IOS (A)

2.0 3
1-A Rated
2
1.5
0.5-A Rated 1
1.0
0

0.5 −1
−40 −20 0 20 40 60 80 100 120 140 −40 −20 0 20 40 60 80 100 120 140
Junction Temperature (°C) G021
Junction Temperature (°C) G022

VIN = 5 V All Unit Types, 5 V

Figure 9. Short Circuit Current (IOS) vs Temperature Figure 10. Reverse Leakage Current (IREV) vs Temperature
1.0 1.0

0.8 0.8

0.6 0.6
125°C
ISD (µA)

ISD (µA)

0.4 0.4

85°C
0.2 0.2

0.0 0.0

−40°C and 25°C

−0.2 −0.2
−40 −20 0 20 40 60 80 100 120 140 4.00 4.25 4.50 4.75 5.00 5.25 5.50
Junction Temperature (°C) G023
Input Voltage (V) G024

Input Voltage = 5.5 V All Unit Types

Figure 11. Disabled Supply Current (ISD) vs Temperature Figure 12. Disabled Supply Current (ISD) vs Input Voltage

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Typical Characteristics (continued)

6.0 80
5.5
5.0 75
4.5 125°C
4.0
70
3.5
IREV (µA)

ISE (µA)
3.0
65
2.5
2.0
1.5 85°C 60
25°C −40°C
1.0
0.5 55
0.0
−0.5 50
4.00 4.25 4.50 4.75 5.00 5.25 5.50 −40 −20 0 20 40 60 80 100 120 140
Output Voltage (V) G025
Junction Temperature (°C) G026

All Unit Types VIN = 0 V All Unit Types VIN = 5.5 V

Figure 13. Reverse Leakage Current (IREV) vs Output Voltage Figure 14. Enabled Supply Current (ISE) vs Temperature
80 0.475

75
125°C 0.450
85°C
70
0.425
65
ISE (µA)

tf (ms)

60 0.400
1.5-A and 2-A Rated, V IN = 4.5 V
55 1.5-A and 2-A Rated, V IN = 5 V
0.375
50 1.5-A and 2-A Rated, V IN = 5.5 V
25°C 0.350
45 −40°C
0.5-A and 1-A Rated, V IN = 5 V
40 0.325
4.00 4.25 4.50 4.75 5.00 5.25 5.50 −40 −20 0 20 40 60 80 100 120 140
Input Voltage (V) G027 Junction Temperature (°C) G028

COUT = 1 µF RLOAD = 100 Ω

Figure 15. Enabled Supply Current (ISE) vs Input Voltage Figure 16. Output Fall Time (TF) vs Temperature
0.85 140

1.5 A, 2 A, 5.5 V 130

0.80
120 0.5-A, 1-A Rated
0.75 110
RDSON (mW)

0.70 100
tr (ms)

90
0.65
80
0.5 A, 1 A, 5 V 1.5 A, 2 A, 5 V 70
0.60
1.5-A, 2-A Rated
1.5 A, 2 A, 4.5 V 60
0.55
50
0.50 40
−40 −20 0 20 40 60 80 100 120 140 −40 −20 0 20 40 60 80 100 120 140
Junction Temperature (°C) G029
Junction Temperature (°C) G030

COUT = 1 µF RLOAD = 100 Ω VIN = 5 V

Figure 17. Output Rise Time (TR) vs Temperature Figure 18. Input-Output Resistance (RDS(ON)) vs Temperature

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Typical Characteristics (continued)

100

Recovery Time (µs)

IOS
10

1
0 5 10 15 20 25
IPK (Shorted) (A) G031

VIN = 5 V CIN = 730 µF IEND = 1.68 A

Figure 19. Recovery vs Current Peak

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8 Detailed Description

8.1 Overview
The TPS2069D are current limited, power-distribution switches providing 1.5 A of continuous load current in 5-V
circuits. These parts use N-channel MOSFETs for low resistance, maintaining voltage regulation to the load.
They are designed for applications where short circuits or heavy capacitive loads are encountered. Device
features include enable, reverse blocking when disabled, output discharge pulldown, overcurrent protection,
overtemperature protection, and deglitched fault reporting.

8.2 Functional Block Diagrams

Current
Sense
IN CS OUT

Charge Current
Pump Limit (Disabled+
UVLO)

EN Driver
FLT
UVLO
OTSD 9-ms
GND Deglitch
Thermal
Sense

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Figure 20. Block Diagram

8.3 Feature Description

8.3.1 Undervoltage Lockout

The undervoltage lockout (UVLO) circuit disables the power switch until the input voltage reaches the UVLO
turnon threshold. Built-in hysteresis prevents unwanted ON/OFF cycling due to input voltage drop from large
current surges. FLT is high impedance when the TPS2069D is in UVLO.

8.3.2 Enable
The logic enable input (EN), controls the power switch, bias for the charge pump, driver, and other circuits. The
supply current is reduced to less than 1 µA when the TPS2069D is disabled. Disabling the TPS2069D
immediately clears an active FLT indication. The enable input is compatible with both TTL and CMOS logic
levels.
The turnon and turnoff times (tON, tOFF) are composed of a delay and a rise or fall time (tR, tF). The delay times
are internally controlled. The rise time is controlled by the device and the external loading (especially
capacitance). TPS2069D fall time is controlled by the loading (R and C), and the output discharge (RPD). An
output load consisting of only a resistor will experience a fall time set by the device. An output load with parallel
R and C elements experiences a fall time determined by the (R × C) time constant if it is longer than the device
tF.
The enable should not be left open, and may be tied to VIN or GND depending on the device.

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Feature Description (continued)

8.3.3 Internal Charge Pump
The device incorporates an internal charge pump and gate drive circuitry necessary to drive the N-channel
MOSFET. The charge pump supplies power to the gate driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The driver incorporates circuitry that controls the rise and fall times of
the output voltage to limit large current and voltage surges on the input supply, and provides built-in soft-start
functionality. The MOSFET power switch will block current from OUT to IN when turned off by the UVLO or
disabled.

8.3.4 Current Limit

The TPS2069D responds to overloads by limiting output current to the static IOS levels shown in Electrical
Characteristics: TJ = TA = 25°C (1). When an overload condition is present, the device maintains a constant output
current, with the output voltage determined by (IOS × RLOAD). Two possible overload conditions can occur.
The first overload condition occurs when either: 1) input voltage is first applied, enable is true, and a short circuit
is present (load which draws IOUT > IOS), or 2) input voltage is present and the device is enabled into a short
circuit. The output voltage is held near zero potential with respect to ground and the TPS2069D ramps the output
current to IOS. The device limits the current to IOS until the overload condition is removed or the device begins to
thermal cycle.
The second condition is when an overload occurs while the device is enabled and fully turned on. The device
responds to the overload condition within tIOS (Figure 5 and Figure 6) when the specified overload (see Electrical
Characteristics: –40°C ≤ TJ ≤ 125°C) is applied. The response speed and shape varies with the overload level,
input circuit, and rate of application. The current limit response will vary between simply settling to IOS, or turnoff
and controlled return to IOS. Similar to the previous case, the device limits the current to IOS until the overload
condition is removed or the device begins to thermal cycle.
The TPS2069D thermal cycles if an overload condition is present long enough to activate thermal limiting in any
of the above cases. This is due to the relatively large power dissipation [(VIN – VOUT) x IOS] driving the junction
temperature up. The device turns off when the junction temperature exceeds 135°C (minimum) while in current
limit. The device remains off until the junction temperature cools 20°C and then restarts.
There are two kinds of current limit profiles typically available in TI switch products similar to the TPS2069D.
Many older designs have an output I vs V characteristic similar to the plot labeled Current Limit with Peaking in
Figure 21. This type of limiting can be characterized by two parameters, the current limit corner (IOC), and the
short circuit current (IOS). IOC is often specified as a maximum value. The TPS2069D does not present noticeable
peaking in the current limit, corresponding to the characteristic labeled Flat Current Limit in Figure 21. This is
why the IOC parameter is not present in Electrical Characteristics: –40°C ≤ TJ ≤ 125°C.
Current Limit Flat Current
with Peaking Limit

VIN Decreasing
VIN Decreasing
Load Load
Slope = -RDS(ON) Resistance Slope = -RDS(ON) Resistance
VOUT

VO UT

0V 0V
0A IOUT IOS IOC
0A IOUT
I OS
Figure 21. Current Limit Profiles

(1) Pulsed testing techniques maintain junction temperature approximately equal to ambient temperature
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Feature Description (continued)

8.3.5 FLT
The FLT open-drain output is asserted (active low) during an overload or overtemperature condition. A 9-ms
deglitch on both the rising and falling edges avoids false reporting at start-up and during transients. A current
limit condition shorter than the deglitch period clears the internal timer upon termination. The deglitch timer will
not integrate multiple short overloads and declare a fault. This is also true for exiting from a faulted state. An
input voltage with excessive ripple and large output capacitance may interfere with operation of FLT around IOS
as the ripple drives the device in and out of current limit.
If the TPS2069D is in current limit and the overtemperature circuit goes active, FLT goes true immediately;
however, the exiting this condition is deglitched. FLT is tripped just as the knee of the constant-current limiting is
entered. Disabling the device clears an active FLT as soon as the switch turns off. FLT is high impedance when
the device is disabled or in undervoltage lockout (UVLO).

8.3.6 Output Discharge

A 470-Ω (typical) output discharge dissipates stored charge and leakage current on OUT when the TPS2069D is
in UVLO or disabled. The pulldown circuit loses bias gradually as VIN decreases, causing a rise in the discharge
resistance as VIN falls towards 0 V. The output is be controlled by an external loadings when the device is in
ULVO or disabled.

8.4 Device Functional Modes

There are no other functional modes.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The TPS2069D current limited power switch uses N-channel MOSFETs in applications requiring continuous load
current. The device enters constant-current mode when the load exceeds the current limit threshold.

9.2 Typical Application

4.5 V~5.5 V 0.1 F VOUT

5 IN OUT 1

RFAULT COUT
Fault
Signal
3 FAULT

Control
4 EN
Signal
GND
2

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Figure 22. Typical Application Schematic

9.2.1 Design Requirements

For this design example, use the following input parameters:
1. The TPS2069D operates from a 5 V±0.5V rail.
2. What is the normal operation current, for example, the maximum allowable current drawn by portable
equipment for USB 3.0 port is 900 mA, so the normal operation current is 900 mA, and the minimum current
limit of power switch must exceed 900 mA to avoid false trigger during normal operation. For the TPS2069D
device, target 1.5 A continuous output current application.
3. What is the maximum allowable current provided by up-stream power, the maximum current limit of power
switch that must lower it to ensure power switch can protect the up-stream power when overload is
encountered at the output of power switch. For the TPS2069D device, the maximum IOS is 2.5 A.

9.2.2 Detailed Design Procedure

To begin the design process a few parameters must be decided upon. The designer needs to know the following:
1. Normal input operation voltage
2. Output continuous current
3. Maximum up-stream power supply output current

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Typical Application (continued)

9.2.2.1 Input and Output Capacitance
Input and output capacitance improves the performance of the device; the actual capacitance should be
optimized for the particular application. For all applications, TI recommends placing a 0.1-µF or greater ceramic
bypass capacitor between IN and GND, as close to the device as possible for local noise decoupling.
All protection circuits such as the TPS2069D has the potential for input voltage overshoots and output voltage
undershoots.
Input voltage overshoots can be caused by either of two effects. The first cause is an abrupt application of input
voltage in conjunction with input power bus inductance and input capacitance when the IN terminal is high
impedance (before turnon). Theoretically, the peak voltage is 2× the applied. The second cause is due to the
abrupt reduction of output short circuit current when the device turns off and energy stored in the input
inductance drives the input voltage high. Input voltage droops may also occur with large load steps and as the
device output is shorted. Applications with large input inductance (for example, connecting the evaluation board
to the bench power-supply through long cables) may require large input capacitance reduce the voltage
overshoot from exceeding the absolute maximum voltage of the device. The fast current limit speed of the device
to hard output short circuits isolates the input bus from faults. However, ceramic input capacitance in the range of
1 µF to 22 µF adjacent to the device input aids in both speeding the response time and limiting the transient
seen on the input power bus. Momentary input transients to 6.5 V are permitted.
Output voltage undershoot is caused by the inductance of the output power bus just after a short has occurred
and the TPS2069D has abruptly reduced OUT current. Energy stored in the inductance drives the OUT voltage
down and potentially negative as it discharges. Applications with large output inductance (such as from a cable)
benefit from use of a high-value output capacitor to control the voltage undershoot. When implementing USB
standard applications, a 120 µF minimum output capacitance is required. Typically a 150-µF electrolytic capacitor
is used, which is sufficient to control voltage undershoots. However, if the application does not require 120 µF of
capacitance, and there is potential to drive the output negative, then TI recommends a minimum of 10-µF
ceramic capacitance on the output. The voltage undershoot should be controlled to less than 1.5 V for 10 µs.

9.2.3 Application Curves

12 2.5 10 3.0

10 2.0 8 2.5
EN Output
8 1.5 6 Current 2.0
Amplitude (V)
Amplitude (V)

Current (A)
Current (A)

EN
6 Output Current 1.0 4 1.5

4 0.5 2 1.0
FLT
2 0.0 0 0.5
FLT
Output Voltage
0 −0.5 −2 0.0
Output Voltage
−2 −1.0 −4 −0.5
−4m −2m 0 2m 4m 6m 8m 10m 12m 14m 16m −2m 0 2m 4m 6m 8m 10m 12m 14m 16m 18m
Time (s) G001
Time (s) G002

VIN = 5 V COUT = 150 µF RLOAD = 3.3 Ω VIN = 5 V COUT = 150 µF RLOAD = 50 mΩ

Figure 23. Turnon into 3.3 Ω Figure 24. Enable into Short

Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 15

TPS2069D
SLVSDQ5 – DECEMBER 2016 www.ti.com

Typical Application (continued)

10 3.0

8 2.5
EN
6 2.0

Amplitude (V)

Current (A)
4 1.5

2 1.0
Output Current
0 0.5

−2 0.0
Output Voltage FLT
−4 −0.5
−12.5m −7.5m −2.5m 2.5m 7.5m 12.5m
Time (s) G003

VIN = 5 V COUT = 150 µF RLOAD = 50 mΩ

Figure 25. Pulsed Output Short

16 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

 TPS2069D
www.ti.com SLVSDQ5 – DECEMBER 2016

10 Power Supply Recommendations

Design of the devices is for operation from an input voltage supply range of 4.5 V to 5.5 V. The current capability
of the power supply should exceed the maximum current limit of the power switch.

11 Layout

11.1 Layout Guidelines

1. Place the 100-nF bypass capacitor near the IN and GND pins, and make the connections using a low
inductance trace.
2. Place at least 10-µF low ESR ceramic capacitor near the OUT and GND pins, and make the connections
using a low inductance trace.
3. The PowerPAD™ should be directly connected to PCB ground plane using wide and short copper trace.

11.2 Layout Example

GND: 0.052in2 Total
& 3 x 0.018in vias COUT

0.050in trace
CIN

4 x 0.01in vias

VIN : 0.00925in2 VOUT: 0.041in2 total

& 3 x 0.018in vias
Figure 26. DBV Package PCB Layout Example

11.3 Power Dissipation and Junction Temperature

It is good design practice to estimate power dissipation and maximum expected junction temperature of the
TPS2069D. The system designer can control choices of package, proximity to other power dissipating devices,
and printed-circuit-board (PCB) design based on these calculations. These have a direct influence on maximum
junction temperature. Other factors, such as airflow and maximum ambient temperature, are often determined by
system considerations. It is important to remember that these calculations do not include the effects of adjacent
heat sources, and enhanced or restricted air flow.
Addition of extra PCB copper area around these devices is recommended to reduce the thermal impedance and
maintain the junction temperature as low as practical. The lower junction temperatures achieved by soldering the
pad improve the efficiency and reliability of both device parts and the system. The following examples were used
to determine the θJACustom thermal impedances noted in Thermal Information. They were based on use of the
JEDEC high-k circuit board construction (2 signal and 2 plane) with 4, 1-oz. copper weight, layers.

As shown in Equation 1, the following procedure requires iteration because power loss is due to the internal
MOSFET I2 × RDS(ON), and RDS(ON) is a function of the junction temperature. As an initial estimate, use the
RDS(ON) at 125°C from the Typical Characteristics, and the preferred package thermal resistance for the preferred
board construction from the Thermal Information table.

Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 17

TPS2069D
SLVSDQ5 – DECEMBER 2016 www.ti.com

Power Dissipation and Junction Temperature (continued)

TJ = TA + ((IOUT2 × RDS(ON)) × θJA)
where
• IOUT = rated OUT pin current (A)
• RDS(ON) = Power switch on-resistance at an assumed TJ (Ω)
• TA = Maximum ambient temperature (°C)
• TJ = Maximum junction temperature (°C)
• θJA = Thermal resistance (°C/W) (1)
If the calculated TJ is substantially different from the original assumption, estimate a new value of RDS(ON) using
the typical characteristic plot and recalculate.
If the resulting TJ is not less than 125°C, try a PCB construction and/or package with lower θJA.

18 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated

 TPS2069D
www.ti.com SLVSDQ5 – DECEMBER 2016

12 Device and Documentation Support

12.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2016, Texas Instruments Incorporated Submit Documentation Feedback 19

 PACKAGE OPTION ADDENDUM

www.ti.com 9-Dec-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS2069DDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 18PF
& no Sb/Br)
TPS2069DDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 125 18PF
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 9-Dec-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jul-2017

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2069DDBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS2069DDBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jul-2017

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2069DDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TPS2069DDBVT SOT-23 DBV 5 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA

1 5

2X 0.95
3.05
2.75
1.9 1.9
2

4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/D 11/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/D 11/2018

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/D 11/2018

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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