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TL5209
SLVS581B – SEPTEMBER 2006 – REVISED JUNE 2015

TL5209 500-mA Low-Noise Low-Dropout Voltage Regulator With Shutdown

1 Features 3 Description
•
1 Adjustable Output Voltage The TL5209 device is 500-mA low-dropout (LDO)
regulator that is well suited for portable applications.
• 1%/2% Accuracy (25°C/Full Range) It has a lower quiescent current than most traditional
• 500-mV (Maximum) Dropout at Full Load of PNP regulators and allows for a shutdown current of
500 mA 0.05 μA (typical). The TL5209 also has very good
• Tight Regulation Overtemperature Range dropout voltage characteristics, requiring a maximum
dropout of 10 mV at light loads and 500 mV at full
– 0.1%/V (Maximum) Line Regulation load. In addition, the LDO also has a 1% output
– 0.7% (Maximum) Load Regulation voltage accuracy and very tight line and load
• Ultra Low-Noise Capability (300 nV/√Hz Typical) regulation that is comparable to its CMOS
• Shutdown Current of 3 μA (Maximum) counterparts.
• Low Temperature Coefficient For noise-sensitive applications, the TL5209 allows
for low-noise capability through an external bypass
• Current Limiting and Thermal Protection
capacitor connected to the BYP pin, which reduces
• Stable With Minimum Load of 1 mA the output noise of the regulator. Other features
• Reverse-Battery Protection include current limiting, thermal shutdown, reverse-
• Applications battery protection, and low temperature coefficient.
– Portable Applications (PDAs, Laptops, The TL5209 is available with adjustable output.
Cell Phones) Offered in an SOIC-8 surface-mount package, the
TL5209 is characterized for operation over the virtual
– Consumer Electronics
junction temperature ranges of –40°C to 125°C.
– Post-Regulation for SMPS
• Available in Convenient SOIC-8 Surface-Mount Device Information(1)
Package PART NUMBER PACKAGE BODY SIZE (NOM)
TL5209 SOIC (8) 4.90 mm × 3.91 mm
2 Applications (1) For all available packages, see the orderable addendum at
• Set-Top Boxes the end of the data sheet.

• PCs and Notebooks

• EPOS
• Building Automation

4 Typical Application Schematic

VIN IN OUT VOUT

R1
1 µF 2.2 µF
EN ADJ/BYP
GND

470 pF R2

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL5209
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 12
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 9 Application and Implementation ........................ 13
4 Typical Application Schematic............................. 1 9.1 Application Information............................................ 13
9.2 Typical Application .................................................. 13
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 16
7 Specifications......................................................... 3 11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
7.1 Absolute Maximum Ratings .................................... 3
11.2 Layout Example .................................................... 16
7.2 ESD Ratings.............................................................. 3
7.3 Recommended Operating Conditions...................... 3 12 Device and Documentation Support ................. 17
7.4 Thermal Information .................................................. 4 12.1 Community Resources.......................................... 17
7.5 Electrical Characteristics........................................... 4 12.2 Trademarks ........................................................... 17
7.6 Typical Characteristics .............................................. 5 12.3 Electrostatic Discharge Caution ............................ 17
12.4 Glossary ................................................................ 17
8 Detailed Description ............................................ 12
8.1 Overview ................................................................. 12 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 12
Information ........................................................... 17

5 Revision History
Changes from Revision A (May 2007) to Revision B Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

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6 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View

EN 1 8 GND
IN 2 7 GND
OUT 3 6 GND
ADJ/BYP 4 5 GND

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
Adjust/Bypass pin, forces a constant voltage of 1.242 V to allow for adjusting the output
ADJ/BYP 4 I voltage with external resistors. A bypass capacitance can be used on this pin to slow down
the ramp up of the output voltage.
EN 1 I Control input, active high
GND 5-8 - Ground
IN 2 I Input voltage
OUT 3 O Output voltage

7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VI Continuous input voltage –20 20 V
VO Output voltage 7.5 V
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2500
V(ESD) Electrostatic discharge Charged device model (CDM), per JEDEC specification JESD22- ±1000 V
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VI Input voltage 2.5 16 V
VO Output voltage 6.5 V
VEN Enable input voltage 0 VI V
TJ Operating junction temperature –40 125 °C

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7.4 Thermal Information

TL5209
THERMAL METRIC (1) D [SOIC] UNIT
8 PINS
RθJA Junction-to-ambient thermal resistance 116.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 61.6 °C/W
RθJB Junction-to-board thermal resistance 56.3 °C/W
ψJT Junction-to-top characterization parameter 14.9 °C/W
ψJB Junction-to-board characterization parameter 55.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics

VIN = VOUT + 1 V, COUT = 4.7 μF, IOUT = 1 mA, full range TJ = –40°C to 125°C
PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT
25°C –1% 1%
Output voltage accuracy VOUT = 2.5 V for ADJ only
–40°C to 125°C –2% 2%
Output voltage
αVOUT –40°C to 125°C 40 ppm/°C
temperature coefficient
25°C 0.009 0.05
Line regulation VIN = (VOUT + 1 V) to 16 V %/V
–40°C to 125°C 0.1
25°C 0.05% 0.5%
Load regulation IOUT = 1 mA to 500 mA (1)
–40°C to 125°C 0.7%
25°C 45 60
IOUT = 1 mA
–40°C to 125°C 80
25°C 115 175
IOUT = 50 mA
–40°C to 125°C 250
VIN – VOUT Dropout voltage (2) mV
25°C 150 250
IOUT = 100 mA
–40°C to 125°C 300
25°C 350 500
IOUT = 500 mA
–40°C to 125°C 600
25°C 100 140
VEN ≥ 3 V, IOUT = 1 mA
–40°C to 125°C 170
μA
25°C 350 650
VEN ≥ 3 V, IOUT = 50 mA
–40°C to 125°C 900
IQ Quiescent current
25°C 1.2 2
VEN ≥ 3 V, IOUT = 100 mA
–40°C to 125°C 3
mA
25°C 8 20
VEN ≥ 3 V, IOUT = 500 mA
–40°C to 125°C 25
Imin Minimum load current (3) –40°C to 125°C 1 mA
VEN ≤ 0.4 V 25°C 0.05 3
ISD Shutdown current 25°C 0.1 μA
VEN ≤ 0.18 V
–40°C to 125°C 8
Ripple rejection f = 120 Hz 25°C 75 dB
25°C 700 900
ILIMIT Current limit VOUT = 0 V mA
–40°C to 125°C 1000

(1) Low duty cycle testing is used to maintain the junction temperature as close to the ambient temperature as possible. Changes in output
voltage due to thermal effects are covered separately by the thermal regulation specification.
(2) Dropout is defined as the input to output differential at which the output drops 2% below its nominal value measured at 1-V differential.
(3) For stability across the input voltage and temperature. For ADJ versions, the minimum current can be set by R1 and R2.
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Electrical Characteristics (continued)

VIN = VOUT + 1 V, COUT = 4.7 μF, IOUT = 1 mA, full range TJ = –40°C to 125°C
PARAMETER TEST CONDITIONS TJ MIN TYP MAX UNIT
ΔVOUT/ΔP VIN = 16 V, 500-mA load
Thermal regulation (4) 25°C 0.05 %/W
D pulse for t = 10 ms
VOUT = 2.5 V, IOUT = 50 mA,
25°C 500
COUT = 2.2 μF, CBYP = 0
Vn Output noise IOUT = 50 mA, nV/√Hz
COUT = 2.2 μF, 25°C 300
CBYP = 470 pF (5)
VEN = logic LOW 25°C 0.4
VEN Enable logic voltage (shutdown) –40°C to 125°C 0.18 V
VEN = logic HIGH (enabled) 25°C 2
VEN ≤ 0.4 V (shutdown) 25°C 0.01 –1
VEN ≤ 0.18 V (shutdown) –40°C to 125°C 0.01 –2
IEN Enable input current μA
25°C 5 20
VEN ≥ 2 V (enabled)
–40°C to 125°C 25

(4) Thermal regulation is defined as the change in output voltage at a specified time after a change in power dissipation is applied,
excluding line and load regulation effects.
(5) CBYP is optional and connected to the BYP/ADJ pin.

7.6 Typical Characteristics

0 0
VIN = 3.5 V VIN = 3.5 V
-10 -10
COUT = 2.2 µF COUT = 2.2 µF
-20 CBYP = 0 µF -20 CBYP = 0.01 µF
-30 IOUT = 1 mA IOUT = 1 mA
-30
-40
-40
PSRR – dB
PSRR – dB

-50
-50
-60
-60
-70
-70
-80
-80
-90

-100 -90

-110 -100
10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M

Frequency – Hz Frequency – Hz

Figure 1. Power Supply Rejection Ratio Figure 2. Power Supply Rejection Ratio

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Typical Characteristics (continued)

-10 0
VIN = 3.5 V VIN = 3.5 V
-20 -10
COUT = 2.2 µF COUT = 2.2 µF
-30 CBYP = 0 µF -20 CBYP = 0.01 µF
IL = 10 mA IOUT = 10 mA
-40 -30

-50 -40

PSRR – dB
PSRR – dB

-60 -50

-70 -60

-80 -70

-90 -80

-100 -90

-110 -100
10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06 1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M

f –Frequency
Frequency– Hz
– Hz Frequency – Hz

Figure 3. Power Supply Rejection Ratio Figure 4. Power Supply Rejection Ratio

0 0
VIN = 3.5 V VIN = 3.5 V
-10 -10
COUT = 2.2 µF COUT = 2.2 µF
-20 CBYP = 0 µF -20 CBYP = 0.01 µF
IOUT = 100 mA IOUT = 100 mA
-30 -30

-40 -40
PSRR – dB
PSRR – dB

-50 -50

-60 -60

-70 -70

-80 -80

-90 -90

-100 -100
1.E+01
10 1.E+02
100 1.E+03
1k 1.E+04
10k 1.E+05
100k 1.E+06
1M 10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06
Frequency – Hz Frequency – Hz

Figure 5. Power Supply Rejection Ratio Figure 6. Power Supply Rejection Ratio

120 120
VOUT = 2.5 V
110 IL = 1 mA 110
COUT = 2.2 µF VOUT = 2.5 V IL = 1 mA
100 IL = 10 mA 100
CBYP = 0 µF COUT = 2.2 µF
90 90 CBYP = 0.01 µF

80 80 IL = 10 mA
IL = 100 mA
PSRR – dB

PSRR – dB

70 70
60 60
50 50
40 40
30 30 IL = 100 mA
20 20

10 10
0 0
0 0.1 0.2 0.3 0.4 0.5 0 0.1 0.2 0.3 0.4 0.5
Voltage Drop – V Voltage Drop – V

Figure 7. Power Supply Ripple Rejection vs Voltage Drop Figure 8. Power Supply Ripple Rejection vs Voltage Drop

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Typical Characteristics (continued)

0.8 0.7
VIN = 3.5 V
0.7 COUT = 2.2 µF 0.6 IL = 100 mA
CBYP = 0 µF
0.6 IL = 1 mA
0.5

– µV/sqrt(Hz)
– µV/sqrt(Hz)

IL = 100 mA

– µV/√Hz
– µV/√Hz

0.5
IL = 10 mA 0.4
0.4
IL = 10 mA

Noise
0.3
Noise

IL = 1 mA

Noise
Noise

0.3
0.2
0.2
VIN = 3.5 V
0.1 0.1 COUT = 2.2 µF
CBYP = 0.01 µF
0 0
10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05
Frequency – Hz Frequency – Hz

Figure 9. Noise Performance Figure 10. Noise Performance

500 2.55
VOUT = 2.5 V VIN = 3.5 V
450 2.54
COUT = 2.2 µF COUT = 4.7 µF
400 CBYP = 0 2.53 IL = 1 mA
VDO – Dropout Voltage – mV

VOUT – Output Voltage – V

350 2.52

300 2.51

250 2.50

200 2.49

150 2.48

100 2.47

50 2.46

0 2.45
0 50 100 150 200 250 300 350 400 450 500 -40 -25 -10 5 20 35 50 65 80 95 110 125
IL – Load Current – mA TA – Temperature – °C

Figure 11. Dropout Voltage vs Load Current Figure 12. Output Voltage vs Temperature

20 2
VIN = 3.5 V
18 1.8
COUT = 4.7 µF
16 CIN = 1 µF 1.6
IGND – GND Pin Current – mA
IGND – GND Pin Current – mA

IL = 100 mA
14 1.4

12 1.2

10 1

8 0.8

6 0.6

4 0.4

2 0.2 IL = 1 mA

0 0
0 50 100 150 200 250 300 350 400 450 500 0 1 2 3 4 5 6 7 8
IL – Load Current – mA VCC – Supply Voltage – V

Figure 13. Ground Current vs Load Current Figure 14. Ground Current vs Supply Voltage

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Typical Characteristics (continued)

20 2.53
VIN = 3.5 V
18
IL = 500 mA COUT = 4.7 µF
2.52
16 IL = 1 mA to 500 mA
IGND – GND Pin Current – mA

VOUT – Output Voltage – V

14
2.51
12
TA = 25°C
10 2.50

8
TA = 125°C
2.49
6

4
2.48 TA = -40°C
2

0 2.47
0 1 2 3 4 5 6 7 8 0 50 100 150 200 250 300 350 400 450 500

VCC – Supply Voltage – V IL – Load Current – mA

Figure 15. Ground Current vs Supply Voltage Figure 16. Output Voltage vs Load Current

10 10
VIN = 3.5 V VIN = 3.5 V
COUT = 1 µF COUT = 2.2 µF
VENB = 2 V VENB = 2 V
Output Impedance – Ω♦

Output Impedance – Ωℵ
IL = 1 mA IL = 1 mA
1 1
IL = 10 mA IL = 10 mA

IL = 100 mA IL = 100 mA

0.1 0.1

0.01 0.01
10
1.E+01 100
1.E+02 1.E+03
1k 10k
1.E+04 100k
1.E+05 1.E+06
1M 10
1.E+01 100
1.E+02 1k
1.E+03 10k
1.E+04 100k
1.E+05 1M
1.E+06
Frequency – Hz Frequency – Hz

Figure 17. Output Impedance vs Frequency Figure 18. Output Impedance vs Frequency

2.55 0.5
VIN = 3.5 V to 16 V VIN = 3.5 V
2.54
COUT = 4.7 µF COUT = 4.7 µF
2.53 IL = 1 mA 0.4 IL = 1 mA to 500 mA
VOUT – Output Voltage – V

2.52
Load Regulation – %

2.51 0.3

2.50 TA = 25°C

2.49 TA = 125°C 0.2

2.48 TA = -40°C

2.47 0.1

2.46

2.45 0
3 6 9 12 15 18 -40 -25 -10 5 20 35 50 65 80 95 110 125
VIN – Input Voltage – V TA – Temperature – °C

Figure 19. Output Voltage vs Input Voltage Figure 20. Load Regulation

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Typical Characteristics (continued)

0.01 COUT = 10 µF
VIN = 3.5 V to 16 V VIN = 3.5 V
COUT = 4.7 µF

Load (mA)
VENB = 2 V
0.008 IL = 100 µA 100 CIN = 1 µF
Line Regulation – %/V

0.006
1

0.004

Output Voltage (mV)

10

Change in
0.002
0

0
-10
-50 -25 0 25 50 75 100 125

TA – Temperature – °C

Time (25 µs/div)

Figure 21. Line Regulation Figure 22. Load Transient Response

COUT = 10 µF
COUT = 2.2 µF
Load (mA) VIN = 3.5 V
VIN = 3.5 V
VENB = 2 V
VENB = 2 V 500
CIN = 1 µF
CIN = 1 µF
Load (mA)

100 1
Change in Output Voltage (mV)

20
Change in Output

10
Voltage (mV)

0 0

-10 -20

Time (25 µs/div) Time (25 µs/div)

Figure 23. Load Transient Response Figure 24. Load Transient Response

COUT = 10 µF
Input Voltage (V)

VIN = 3.5 V
COUT = 1 µF
VENB = 2 V
Load (mA)

4.5 IL = 1 mA
500 CIN = 1 µF
3.5

100
Change in Output Voltage (mV)

20
40
Output Voltage (mV)

10
Change in

20
0

0 -10

-20
Time (500 µs/div)

Time (25 µs/div)

Figure 25. Load Transient Response Figure 26. Line Transient Response

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Typical Characteristics (continued)

Input Voltage (V)

Input Voltage (V)

COUT = 2.2 µF COUT = 1 µF
4.5 IL = 1 mA 4.5 IL = 100 mA

3.5 3.5
Change in Output Voltage (mV)

Change in Output Voltage (mV)

20 20

10 10

0 0

-10 -10

Time (500 µs/div) Time (500 µs/div)

Figure 27. Line Transient Response Figure 28. Line Transient Response

Change in Output Voltage (mV) Input Voltage (V)

Input Voltage (V)

COUT = 2.2 µF COUT = 1 µF

4.5 IL = 100 mA 4.5 IL = 500 mA
3.5 3.5
Change in Output Voltage (mV)

20 20

10
10

0
0
-10
-10

Time (500 µs/div)

Time (500 µs/div)

Figure 29. Line Transient Response Figure 30. Line Transient Response
Enable Voltage (V)

2
Change in Output Voltage (mV) Input Voltage (V)

COUT = 2.2 µF
4.5 IL = 500 mA 0

3.5

2
Output Voltage (mV)

20

10 1
COUT = 1 µF
VIN = 3.5 V
0 0
ILOAD = 10 mA
-10 CIN = 1 µF

Time (500 µs/div)

Time (50 µs/div)

Figure 31. Line Transient Response Figure 32. Turnon Time

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Typical Characteristics (continued)

Enable Voltage (V)

Enable Voltage (V)

2 2

0 0

2 2
Output Voltage (mV)

Output Voltage (mV)

1 1
COUT = 1 µF COUT = 2.2 µF
VIN = 3.5 V VIN = 3.5 V
0 0
ILOAD = 500 mA ILOAD = 10 mA
CIN = 1 µF CIN = 1 µF

Time (50 µs/div) Time (50 µs/div)

Figure 33. Turnon Time Figure 34. Turnon Time
Enable Voltage (V)

1000
2 COUT = 2.2 µF

ISC – Short-Circuit Current Limit – mA

0 900

800

2
Output Voltage (mV)

700
1
COUT = 2.2 µF
VIN = 3.5 V 600
0
ILOAD = 500 mA
CIN = 1 µF
500
3 6 9 12 15 18

VCC – Supply Voltage – V

Time (50 µs/div)

Figure 35. Turnon Time Figure 36. Short-Circuit Current vs Supply Voltage

CIN = 1 µF VIN = 3.5 V CIN = 1 µF VIN = 16 V

800 COUT = 4.7 µF VOUT = 0 V COUT = 4.7 µF VOUT = 0 V
Short-Circuit Current – mA

1000
Short-Circuit Current – mA

600 900

400 800

200 600

0 400

200

Time – 25 ms/div Time – 10 ms/div

Figure 37. Short-Circuit Current vs Time Figure 38. Short-Circuit Current vs Time

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8 Detailed Description

8.1 Overview
The TL5209 device is a low-dropout (LDO) regulator with an input voltage range from 2.5 V to 16 V and a
maximum output current of 500 mA. The output voltage can be adjusted using external resistors (R1 and R2)
and has an accuracy of 1% to 2% depending on the ambient temperature. The maximum voltage drop across the
device varies from 10 mV to 500 mV depending on the current load at the output.

8.2 Functional Block Diagram

IN OUT
VIN VOUT

COUT
R1

ADJ/BYP
+
−
Bandgap
Reference CBYP
EN R2 (optional)

Current Limiting and

Thermal Shutdown

GND

Figure 39. Low-Noise Adjustable Regulator

8.3 Feature Description

8.3.1 Enable and Shutdown
The EN pin is CMOS-logic compatible. When EN is held high (>2 V), the regulator is active. Likewise, applying a
low signal (<0.4 V at 25°C) to EN or leaving it open shuts down the regulator. If the enable or shutdown feature
is not needed, EN should be tied to VIN.

8.4 Device Functional Modes

The table below lists the expected value of VOUT as determined by the EN pin.

Table 1. VOUT Function Table

EN (Control Input) VOUT
L Open
H 1.242 V × (1 + R2/R1)

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

9.1.1 Low-Voltage Operation
When using the TL5209 in voltage-sensitive applications, special considerations are required. If appropriate
output and bypass capacitors are not chosen properly, these devices may experience a temporary overshoot of
their nominal voltages.
At start-up, the full input voltage is initially applied across the regulator pass transistor, causing it to be
temporarily fully turned on. By contrast, the error amplifier and voltage-reference circuits, being powered from the
output, are not powered up as fast. To slow down the output ramp and give the error amplifier time to respond,
select larger values of output and bypass capacitors. The longer ramp time of the output allows the regulator
enough time to respond and keeps the output from overshooting its nominal value.
To prevent an overshoot when starting up into a light load (≉100 μA), TI recommends 4.7-μF and 470-pF
capacitors for the output and bypass capacitors, respectively. At higher loads, 10-μF and 470-pF capacitors
should be used.
If the application is not very sensitive to regulator overshoot, both the output capacitor and bypass capacitor (if
applicable) can be reduced.

9.2 Typical Application

VIN IN OUT VOUT

R1
1 µF 2.2 µF
EN ADJ/BYP
GND

470 pF R2

A. VOUT = 1.242 V (1 + R2/R1)

B. R2 should be ≤ 470 kΩ for optimal performance.
C. Maximum VOUT = 6.75 V ± 10%

Figure 40. TL5209 Typical Application

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
VIN 5V
R1 100 kΩ
Load current 500 mA
Desired VOUT 3.3 V

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9.2.2 Detailed Design Procedure

9.2.2.1 Setting the Output Voltage

The TL5209 develops a 1.242-V reference voltage, VREF, between the output and the adjust terminal. As shown
in Figure 40, this voltage is applied across resistor R1 to generate a constant current. The current IADJ from the
ADJ terminal could introduce DC offset to the output. Because, this offset is very small (about 50 nA), it can be
ignored. The constant current then flows through the output set resistor R2 and sets the output voltage to the
desired level. Equation 1 is used for calculating VOUT:
VOUT = 1.242 V × (1 + R2 / R1) (1)
With an R1 resistance of 100 kΩ and a desired output voltage of 3.3 V, the value for R2 can be calculated:
3.3 V = 1.242 V × (1 + R2 / 100 kΩ) (2)
100 kΩ × ((3.3 V / 1.242 V) - 1) = R2 (3)
R2 = 165.7 kΩ (4)
Therefore, with an R2 resistance of 165.7 kΩ, the output voltage can be set to 3.3 V.
The TL5209 adjustable output should not be adjusted above 6.75 V ± 10% due to the internal Zener diode
clamping the output voltage above 6.75 V. Although IADJ is very small, R2 should be limited to less than 470 kΩ
for optimum performance.

9.2.2.2 Input Capacitor

If the input of the regulator is located more than ten inches from the power-supply filter, or if a battery is used to
power the regulator, TI recommends a minimum 1-μF input capacitor.

9.2.2.3 Output Capacitor

As with all PNP regulators, an output capacitor is needed for stability. The required minimum size of this output
capacitor depends on several factors, one of which is whether a bypass capacitor is used.
• With no bypass capacitor, TI recommends a minimum COUT of 1 μF.
• With a bypass capacitor of 470 pF (see Figure 40), TI recommends a minimum COUT of 2.2 μF.
• Larger values of COUT are beneficial, because they improve the regulator transient response.
Another factor that can determine the minimum size of the output capacitor is the load current. At low loads, a
smaller output capacitor is needed for stability.
The equivalent series resistance (ESR) of the output capacitor also can affect regulator stability. COUT should
have an ESR of ≉1 Ω, and it should have a resonant frequency greater than 1 MHz. Too low of an ESR can
cause the output to have a low-amplitude oscillation and/or underdamped transient response. Most tantalum or
aluminum electrolytic capacitors can be used for the output capacitors. However, care must be taken at low
temperatures, because aluminum electrolytics use electrolytes that can freeze at low temperature (≉ –30°C).
Solid tantalum capacitors do not exhibit this problem and should be used below –25°C.

9.2.2.4 Bypass Capacitor

An optional bypass capacitor, CBYP, can be externally connected to the regulator through the BYP pin for
improved noise performance. Connected to the internal voltage divider and the error amplifier of the regulator,
this bypass capacitor filters the noise of the internal reference and reduces the noise effects on the error
amplifier. The overall result is a significant drop in output noise of the regulator. TI recommends a 470-pF bypass
capacitor.
Adding a bypass capacitor has several effects on the regulator that must be taken into account. First, the bypass
capacitor reduces the phase margin of the regulator and, thus, the minimum COUT needs to be increased to 2.2
μF, as previously mentioned. Second, upon start-up of the regulator, the bypass capacitor has an effect on the
regulator turnon time. If a slow ramp-up of the output is needed, larger values of CBYP should be used.
Conversely, if a fast ramp-up of the output is needed, use a smaller CBYP or none at all.
If a bypass capacitor is not needed, BYP should be left open.

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 TL5209
www.ti.com SLVS581B – SEPTEMBER 2006 – REVISED JUNE 2015

9.2.3 Application Curves

Figure 41 shows the expected output voltage versus R2 for various values of R1.
6.5
6.0
5.5
5.0

Output Voltage (V)

4.5
4.0
3.5
3.0
2.5
2.0 R1 = 50k:
R1 = 100k:
1.5
R1 = 200k:
1.0
0 50 100 150 200 250 300 350 400 450 500
R2 (k:) D001
Figure 41. Expected Output Voltage vs R2 Resistance

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TL5209
SLVS581B – SEPTEMBER 2006 – REVISED JUNE 2015 www.ti.com

10 Power Supply Recommendations

The device is designed to operate with an input voltage range of 2.5 V to 16 V. This supply must be well
regulated and placed as close to the device terminals as possible. It must also be able to withstand all transient
and load currents, using a recommended input capacitance of 1 µF if necessary. If the supply is located more
than a few inches from the device terminals, additional bulk capacitance may be required in addition to the
ceramic bypass capacitors. If additional bulk capacitance is required, an electrolytic, tantalum, or ceramic
capacitor of 10 µF may be sufficient.

11 Layout

11.1 Layout Guidelines

For best performance, VIN, VOUT, and GND traces must be as short and wide as possible to help minimize the
parasitic electrical effects. To be most effective, the input and output capacitors must be placed close to the
device to minimize the effects that parasitic trace inductances may have on normal operation.

11.2 Layout Example

Figure 42. TL5209 Layout Schematic

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 TL5209
www.ti.com SLVS581B – SEPTEMBER 2006 – REVISED JUNE 2015

12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2006–2015, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: TL5209
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TL5209DR ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL5209
& no Sb/Br)
TL5209DRG4 ACTIVE SOIC D 8 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM -40 to 125 TL5209
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Aug-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TL5209DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Aug-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TL5209DR SOIC D 8 2500 340.5 338.1 20.6

Pack Materials-Page 2
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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