MOS DEVICE FUNDAMENTALS

Professor A. K. Majumdar

Metal-Oxide Semiconductor (MOS) Field Effect Transistors

Computer Science and Engineering Department Indian Institute of Technology, Kharagpur

NMOS enhancement mode transistor
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Induced Channel in NMOS Transistor

Current Voltage characteristics of NMOS transistors

Enhancement mode NMOS transistor with VGS>0 showing induced channel

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NMOS Transistor Analysis

Induced Channel Charge / Unit Area Q(x) = - COX [ VGS V(x) Vth] Where COX = OX/ tOX capacitance per unit area due to gate oxide Drain current IDS = vn(x) Q(x)W vn(x) = drift velocity of electron

NMOS Transistor Analysis Contd

vn(x) = - n E(x) = n dV/dx n = Mobility of electrons Hence IDS = - n Q(x)W dV/dx Substituting for Q(x), IDS dx = n COX W[VGS V(x) Vth] dV Integrating IDS= n COX W/L[(VGS - Vth ) - VDS /2 ] VDS IDS = n [(VGS - Vth ) - VDS /2 ] VDS
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NMOS Transistor Analysis in Linear Region

kn =n COX = n OX/ tOX is called process transconductance parameter n = kn(W/L) is called gain factor For small VDS , VDS2 /2 can be ignored and IDS depends linearly on VDS Rlinear = 1/ (n (VGS - Vth))

NMOS Transistor Analysis in Linear Region

Transconductance of NMOS transistor gm = (dIDS/ dVGS) VDS = constant In linear region gm = n VDS

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NMOS Transistor Analysis Saturation Region

VDS VGS Vth Channel is pinched off Assuming voltage difference over induced channel from source to pinch off point fixed at VGS Vth IDS = n /2 (VGS Vth)2 In saturation region, MOS transistor acts as a constant current source. Transconductance in saturation region gm = n (VGS Vth)
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Current Voltage Relationship of NMOS Transistor

The drain-to-source current-voltage dependence for a NMOS transistor is given by the following equations
IDS = 0 IDS = n/2.(VGS Vth)2 for VDS < Vth (off) for 0 < VDS Vth < VDS (saturation)

IDS = n(VGS Vth VDS/2)VDS for VGS > Vth and VGS Vth VDS (linear) n = (nox/tox).W/L

where n is the mobility of electron, ox is the permittivity of the oxide material, and tox is the thickness of the oxide.
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Channel Length Modulation

In saturation region, the transistor does not operate as a perfect current source, i.e. IDS is not independent of VDS As VDS is increased beyond (VGS Vth) effective channel length decreases. Since IDS 1/L, reduction in effective channel length increases IDS More accurate representation IDS = n/2.(Vgs Vth)2 ( 1 + VDS)
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Current Voltage Relationship of PMOS Transistor

Cut off VGS > Vth IDS = 0 Linear Region: VGS Vth and VDS > VGS Vth IDS = p(VGS Vth VDS/2)VDS Saturation region VGS Vth, and VDS < VGSVth IDS = p/2.(VGSVth)2 where the gain factor p = (pox/tox).W/L and p is mobility of holes
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Lateral diffusion of source and drain regions

MOSFET Capacitances

Lateral diffusion = Ld Effective channel length Leff = L -2 Ld

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MOS transistor gate capacitances for three operating regions

NMOS Inverter

Capacitance CGB CGS CGD

Cutoff Linear Saturation CoxW Leff 0 0 Cox W Ld CoxW Ld + CoxW Leff CoxW Ld + 2/3 CoxW Leff Cox W Ld CoxW Ld + CoxW Leff CoxW Ld

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Pull Up and Pull Down transistors

The depletion mode transistor is a pull up device. It is always on (Vgs = 0) The enhancement mode transistor is the pull down device. With no current drawn from output, current in both pull up and pull down transistors must be same.

Current Voltage Characteristics of NMOS Inverter

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NMOS Inverter
The points of intersection of the pull up (for Vgs =0 ) and pull down curves give points on the transfer characteristics for the inverter As Vin exceeds VTpd (pull down transistor threshold) current will flow and Vout falls. Further increase in Vin will cause pull down transistor to be out of saturation and will behave as resistor Pull up device is initially resistive when pull down is turned on The point at which Vin = Vout is called Vinv Vinv can be shifted by variation of ratios of pull up and down resistances determined by the length to width ratio of the transistor.
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NMOS Inverter
With NMOS Depletion Mode transistor High Dissipation: When VIN is high current flows through both the devices. Output switching: occurs when Vin exceeds Vthpd During fall 1 0 transition, pull up offers lower resistance to charge capacitive load. Degrades 0 value : Low output value is determined by pull down resistance.
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CMOS INVERTER

CMOS Inverter
N Well VDD 2

VDD

PMOS

PMOS In Out
In Polysilicon

Contacts

Out Metal 1

NMOS
NMOS GND

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CMOS Fabrication

CMOS Fabrication

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Current Voltage Characteristics

CMOS INVERTER VOLTAGE TRANSFER CHARACTERISTICS

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CMOS INVERTER - CONTD

Region R1: 0 < Vin < Vthn, NMOS transistor is off, PMOS device operates in the linear region. Region R2: Vthn< Vin< VDD - |Vthp| and Vin + |Vthp| < Vout VDD, NMOS transistor in saturation, and PMOS transistor still in the linear region. Region R3: Vthn<Vin<VDD - |Vthp| and Vin - Vthn Vout Vin + |Vthp|, both the transistors are in saturation. Region R4: Vthn < Vin< VDD |Vthp| and Vout < Vin - Vthn, NMOS transistor is in the linear region and PMOS remains in saturation. Region R5: VDD |Vthp| < Vin < VDD, PMOS transistor in cut-off, NMOS in the linear region.

CMOS Inverter Characteristics

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Static Analysis of CMOS Inverter

Current Voltage Relationship of NMOS transistor : VGSn = Vin , VDSn = Vout n = (n /tox) (W/L)n Cut-off (Vin Vthn) : IDS = 0

Current Voltage Relationship of PMOS transistor

VGSp = - (VDD Vin), VDSp = - (VDD Vout) p = (p /tox) (W/L)n Cut-off (Vin > VDD - |Vthp|) : IDS = 0

Linear (Vin Vthn Vout) : IDS = n(VGSn Vthn VDSn/2)VDSn Saturation ( Vthn Vin, Vout > Vin Vthn): IDS = n/2(VGSn Vthn)2
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Linear (Vin VDD - |Vthp|) and (Vout >Vin +|Vthn|) : IDS = n(VGSp |Vthp| VDSp/2)VDSp Saturation (Vin VDD - |Vthp|) and (Vout Vin +|Vthp|) :IDS = p/2(VGSn |Vthp|)2

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Static Analysis of CMOS InverterContd

VOH = VDD VOL = 0 Vinv = [ Vthn + (1/)(VDD + Vthp)] / (1 + 1/) = n/p =[n(ox/tox)n (W/L)n ]/ [p(ox/tox)p(W/L)p] for = 1, (W/L)n / (W/L)p = p/n 1/2.5 (W/L)p 2.5 (W/L)n
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Static Analysis of CMOS InverterContd

VIL = (2Vout + Vthp VDD + Vthn) / (1 + ) = 1, and Vthn = Vthp VIL = 1/8 (3VDD +2 Vthn) VIH = [VDD + Vthp + (2 Vout + Vthn)] / (1 + ) with = 1, and Vthn = Vthp, VIH = (5VDD 2Vthn) /8

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NOISE MARGINS

Switching Characteristics of a CMOS Inverter

NML = VIL VOL = VIL NMH = VOH VIH = VDD VIH

Parasitic capacitances in a cascaded CMOS inverter

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Switch model of a static CMOS inverter

Propagation delay times and rise and fall times of an inverter

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CMOS inverter equivalent circuit during high-to-low and low-to-high output transitions

Propagation Delay Estimation

High to Low Transition pHL = pHL1 + pHL2 pHL1 = the period during which Vout drops from VDD to VDD Vthn. pHL1 = 2 CLVthn / n (VDD Vthn)2 pHL2 = the period during which Vout drops from VDD Vthn to VDD /2. pHL2 = n (V DD
4V thn CL ln 3 V thn ) V DD
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Propagation Delay Estimation Contd.

Low to High Transition pLH =
p(VDD|Vthp |)(VDD|Vthp |)
CL 2|Vthp | 4|Vthp | + ln3 VDD

Typical input - output and load capacitor current waveforms in a CMOS inverter

For pHL = pLH , (W/L)p 2.5 (W/L)n

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Power Dissipation in CMOS Inverter

Dynamic Power Consumption
Charging and Discharging Capacitors

Dynamic Power Consumption

Short Circuit Currents

Short Circuit Path between Supply Rails during Switching

Leakage
Leaking diodes and transistors

E-charge = CL VDD2 E-discharge = CL VDD2 Average Power dissipation PAvg= 1/T CL VDD2 = CL VDD2 f
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Switching Power Dissipation in CMOS Inverter

fmax = 1/2p Power Delay Product, PDP = Pavg p For f = fmax, PDP = CL VDD2 fmax p = CL VDD2 Note: average switching power dissipation of a CMOS inverter is independent of transistor sizes and characteristics provided there is full voltage swing Analysis is valid when output node of the gate undergoes one transition (0 to VDD) in a clock cycle.
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Switching Power Dissipation - Contd

When node transition rate is slower than clock rate PAvg = T CL VDD2 f where T is the node transition factor (effective number of power consuming transition per cycle) Energy Delay Product EDP = PDP p = CL VDD2 p

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Short Circuit Current in CMOS Inverter

Short Circuit Current

Short circuit current is large if output load capacitance is low and input rise/fall time is large. To reduce short circuit power dissipation input/output rise and fall times should be of same order = PAvg(short-circuit) = 1/12[k f (VDD- Vthn -|Vthp|)3]

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Sub Threshold Leakage

Reverse-Biased Diode Leakage ReverseGATE

p+

p+

Reverse Leakage Current +

V - dd

IDL = JS A

Reverse leakage Current of a p-n junction Ireverse= A JS(e

Reverse saturation current Density JS = 10-100 pA/m2
JS doubles for every 9 deg C!

qVbias/kT

1)

at 25 deg C for 0.25m CMOS,

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Advantages of CMOS Inverter

The high and low output voltages are equal to Vdd and ground respectively so that the voltage swing is the same as the supply voltage.. The logic levels are not dependent on the relative device sizes and hence the size of the transistors can be minimized. There is always a finite resistance between the output and either Vdd or ground in the steady state. The inverter can, therefore, be designed to have a low input impedance, making it less sensitive to noise. The CMOS inverter has a very high input resistance and draws no dc input current as the gate of a MOS transistor is virtually a perfect insulator.
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Technology Scaling
Full Scaling (Constant Field Scaling) Constant Voltage Scaling
Parameter Channel Length (L) Channel Width (W) Gate oxide thickness (tox) Supply voltage VDD Junction depth (Xj) Threshold voltage (Vth) Doping densities ND (NA) Full Scaling Constant-Voltage Scaling L/ L/ W/ W/ tox / tox / VDD / Xj/ Vth/ ND (NA) VDD Xj/ Vth ND (NA )
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2 2

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Effects of scaling on MOS transistor characteristics

Parameter Gate Area (A = WL) Oxide capacitance (Cox) Gate capacitance Cg (= CoxWL) Transconductance/Gain factor () Electric field (E) Drain current (IDS) Power dissipation (P) Power density ( PD = P/area) Gate delay () Full Scaling 2 A/ Constant-Voltage Scaling 2 A/

COMPLEMENTARY CMOS DESIGN

VDD In1 In2 InN In1 In2 InN PDN PMOS Circuit OUT= F(In1,In2,InN) NMOS Circuit

PUN

Cox Cg/
E IDS/ 2 P/ PD /

Cox Cg/ E IDS P 3 PD 2 /

Static Complementary CMOS Circuit

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COMPLEMENTARY CMOS NAND GATE

CMOS NAND GATE

With both input A =1, and B = 1 PMOS pull up transistors are in cut off. NMOS pull down transistors create conducting path. For other input combinations one of the pull up PMOS transistors will be on and NMOS network will be cut- off

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CMOS NAND GATE

Taking (W/L) to be same for each type of transistors, i.e. (W/L)n,A = (W/L)n,B and (W/L)p,A = (W/L)p,B Vinv = [Vthn + 2 sqrt(p / n) (VDD |Vthp|)] / (1+ 2 sqrt(p / n)) Assuming Vthn = |Vthp| , for Vinv = VDD/2, one should select n = 4 p .
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Lumped parameter switching model of a two input CMOS NAND gate

Delay is dependent on the input pattern : tpLH =0.69 Rp/2 CL for low to high output transition when both inputs go low. tpLH = 0.69 Rp CL when one input goes low. tpHL = 0.69 * 2 Rn CL for low to high transition of both inputs. To have same pull-down delay as the minimum sized inverter the NMOS devices in the PDN of the NAND gate should be twice as wide.
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4-Input NAND gate

CMOS TWO INPUT NAND GATE LAYOUT

Stick Diagram

Elmore Delay Model: tpHL = 0.69 Rn(C1+2C2+3C3+4CL) Propagation delay deteriorates rapidly as a function of fan-in quadratically Layout

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2-input NOR gate

CMOS NOR GATE

VOL = 0 and VOH =VDD Switching Threshold Computation
Assume (W/L) to be same for each type of transistors, i.e. (W/L)n,A = (W/L)n,B and (W/L)p,A = (W/L)p,B both input voltage switch simultaneously, i.e. VA = VB Neglect body effect for PMOS transistors

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CMOS NOR GATE

At switching Threshold VA = VB = Vout = Vinv NMOS transistors are in saturation (since VGS= VDS) Lower PMOS transistor (with A-input) is in linear region, the upper PMOS (B-input) is in saturation Vinv = [Vthn + sqrt(p /4 n) (VDD |Vthp|)] / (1+ sqrt(p /4 n)) Assuming Vthn = |Vthp| , for Vinv = VDD/2, one should select p = 4 n .
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XOR Gate

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CMOS realization of a switching function

F = (A+D) B + CD

Features of Complementary CMOS Design

No static power consumption
High noise margins : VOH = V DD , VOL = GND
Low output impedance Very high input resistance Logic levels independent of relative device sizes . of the NMOS and PMOS transistors : ratioless With proper sizing , rise and fall times are of same order

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Pass Transistor

Pass Transistor
NMOS pass transistor :
Passes 0 (low ) well but degrades 1 (high) Maximum value of output is VDD Vthn

PMOS pass transistor

Passes 1 without any degradation Low value is degraded to Vthp

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PASS TRANSISTOR LOGIC

PASS TRNASISTOR LOGIC - PROBLEMS

NMOS

pass transistor passes 0V(VOL) correctly, but degrades VOH to VDD Vthn .

PMOS pass transistor passes 1 i.e. VDD correctly but degrades 0 to |Vthp| When the input A is high, Q1 is turned on and input B is copied to the output Z. If A is low, the pass transistor Q2 is turned on and passes 0 to Z. The transistor Q2 offers low impedance path to the supply rails even when A is low.
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Signal level degradation can be remedied by insertion of a CMOS inverter or by the usage of suitable level restoration circuits. Pass transistor gates should not be cascaded

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COMPLEMENTARY PASS TRANSISTOR LOGIC

CMOS Transmission Gate Logic

With

CMOS transmission gates : No signal degradation

Equivalent resistance of a CMOS transmission gate is almost independent of the output voltage. Compared to the corresponding static CMOS realization the transmission gate realization would have speed advantage.
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CMOS transmission gate realization of XOR function.

Six transistor CMOS transmission gate realization of the XOR function.

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Dynamic CMOS Design

DYNAMIC CMOS LOGIC OPERATION

When CLK = 0, the output is pre-charged to VDD by the transistor Qp. The evaluation NMOS transistor Qe remains off during this time thus disabling the pull-down path. For CLK = 1, the evaluation Qe is turned on while the pre-charge transistor Qp is turned off. The output is conditionally discharged depending upon the inputs and the topology of the PDN - if the PDN is conducting, it would offer a low resistance path between out and the ground. On the other hand, if the PDN is turned off, the pre-charged value will remain stored in the output capacitance CL . Once the node out is discharged, it cannot be charged again till the next pre-charge begins. Thus during the evaluation phase the inputs can make not more than just one transition.
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The circuit operates in two phases, pre-charge and evaluation, and the mode of operation is determined by the clock signal CLK
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DYNAMIC CMOS DESIGN ADVANTAGES

The number of transistors required is (N + 2) in dynamic CMOS as compared to 2N for static design. The dynamic design is non-ratioed. The size of the CMOS pre-charge transistor is not important for proper realization of the gate and hence can be increased to improve the low-tohigh transition time. The dynamic gates have reduced load capacitance because of a fewer number of transistors and hence faster switching speeds.
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Dynamic CMOS realization of the Boolean function F=AB+BD+CD

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Charge sharing in a dynamic CMOS Circuit

CHARGE SHARING PROBLEMS WITH DYNAMIC LOGIC

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Cascading problem in dynamic CMOS gates

DOMINO LOGIC

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DOMINO LOGIC OPERATION

A static inverter (buffer) follows an n-type dynamic logic block. Pre-charge phase: CLK=Low, output of the dynamic gate is charged up to VDD through Qp which is ON and Inverter output is Low. Evaluation phase: CLK=High, Qp turns off, inverter output can change for Low to High depending on the inputs if PDN conducts, dynamic gate will discharge and inverter output will become high, else output of dynamic gate will remain charged (high) and the poutput of domino gate will remain low. The inverter output voltage can make at most one transition from 0 to 1 during the evaluation phase. The buffer output can never make 1 to 0 transition during the evaluation phase for any combination of the input values. Hence a domino gate can only implement non-inverting logic.

REFERENCES
1. 2. 3. Rabaey J. M.,Chandrakasan A., and Nikolic B., Digital Integrated Circuits, Prentice- Hall of India, 2003. Kang, Sung-Mo and Leblebici, Y.: CMOS Digital Integrated Circuits, McGraw Hill Pub., 2003 Weste N.H.E and Eshraghlan, K: Principles of CMOS VLSI Design, Pearson Education, 2004.

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