MTP52N06V

Preferred Device

Power MOSFET
52 Amps, 60 Volts
NChannel TO220

This Power MOSFET is designed to withstand high energy in the

avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected voltage
transients.
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature

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52 AMPERES
60 VOLTS
RDS(on) = 22 m
NChannel
D

MAXIMUM RATINGS (TC = 25C unless otherwise noted)

Symbol

Value

Unit

DrainSource Voltage

VDSS

60

Vdc

DrainGate Voltage (RGS = 1.0 M)

VDGR

60

Vdc

GateSource Voltage
Continuous
NonRepetitive (tp 10 ms)

VGS
VGSM

20
25

Vdc
Vpk

ID
ID

52
41
182

Adc

PD

188
1.25

Watts
W/C

TJ, Tstg

55 to
175

EAS

406

mJ

Rating

Drain Current Continuous

Drain Current Continuous @ 100C
Drain Current Single Pulse (tp 10 s)
Total Power Dissipation
Derate above 25C
Operating and Storage Temperature
Range
Single Pulse DraintoSource Avalanche
Energy Starting TJ = 25C
(VDD = 25 Vdc, VGS = 10 Vdc,
IL = 52 Apk, L = 0.3 mH, RG = 25 )
Thermal Resistance
Junction to Case
Junction to Ambient
Maximum Lead Temperature for Soldering
Purposes, 1/8 from case for 10
seconds

IDM

G
S

MARKING DIAGRAM
& PIN ASSIGNMENT

Apk

TO220AB
CASE 221A
STYLE 5
1

RJC
RJA

0.8
62.5

TL

260

C/W

4
Drain

MTP52N06V
LLYWW
1
Gate

3
Source
2
Drain

C
MTP52N06V
LL
Y
WW

= Device Code
= Location Code
= Year
= Work Week

ORDERING INFORMATION
Device
MTP52N06V

Package

Shipping

TO220AB

50 Units/Rail

Preferred devices are recommended choices for future use

and best overall value.

Semiconductor Components Industries, LLC, 2006

August, 2006 Rev. 5

Publication Order Number:

MTP52N06V/D

MTP52N06V
ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)
Characteristic

Symbol

Min

Typ

Max

Unit

60

66

Vdc
mV/C

10
100

100

nAdc

2.0

2.7
6.4

4.0

Vdc
mV/C

0.019

0.022

1.4
1.2

gFS

17

24

mhos

Ciss

1900

2660

pF

Coss

580

810

Crss

150

300

td(on)

12

20

tr

298

600

td(off)

70

140

tf

110

220

QT

125

175

Q1

10

Q2

30

Q3

40

1.0
0.98

1.5

trr

100

ta

80

tb

20

QRR

0.341

3.5
4.5

7.5

OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)

(Cpk 2.0) (Note 3)

V(BR)DSS

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C)

IDSS

GateBody Leakage Current (VGS = 20 Vdc, VDS = 0)

IGSS

Adc

ON CHARACTERISTICS (Note 1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 Adc)
Temperature Coefficient (Negative)

(Cpk 2.0) (Note 3)

VGS(th)

Static DrainSource OnResistance

(VGS = 10 Vdc, ID = 26 Adc)

(Cpk 2.0) (Note 3)

RDS(on)

DrainSource OnVoltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150C)

VDS(on)

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

Ohm
Vdc

DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)

Output Capacitance
Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS (Note 2)

TurnOn Delay Time
(VDD = 30 Vdc, ID = 52 Adc,
VGS = 10 Vdc,
RG = 9.1 )

Rise Time
TurnOff Delay Time
Fall Time
Gate Charge
(See Figure 8)

(VDS = 48 Vdc, ID = 52 Adc,

VGS = 10 Vdc)

ns

nC

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (Note 1)

(IS = 52 Adc, VGS = 0 Vdc)

(IS = 52 Adc, VGS = 0 Vdc, TJ = 150C)

Reverse Recovery Time

(See Figure 14)
(IS = 52 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s)
Reverse Recovery Stored
Charge

VSD

Vdc

ns

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25 from package to center of die)

LD

Internal Source Inductance

(Measured from the source lead 0.25 from package to source bond pad)

LS

1. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.

2. Switching characteristics are independent of operating junction temperature.
Max limit Typ
3. Reflects typical values.
Cpk =
3 x SIGMA

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2

nH

nH

MTP52N06V
TYPICAL ELECTRICAL CHARACTERISTICS

VGS = 10 V
9V

I D , DRAIN CURRENT (AMPS)

80
70
60

6V

50
40
30

5V

0.035

10

70
60
50
40
30

TJ = 55C
2.5

3.5

4.5

5.5

6.5

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

TJ = 100C

0.025
25C
0.02

0.015

55C

0.01

0.005
10

20

30

40

50

60

70

80

90

0.023

95

105

TJ = 25C

0.021
VGS = 10 V

0.020
0.019

15 V

0.018
0.017
0.016

0.015

100 110

7.5

0.022

25

15

35

45

55

65

75

85

ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

100

2
1.75

VGS = 0 V

VGS = 10 V
ID = 26 A

1.5

I DSS , LEAKAGE (nA)

RDS(on) , DRAINTOSOURCE RESISTANCE

(NORMALIZED)

25C

80

10
0

VGS = 10 V

90

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.03

100C

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

10
0

VDS 10 V

100

7V

90

20

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

110

TJ = 25C

8V

I D , DRAIN CURRENT (AMPS)

110
100

1.25
1
0.75

TJ = 125C

10
100C

0.5
0.25
50

25

25

50

75

100

125

150

175

TJ, JUNCTION TEMPERATURE (C)

10

20

30

40

50

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with

Temperature

Figure 6. DrainToSource Leakage

Current versus Voltage

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3

60

MTP52N06V
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because draingate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)

The capacitance (Ciss) is read from the capacitance curve at

a voltage corresponding to the offstate condition when
calculating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

During the rise and fall time interval when switching a

resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
7000

VDS = 0 V

C, CAPACITANCE (pF)

VGS = 0 V

TJ = 25C

Ciss

6000
5000

Crss

4000
3000

Ciss

2000

Coss

1000
0

Crss
10

0
VGS

10

15

20

25

VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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4

36
33

QT
10

30
27

VGS

24
21

Q2

Q1

18
15

12
9

ID = 52 A
TJ = 25C

2
0

Q3
0

20

VDS
40

60
80
100
QT, TOTAL CHARGE (nC)

120

6
3
0
140

1000

t, TIME (ns)

12

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

MTP52N06V
VDD = 30 V
ID = 52 A
VGS = 10 V
TJ = 25C

100

tr
tf
td(off)

td(on)

10

1
1

10
RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

100

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

55

VGS = 0 V
TJ = 25C

I S , SOURCE CURRENT (AMPS)

50
45
40
35
30
25
20
15
10
5
0
0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.1

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
Transient
Thermal
ResistanceGeneral Data and Its Use.
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 s. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) TC)/(RJC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance

dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous ID can safely be
assumed to equal the values indicated.

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5

MTP52N06V
SAFE OPERATING AREA
450

VGS = 20 V
SINGLE PULSE
TC = 25C

EAS, SINGLE PULSE DRAINTOSOURCE

AVALANCHE ENERGY (mJ)

I D , DRAIN CURRENT (AMPS)

1000

10s

100

100s
10

1ms
10ms

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

dc

10
1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

0.1

ID = 52 A

400
350
300
250
200
150
100
50
0

100

25

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

50
75
100
125
150
TJ, STARTING JUNCTION TEMPERATURE (C)

175

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

r(t), NORMALIZED EFFECTIVE

TRANSIENT THERMAL RESISTANCE

1
D = 0.5
0.2
0.1
0.1 0.05

P(pk)

0.02
t1

0.01

t2
DUTY CYCLE, D = t1/t2

SINGLE PULSE
0.01
1.0E05

1.0E04

1.0E03

1.0E02
t, TIME (s)

1.0E01

Figure 13. Thermal Response

di/dt
IS
trr
ta

tb
TIME
0.25 IS

tp
IS

Figure 14. Diode Reverse Recovery Waveform

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6

RJC(t) = r(t) RJC

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) RJC(t)

1.0E+00

1.0E+01

MTP52N06V
PACKAGE DIMENSIONS
TO220 THREELEAD
TO220AB
CASE 221A09
ISSUE AA

SEATING
PLANE

T
B

C
S

DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

Q
1 2 3

H
K

Z
L

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

G
D
N

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

STYLE 5:
PIN 1.
2.
3.
4.

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

GATE
DRAIN
SOURCE
DRAIN

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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MTP52N06V/D