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    M. Tech (VLSI Design) II Semester End Term Examination, May 2020 MVL 202: Analog IC Design

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    Neeraj Sharma
    This document is the question paper for the M. Tech (VLSI Design) II Semester End Term Examination in the subject Analog IC Design. It contains 10 short answer questions in Module 1 worth 1 mark each, 2 long answer questions in Module 1 worth 10 marks total, and long answer or alternative questions in Modules 2 through 5 worth 10 marks each. The questions cover topics such as small-signal MOSFET models, noise, fabrication processes, differential amplifiers, operational amplifiers, voltage references, compensation techniques, and switched capacitor circuits.

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    M. Tech (VLSI Design) II Semester End Term Examination, May 2020 MVL 202: Analog IC Design

    Uploaded by

    Neeraj Sharma
    90 views3 pages
    This document is the question paper for the M. Tech (VLSI Design) II Semester End Term Examination in the subject Analog IC Design. It contains 10 short answer questions in Module 1 worth 1 mark each, 2 long answer questions in Module 1 worth 10 marks total, and long answer or alternative questions in Modules 2 through 5 worth 10 marks each. The questions cover topics such as small-signal MOSFET models, noise, fabrication processes, differential amplifiers, operational amplifiers, voltage references, compensation techniques, and switched capacitor circuits.

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    This document is the question paper for the M. Tech (VLSI Design) II Semester End Term Examination in the subject Analog IC Design. It contains 10 short answer questions in Module 1 worth 1 mark each, 2 long answer questions in Module 1 worth 10 marks total, and long answer or alternative questions in Modules 2 through 5 worth 10 marks each. The questions cover topics such as small-signal MOSFET models, noise, fabrication processes, differential amplifiers, operational amplifiers, voltage references, compensation techniques, and switched capacitor circuits.

    Copyright:

    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    90 views3 pages

    M. Tech (VLSI Design) II Semester End Term Examination, May 2020 MVL 202: Analog IC Design

    Uploaded by

    Neeraj Sharma
    This document is the question paper for the M. Tech (VLSI Design) II Semester End Term Examination in the subject Analog IC Design. It contains 10 short answer questions in Module 1 worth 1 mark each, 2 long answer questions in Module 1 worth 10 marks total, and long answer or alternative questions in Modules 2 through 5 worth 10 marks each. The questions cover topics such as small-signal MOSFET models, noise, fabrication processes, differential amplifiers, operational amplifiers, voltage references, compensation techniques, and switched capacitor circuits.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
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    : ---------------------- Total Printed Page : 3

    M. Tech (VLSI Design) II Semester End Term Examination, May 2020

    MVL 202 : Analog IC Design


    Time: 3 Hours Total Marks: 60

     Marks of question are indicated against each question including sub parts of the question.
     Draw neat and comprehensive sketches wherever necessary to clearly illustrate your answer.
    Assume missing data suitably if any and specify the same.

    Q.1 Attempt all questions. Each question carries one mark


    [10*1=10]

    1. Define second order effects in MOS transistors.


    2. Briefly discuss thermal and Flicker noise..
    3. Define Short Channel effects in MOS transistors.
    4. Discuss Miller’s effect with relevant equations.
    5. Effect of loading on feedback amplifiers.
    6. Define Cascade current mirrors with diagram
    7. Draw diagram of two stage operational amplifier.

    8. Frequency response of two stage amplifier follows the relationship


    (a) Non linearity (b) Linearity, constant (c) parabolic (d) Exponential

    9. Discuss Non- linearity of Differential Circuits

    10. Define Offset effects in Amplifiers.


    Module – 1

    Q.2 (a) Explain the Small-signal model for the MOS Transistor. [4]
    (b) Write short notes on:
    (i) MOSFET noise (ii) Substrate Coupling [6]

    OR
    Q.3 (a) Write short note on Double Poly Process of analog IC design [4]
    (b) Explain with suitable diagrams the fabrication process of active devices, passive
    device and their interconnects. [6]
    Module – 2

    Q.4 (a) Explain working and operation of single-ended differe of differential amplifier [4]
    (b) Discuss in detail the relationship between cascade – current mirror and Wilson
    -current mirror. [6]

    OR
    Q.5 (a) Explain the following terms:
    (i) Common mode response (ii) Current sources in Differential Amplifiers
    [4]

    (b) Perform the Large signal analysis of CMOS differential amplifiers. [6]

    Module – 3

    Q.6 (a) Neglecting Channel length modulation, Calculate the pole associated with note x
    (take a node arbitrarily for an op-amp) [6]
    (b) Explain the major issues of different configurations of voltage References. [4]

    OR
    Q.7 (a) Explain series and shunt topologies of Voltage References. Discuss some of the major
    issues regarding this [6]
    (b) Obtain the transfer function and total capacitance of a two – stage amplifiers using op
    -amp [4]

    Module – 4

    Q.8 (a) Explain the Compensation techniques used for Op-amps. [4]

    (b) Compare various topologies technologies used in an Op-amp. [6]

    OR

    Q.9 (a) Explain the slew rate for p-channel differential amplifier with necessary equations.

    [4]
    (b) Explain the design of 2 – stage MOS operational amplifier. Discuss about gain
    boosting. [6]
    Module – 5

    Q.10(a) Discuss speed considerations and precision considerations in switched capacitor

    circuits. [5]

    (b) What are the methods of Capacitive switching in switched capacitor amplifier?

    Explain any one of these. [5]

    OR

    Q.11 (a) Define: Compensation techniques and Offset cancellation in amplifiers [5]

    (b) Explain Charge Injection Cancellation in transistor (MOS) amplifiers. Discuss


    concept behind switched capacitor common mode feedback. [5]

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