Automotive 38 V, 5 W Synchronous Iso-Buck Converter For Isolated Applications

A6986I
Datasheet
Automotive 38 V, 5 W synchronous iso-buck converter for isolated applications
Features
• AEC-Q100 Grade 1 qualified

• Designed for iso-buck topology
HTSSOP16 (RTH = 40 °C/W) • 4 V to 38 V operating input voltage
• Primary output voltage regulation / no optocoupler required
• 1.9 A typical sink peak primary current capability
• Peak current mode architecture in forced PWM operation
• 300 ns blanking time
• 8 µA IQ-SHTDWN
• Adjustable fSW and synchronization
• Embedded primary output voltage supervisor
• Adjustable soft-start time
• Internal primary current limiting
• Overvoltage protection
• RDS(on) HS = 180 mΩ, RDS(on) LS = 150 mΩ
• Thermal shutdown
Applications
• Automotive isolated IGBT/SiC MOSFET gate drive supply
Maturity status link • OBC (On-board charger) for HEV/EV
A6986I • Electric traction systems
Description
The A6986I is an automotive grade device specifically designed for the isolated
buck topology. The 100% duty cycle capability and the wide input voltage range
meet the cold crank and load dump specifications for automotive systems. The
primary output voltage can be accurately adjusted, whereas the isolated secondary
output is derived by using a given transformer ratio. No optocoupler is required. The
primary sink capability typically up to 1.9 A (even during soft-start) allows a proper
energy transfer to the secondary side as well as enabling a tracked soft-start of the
secondary output. The control loop is based on a peak current mode architecture
and the device operates in forced PWM. The 300 ns blanking time filters oscillations,
generated by the transformer leakage inductance, making the solution more robust.
Pulse-by-pulse current sensing on both power elements implements an effective
constant current protection in the primary side. Due to the primary reverse current
limit, the secondary output is protected against short-circuit events. A primary output
voltage supervisor, which notifies primary output voltage regulation through the
RST open collector output, overvoltage protection, adjustable switching frequency,
synchronization and a programmable soft-start are also available. For traditional
buck topology in automotive application the A6986 / A6985F / A6986F / A6986H is
recommended.
DS13481 - Rev 2 - May 2021 www.st.com

For further information contact your local STMicroelectronics sales office.
A6986I
Application schematic
1 Application schematic
Figure 1. Application schematic
DS13481 - Rev 2 page 2/62

A6986I
Pin connection
2 Pin connection
Figure 2. Pin connection (top view)
RST 1 16 VBIAS
VCC 2 15 VIN
SS/INH 3 14 LX
EXPOSED
SYNCH 4 PAD TO 13 LX
FSW 5 SGND+PGND 12 PGND
MLF 6 11 PGND
COMP 7 10 SGND
DELAY 8 9 FB
Table 1. Pin description
N° Pin Description
The RST open collector output is driven low when the output voltage is out of regulation. The
1 RST RST is released after an adjustable time DELAY once the primary output voltage is over the
active delay threshold.
Connect a ceramic capacitor (≥ 470 nF) to filter internal voltage reference. This pin supplies
2 VCC
the embedded analog circuitry.
An open collector stage can disable the device clamping this pin to GND (INH mode).
3 SS / INH An internal current generator (4 µA typ.) charges the external capacitor to implement the
soft-start.
4 SYNCH The pin features master / slave synchronization. Leave this pin floating when it is not used.
A pull-up resistor (E24 series only) to VCC or pull-down to GND selects the switching
5 FSW frequency. Pin strapping is active only before the soft-start phase to minimize the IC
consumption.
Connect this pin to ground either directly or through a pull-down resistor if the RST threshold
6 MLF
should be adjusted (see Table 7).
7 COMP Output of the error amplifier. The designed compensation network is connected at this pin.
An external capacitor connected to this pin sets the time DELAY to assert the rising edge of
8 DELAY the RST open collector after the output voltage is over the reset threshold. If this pin is left
floating, RST is like a Power Good.
9 FB Primary output voltage sensing
10 SGND Signal GND
11 PGND Power GND
12 PGND Power GND
13 LX Switching node
14 LX Switching node
15 VIN DC input voltage
Typically connected to the regulated primary output voltage, if it does not exceed 6 V.
16 VBIAS
Otherwise connect it to GND.
- Exposed pad Exposed pad must be connected to SGND, PGND
DS13481 - Rev 2 page 3/62

A6986I
Maximum ratings
2.1 Maximum ratings

Stressing the device above the rating listed in the table below may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or any other conditions above those indicated
in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Table 2. Absolute maximum ratings
Symbol Description Min. Max. Unit
VIN -0.3 40 V
DELAY -0.3 VCC + 0.3 V

PGND SGND - 0.3 SGND + 0.3 V
SGND - - V
VCC -0.3 (VIN + 0.3) or (max. 4) V
SS /INH -0.3 VIN + 0.3 V

MLF -0.3 VCC + 0.3 V
See Table 1
COMP -0.3 VCC + 0.3 V
VFB -0.3 10 V
FSW -0.3 VCC + 0.3 V
SYNCH -0.3 VIN + 0.3 V
VBIAS -0.3 (VIN + 0.3) or (max. 6) V
RST -0.3 VIN + 0.3 V

LX -0.3 VIN + 0.3 V
TJ Operating temperature range -40 150 °C
TSTG Storage temperature range - -65 to 150 °C
TLEAD Lead temperature (soldering 10 s.) - 260 °C
IHS, ILS High-side / low-side switch current - 2 A
Table 3. Thermal data
Symbol Parameter Value Unit
Thermal resistance junction ambient (device soldered

RthJA 40 °C/W
on the STMicroelectronics demonstration board)
Thermal resistance junction to exposed pad for board
RthJC design (not suggested to estimate TJ from power 5 °C/W
losses)
Table 4. ESD protection
Symbol Test conditions Value Unit
HBM 2 kV
ESD CDM 500 V
CDM corner pins 750 V
DS13481 - Rev 2 page 4/62

A6986I
Electrical characteristics
3 Electrical characteristics
Table 5. Electrical characteristics (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified).
Symbol Parameter Test condition Min. Typ. Max. Unit
VIN Operating input voltage range 4 38
VIN_H VCC UVLO rising threshold 2.7 3.5 V
VIN_L VCC UVLO falling threshold 2.4 3.5
Duty cycle < 20% 2.55

IPK Peak current limit
Duty cycle = 100% closed loop operation 2.1
IVY Valley current limit 2.7
A
TJ = - 40°C 1.165 1.9 2.755
IVY_SNK Reverse current limit TJ = 25°C 1.285 1.9 2.61
TJ = 135°C 1.385 1.9 2.425
RDS(on)HS High-side RDSON ISW = 1 A 0.18 0.36

Ω
RDS(on)LS Low-side RDSON ISW = 1 A 0.15 0.30
fSW Selected switching frequency FSW pinstrapping before SS See Table 6
IFSW FSW biasing current SS ended 0 500 nA
IMLF MLF biasing current SS ended 0 500 nA
D Duty cycle (1) 0 100 %
TJ = - 40°C 267 325 379
TON MIN Minimum on-time TJ = 25°C 281 330 383 ns
TJ = 135°C 330 400 461
VCC regulator
VBIAS = GND (no switchover) 2.9 3.3 3.6

VCC LDO output voltage
VBIAS = 5 V (switchover) 2.9 3.3 3.6
V
Switch internal supply from VIN to VBIAS 2.85 3.2
SWO VBIAS threshold (3 V < VBIAS < 5.5 V)
Switch internal supply from VBIAS to VIN 2.7 3.15
Power consumption
ISHTDWN Shutdown current from VIN VSS / INH = GND 4 8 15 μA
SWO
0.5 1.5 5
VFB = GND (NO SLEEP) VBIAS = 3.3 V
IQ OPVIN Quiescent current from VIN mA
NO SWO VFB = GND (NO SLEEP) VBIAS =
2 2.8 6
GND
IQ OPVBIAS Quiescent current from VBIAS SWO VFB = GND (NO SLEEP) VBIAS = 3.3 V 0.5 1.2 5 mA
Soft-start
VINH VSS threshold SS rising 200 460 700
mV
VINH HYST VSS hysteresis 75 140
VSS < VINH or t < TSS SETUP or VEA + > VFB(1) 1

ISS CH CSS charging current μA
t > TSS SETUP and VEA + < VFB(1) 4
DS13481 - Rev 2 page 5/62

A6986I
Symbol Parameter Test condition Min. Typ. Max. Unit
VSS START Start of internal error amplifier ramp 0.995 1.1 1.150 V
SS/INH to internal error amplifier

SSGAIN 3
gain
Error amplifier
VFB Voltage feedback 0.841 0.85 0.859 V
IFB FB biasing current 50 500 µA
AV Error amplifier gain (1) 100 dB
±6 ±12 ±25 µA
ICOMP EA output current capability
±4 (2)
Inner current loop

Current sense transconductance
gCS Ipk = 1 A 2.5 A/V
(VCOMP to inductor current gain) (1)
VPP*gCS Slope compensation (3) 0.45 0.75 1.1 A
Overvoltage protection
VOVP Overvoltage trip (VOVP/VREF) 1.15 1.2 1.25
VOVP HYST Overvoltage hysteresis 0.5 2 5 %
Synchronization (fanout: 6 slave devices typ.)

FSW = VCC 275 1000
fSYNCH Synchronization frequency kHz
FSW = GND 475 2200
VSYN TH SYNCH input threshold SYNCH rising 0.70 1.2 V
ISYN SYNCH pull-down current VSYN = 1.2 V 0.7 mA
High level output 5 mA sinking load 1.40

VSYN OUT V
Low level output 0.7 mA sourcing load 0.6
Reset
VTHR Selected RST threshold MLF pinstrapping before SS See Table 3
VTHR HYST RST hysteresis (1) 2 %
VIN > VIN and VFB < VTH4 mA sinking load 0.4
VRST RST open collector output V
2 < VIN < VINH 4 mA sinking load 0.8
Delay
RST open collector released as soon
VTHD VFB > VTHR 1.19 1.234 1.258 V
as VDELAY > VTHD
ID CH CDELAY charging current VFB > VTHR 1 2 3 µA
Thermal shutdown
TSHDWN Thermal shutdown temperature (1) 165
°C
THYS Thermal shutdown hysteresis (1) 30
1. Not tested in production.

2. TJ = -40°C.
3. Measured at fSW = 250 kHz.
DS13481 - Rev 2 page 6/62

A6986I
Table 6. fSW selection (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified).
Symbol RVCC (E24 series) RGND (E24 series) Tj fSW min. fSW typ. fSW max. Unit
0Ω NC (1) 225 250 275
1.8 Ω NC - 285 -
3.3 kΩ NC - 330 -
(1) (2)
5.6 kΩ NC - 380 -
10 kΩ NC - 435 -
fSW NC 0Ω (3) 450 500 550 kHz
18 kΩ NC - 575 -
33 kΩ NC - 660 -
(1)(3)
56 kΩ NC - 755 -
NC 1.8 kΩ - 870 -
NC 3.3 kΩ (3) 900 1000 1100
1. Synchronization as slave between 275 kHz and 1000 kHz.

2. Not tested in production.
3. Synchronization as slave between 475 kHz and 1000 kHz.
Figure 3. Circuit RVCC, RGND
VCC
VCC
RVCC
A6986I
FSW
A6986I FSW
RGND
SGND SGND
Table 7. RST threshold selection (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified).
Symbol RGND (E241%) VRST/VOUT (tgt. value) VRSTmin. VRSTtyp. VRSTmax. Unit
0Ω (1) 93% 0.779 0.791 0.802
8.2 kΩ ±1% (1) 80% 0.670 0.680 0.690

VRST V
18 kΩ ±1% (1) 87% 0.728 0.740 0.751
39 kΩ ±1%(2) 96% 0.804 0.816 0.828
1. please use the pre-defined resistor values.

2. do not exceed the indicated resistor value.
DS13481 - Rev 2 page 7/62

A6986I
Parameters over the temperature range
4 Parameters over the temperature range
A 100% of the population in the production flow is tested at three different ambient temperatures (-
40°C, + 25°C, + 135°C) to guarantee the datasheet parameters inside the junction temperature range
(- 40°C, + 135°C).
The device operation is guaranteed when the junction temperature is inside the (- 40°C, + 150°C) temperature
range. The designer can estimate the silicon temperature increase with respect to the ambient temperature
evaluating the internal power losses generated during the device operation.
However, the embedded thermal protection disables the switching activity to protect the device in case the
junction temperature reaches the TSHTDWN (+ 165°C typ.) temperature.
All the datasheet parameters can be guaranteed to a maximum junction temperature of + 135°C to avoid
triggering the thermal shutdown protection during the testing phase because of self-heating.
DS13481 - Rev 2 page 8/62

A6986I
Functional description
5 Functional description
The iso-buck topology based on the A6986I consists of:

• Primary side, the regulation loop of the peak current mode architecture regulates the primary voltage (blue
area in the image below)
• A two-windings transformer (in grey)
• The secondary side, which generates the isolated output voltage (in green) given the selected transformer
ratio
Figure 4. Iso-buck general schematic
5.1 Primary side

The A6986I is based on a “peak current mode”, constant frequency control. The intersection between the error
amplifier output and the sensed inductor current generates the PWM control signal to drive the power switch of
the primary side, defining so the duty-cycle and regulating the primary output voltage.
The device operates in forced PWM control (MLF pin to GND), allowing negative currents to flow in the
synchronous MOSFET, hence transferring energy to the secondary coil during the off-time.
DS13481 - Rev 2 page 9/62

A6986I
Primary side
The main internal blocks shown in the block diagram in figure below are:
Figure 5. Internal block diagram
COMP SYNC FSW VIN

SS/INH
SENSE POWER
OSCILLATOR PMOS PMOS
VREF
SS/INH 0
TSS E/A PEAK SLOPE
CL
+
FB LOOP - GND
LOOP
CONTROL
CONTROL
OVP
DRIVER
DRIVER LX
-
+
DELAY RST TH.

ZERO SENSE Vcc POWER
CROSSING NMOS NMOS
GND
RST
VALLEY
CL
DELAY MLF GND
• Embedded power elements. Thanks to the P-channel MOSFET as high-side switch the device features low-
dropout operation
• A fully integrated sawtooth oscillator with adjustable frequency
• A transconductance error amplifier
• An internal feedback divider GDIV INT
• The high-side current sense amplifier to sense the inductor current
• A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
• The soft-start blocks to ramp the error amplifier reference voltage and so decreases the inrush current at
power-up. The SS/INH pin inhibits the device when driven low
• The switchover capability of the internal regulator to supply a portion of the quiescent current when the VBIAS
pin is connected to an external output voltage
• The synchronization circuitry to manage master / slave operation and the synchronization to an external
clock
• The current limitation circuit to implement the constant current protection, sensing pulse-by-pulse high-side /
low-side switch current. In case of heavy short-circuit the current protection is fold back to decrease the
stress of the external components
• A circuit to implement the thermal protection function
• The OVP circuitry to discharge the output capacitor in case of overvoltage event
• MLF normally connected to GND through a resistor to set the threshold of the RST comparator
• FSW pin strapping sets the switching frequency
• The RST open collector output
5.1.1 Power supply and voltage reference

The internal regulator block consists of a start-up circuit, the voltage pre-regulator that provides current to all the
blocks and the bandgap voltage reference. The starter supplies the start-up current when the input voltage goes
high and the device is enabled (SS/INH pin over the inhibits threshold).
The pre-regulator block supplies the bandgap cell and the rest of the circuitry with a regulated voltage that has a
very low supply voltage noise sensitivity.
DS13481 - Rev 2 page 10/62

A6986I
Transformer
5.1.2 Switchover feature

The switchover scheme of the pre-regulator block is used to derive the main contribution of the supply current for
the internal circuitry from an external voltage (3 V < VBIAS < 5.5 V is typically connected to the primary regulated
output voltage). This helps to decrease the equivalent quiescent current seen at VIN.
5.1.3 Voltage monitor

An internal block continuously senses the VCC, VBIAS and VBG (bandgap). If the monitored voltages are good, the
regulator starts operating. There is also a hysteresis on the VCC(UVLO).
5.1.4 Error amplifier

The voltage error amplifier is the core of the loop regulation of the primary output voltage. It is a transconductance
operational amplifier whose non inverting input is connected to the internal voltage reference (0.85 V), while the
inverting input (FB) is connected to the external divider or directly to the output voltage.
Table 8. Uncompensated error amplifier characteristics
Description Value
Transconductance 155 µS
Low frequency gain 100 dB
The error amplifier output is compared with the inductor current sense information to perform PWM control.
Figure 6. Internal circuit
VCC
STARTER PREREGULATOR
VREG
BANDGAP
IC BIAS
D00IN1126 VREF
5.2 Transformer
The transformer is the key component for the iso-buck, ensuring the desired isolation as well as allowing the
energy transfer to the secondary side, hence generating the secondary isolated output voltage.
More details about the transformer selection are provided in the dedicated section (see Section 7.5.2 ).
5.3 Secondary side

The secondary side includes an LC filter (secondary winding of the transformer and secondary output capacitor)
and the rectifying element (Schottky diode).
DS13481 - Rev 2 page 11/62

A6986I
Iso-buck operation principle
5.4 Iso-buck operation principle

The image below describes the operation principle of the iso-buck converter.
When the high-side MOSFET is turned on, the current flows through the primary winding of the transformer
and charges the primary output capacitor. Considering the dot convention of the transformer, the voltage at the
anode of the Schottky diode is negative, hence the diode is reverse biased and no current flows in the secondary
winding. The load connected to the secondary output is supplied by Cout2.
When the low-side MOSFET is turned on, the voltage applied at the transformer windings inverts its polarity. As
a consequence, the Schottky diode is now forward biased and allows the current to flow from the secondary
winding to Cout and the load. Under this condition the energy transfer from primary to secondary side occurs.
Figure 7. Iso-buck basic operating principle
The waveforms in the figure below reproduce the trend of the current in the two windings according to the switch
node transitions.
DS13481 - Rev 2 page 12/62

A6986I
Soft-start and inhibit
Figure 8. Iso-buck primary and secondary current waveforms
5.5 Soft-start and inhibit

The soft-start and inhibit features are multiplexed on the same pin. An internal current source charges the
external soft-start capacitor to implement a voltage ramp on the SS/INH pin. The device is inhibited as long as the
SS/INH pin voltage is lower than the VINH threshold and the soft-start takes place when SS/INH pin crosses VSS
START. (See the figure below).
The internal current generator sources 1 µA typ. current when the voltage of the VCC pin crosses the UVLO
threshold. The current increases to 4 µA typ. as soon as the SS/INH voltage is higher than the VINH threshold.
This feature helps to decrease the current consumption in inhibit mode. An external open collector can be used to
set the inhibit operation clamping the SS/INH voltage below VINH threshold.
The start-up feature minimizes the inrush current and decreases the stress of the power components during the
power-up phase. The ramp implemented on the reference of the error amplifier has a gain three times higher
(SSGAIN) than the external ramp present at SS/INH pin.
DS13481 - Rev 2 page 13/62

A6986I
Soft-start and inhibit
Figure 9. Soft-start phase
The CSS value is chosen according to equation (1)

I ∙T 4μA∙TSS
CSS = SSGAIN∙ SSCH SS = 3∙ (1)
VFB 0.85V
where TSS is the soft-start time, ISS CH the charging current and VFB the reference of the error amplifier.
During normal operation a new soft-start cycle takes place in case of:
• Thermal shutdown event
• UVLO event
• The device is driven in INH mode
The soft-start capacitor is discharged with a 0.6 mA typ. current capability for 1 ms time max. For complete and
proper capacitor discharge in case of fault conditions, a maximum CSS = 67 nF value is suggested.
In case the soft-start should be externally driven by a voltage step (e.g. the signal from ignition switch in
automotive applications), the schematic in Figure 10 can be used.
The secondary output line regulation is defined, similarly to the primary side, as the variation of the secondary
output voltage due to the input voltage change at a specific current.
DS13481 - Rev 2 page 14/62

A6986I
Minimum on-time
Figure 10. Enable the device with external voltage step
More details about the component selection can be found in Section 7.5 .
Secondary side soft-start
As soon as the soft-start begins at the primary circuit, the device already operates in forced PWM and the
energy transfer to the secondary coil during the off-time can take place. Consequently, a tracked soft-start at the
secondary side takes place too. Therefore, the secondary output voltage reaches its steady-state value in tracking
with the primary output voltage, as shown in the figure below.
Figure 11. Tracked soft-start at secondary side
5.6 Minimum on-time

The current sense in the high-side MOSFET is not active (masked) for a certain time at the beginning of the
on-time (masking time, from which the parameter TON MIN derives).
This current sense blanking time is implemented to prevent any primary side pulsed current at the high-side
turn-on (resonating with transformer drive leakage inductance and secondary side capacitance) overcoming the
EA programmed switch current for the conversion and making conversion unstable (depicted in Figure 12 and
Figure 13).
DS13481 - Rev 2 page 15/62

A6986I
Minimum on-time
Figure 12. Simulation with insufficient masking time (< 100 ns)
Figure 13. Simulation with appropriate masking time (330 ns)
Despite the masking time, an RC snubber circuit is normally recommended to dampen the oscillations. The figure
below shows a typical application where the appropriate masking time is implemented as well as an RC snubber
circuit.
Figure 14. Remaining oscillations filtered by the masking time and RC snubber circuit VIN = 12 V, N = 1.58,
IOUTiso = 100 mA
DS13481 - Rev 2 page 16/62

A6986I
Output voltage line regulation
5.7 Output voltage line regulation

All results shown in this section come from measurements performed using the reference schematic depicted in
Figure 14.
Figure 15. Schematic used for line and load regulation tests
Primary output line regulation

The regulator features an enhanced primary line regulation due to the peak current mode architecture. Figure 15
shows negligible output voltage variation (normalized to the value measured at VIN = 12 V) over an input voltage
range up to 24 V for A6986I with VOUT prim = 5.3 V.
Figure 16. Primary line regulation
0.0%
Iout_prim = 0A
Iout_prim = 1A
-0.1%
-0.2%
ΔVOUT_prim [V]
-0.3%
-0.4%
-0.5%
12 13 14 15 16 17 18 19 20 21 22 23 24
VIN [V]
DS13481 - Rev 2 page 17/62

A6986I
Output voltage line regulation
Secondary output line regulation

The secondary output line regulation is defined, similarly to the primary side, as the variation of the secondary
output voltage due to the input voltage change at a specific current. The secondary output line regulation is mainly
affected by the transformer and in particular by its leakage inductance.
Keeping constant the leakage inductance (i.e. using the same transformer), a higher input voltage allows to
slightly increase the isolated output voltage, as shown in Figure 16.
Figure 17. Secondary output line regulation
6%
5%
4%
ΔVOUT_sec [V]
3%
2%
1%
0%
12 13 14 15 16 17 18 19 20 21 22 23 24
VIN [V]
The input voltage value influences the peak current in the secondary winding (see Figure 17), hence determining
the amount of energy delivered to the secondary output and in turn the isolated output voltage value.
Figure 18. Secondary winding current at different input voltages
DS13481 - Rev 2 page 18/62

A6986I
Output voltage load regulation
5.8 Output voltage load regulation

Primary output load regulation
Figure 18 shows negligible primary output voltage variation (normalized to the value measured at IOUT = 0 A) over
the entire output current range for the A6986I with VOUT = 5.3 V.
Figure 19. Load regulation of the non isolated output
0.6%
0.5%
0.4%
0.3%
0.2%
0.1%
ΔVOUT_prim [%]
0.0%
-0.1%
-0.2%
-0.3%
-0.4%
-0.5%
-0.6%
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
IOUT_prim [A]
Secondary output load regulation

Since there is not a regulation loop involving the secondary output, its load regulation depends to some extent
on the primary load regulation and is affected by the leakage inductance (see Figure 19) of the transformer,
the voltage drops across to the Schottky diode (diode forward voltage) and the DCR of the secondary coil, as
indicated by equation (1) (where only the last two contributions are considered). Minimizing all the mentioned
parameters leads to a better load regulation.
Figure 20. Effect of the transformer leakage inductance on the isolated output load regulation
15%
Lleak = 240nH
Lleak = 700nH
10%
5%
ΔVOUT_sec %
0%
-5%
-10%
-15%
10 20 30 40 50 60 70 80 90 100
IOUT [mA]
DS13481 - Rev 2 page 19/62

A6986I
Overcurrent protection
As shown in Section 5.7, the input voltage also plays a role in the isolated output regulation. Figure 20 further
proves the slight dependency of the isolated output voltage on the input voltage.
Figure 21. Input voltage effect on the load regulation of the isolated voltage
20%
VIN = 12V
15% VIN = 18V
VIN = 24V
10%
5%
ΔVOUT_sec %
0%
-5%
-10%
-15%
-20%
10 20 30 40 50 60 70 80 90 100
IOUT [mA]
5.9 Overcurrent protection

Protection against overcurrent conditions and/or short-circuit at the output is ensured at both primary and
secondary side of the iso-buck converter.
Overcurrent protection at the primary side
The current protection circuitry features a constant current protection, so the device limits the maximum peak
current (see Section 3 ) in overcurrent condition.
The A6986I device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side
switches), ensuring an effective current protection over the duty cycle range. The high-side current sensing is
called “peak” the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a
minimum conduction time of the power element. This time is called “masking time” because the information
from the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event.
Consequently, the peak current protection is disabled for a masking time after the high-side switch is turned on,
the valley for a masking time after the low-side switch is turned on. In other words, the peak current protection can
be ineffective at extremely low duty cycles, the valley current protection at extremely high duty cycles.
Summarizing, in case one of the two current sensing circuitries is ineffective because of the masking time, the
device is protected sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley”
current limits assures the effectiveness of the overcurrent protection even in extreme duty cycle conditions.
The valley current threshold is designed higher than the peak to guarantee a proper operation. In case the current
diverges because of the high-side masking time, the low-side power element is turned on until the switch current
level drops below the valley current sense threshold. Under this condition the device can skip some cycle, leading
to a switching frequency reduction. The figure below shows an example of valley current limit intervention in a
short-circuit event (switching frequency set to 500 kHz, actual switching frequency 250 kHz).
DS13481 - Rev 2 page 20/62

A6986I
Overcurrent protection
Figure 22. Valley current sense operation in short-circuit
Figure 22 shows the switching frequency reduction during the valley current sense operation in case of extremely
low duty cycle (VIN = 24 V, fSW = 500 kHz short-circuit condition).
In a worst case scenario (like Figure 22) of the overcurrent protection the switch current is limited to:
V ‐V
IMAX= IVALLEYTH+ IN L OUT ∙TMASKHS (2)
where IVALLEY_TH is the current threshold of the valley sensing circuitry (see Table 1) and TMASK_HS is the
masking time of the high-side switch (330 ns typ.).
In most of the overcurrent conditions the conduction time of the high-side switch is higher than the masking time
and so the peak current protection limits the switch current.
IMAX = IPEAK_TH (3)
Figure 23. Peak current sense operation in overcurrent condition
Figure 23 shows the effect of the peak current protection. On the left the current (blue waveform) during the
on-time reaches the peak current protection threshold. From this point on, any increase of the output current
causes the on-time to be reduced (image on the right) so that the current provided to the output is limited. As a
consequence, the output voltage drops, as the purple waveform depicts.
The DC current flowing in the load in overcurrent condition is:
V ‐V
IDCOC (VOUT) = IMAX‐ IN2LOUT ∙TON (4)
DS13481 - Rev 2 page 21/62

A6986I
Overvoltage protection
Overcurrent protection at the secondary side

The increase of the secondary output current affects the current shape at primary side. In particular, the peak
currents in the high-side and low-side MOSFETs rise (in absolute value in the low-side, i.e. the current becomes
more negative), in accordance with equations (5) and (6)).
∆IL
IPEAK =I +N∙IOUT_sec+ 2 (5)
HS OUT_pri
2D ∆IL
IPEAK = − N∙IOUT_sec∙ 1 − D − 2 + IOUT_prim (6)
LS
where IOUT_pri and IOUT_sec are respectively the primary and secondary output currents, N is the transformer turn
ratio, D the duty cycle and ΔIL the current ripple in the primary winding.
Figure 23 depicts how these peak currents vary depending on the secondary output current, under the specified
conditions.
Normally the negative current during the off-time is more critical and the secondary output is limited by relying on
the reverse current limit (typ. 1.9 A), as shown in the figure below.
A current drawn from the primary output helps to reduce the peak current in the low-side MOSFET [as shown by
equation (6)], hence allowing a higher current from the secondary output. Nevertheless, attention must be paid to
the IPEAKHS [equation (5)] that must be lower than the peak current limit.
Figure 24. Peak currents depending on the secondary output current (VIN = 12 V, VOUT_pri = 5.3, N = 6, fSW
= 500 kHz, no primary output current)
2.4
reverse current
limit (typ.) exceeded
2
1.6
Peak currents [A]
IPEAK HS
1.2
| I PEAK LS |
0.8
0.4
0
0 50 100 150 200
Secondary output current [mA]
Reverse current limit

As mentioned in the previous section, the low-side MOSFET is protected against negative currents. This feature
limits the negative current in the MOSFETs especially during two events:
- Overvoltage at the primary output. Due to an overvoltage event the low-side MOSFET is kept on to discharge
the primary output.
- Overcurrent or short-circuit event at the secondary output, as described in the previous section.
5.10 Overvoltage protection

The overvoltage protection monitors the VFB pin and enables the low-side MOSFET to discharge the output
capacitor if the output voltage is 20% over the nominal value.
DS13481 - Rev 2 page 22/62

A6986I
Thermal shutdown
This is a second level protection and should never be triggered in normal operating conditions if the system
is properly dimensioned. In other words, the selection of the external power components and the dynamic
performance determined by the compensation network should guarantee an output voltage regulation within the
overvoltage threshold even during the worst-case scenario in terms of load transitions.
Figure 25 shows the overvoltage operation during a negative steep load transient and designed with a not
optimized compensation network. This can be considered as an example for a system with dynamic performance
not in line with the load request.
The A6986I device implements a 1.9 A typ. negative current limitation to limit the maximum reversed switch
current during the overvoltage operation.
Moreover, the overvoltage protection also activates the internal pull-down on the RST pin. Once OVP is
deactivated, the A6986I releases the RST (Figure 25). The release of the RST pin can be delayed by connecting
a capacitor to the DELAY pin (pin 9). For the selection of the capacitance value, equation (28) can be used.
Figure 25. Overvoltage operation
5.11 Thermal shutdown

The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal
threshold (165°C typical). The thermal sensing element is close to the power elements, ensuring fast and
accurate temperature detection. A hysteresis of approximately 30°C prevents the device from turning ON and
OFF continuously. When the thermal protection runs away a new soft-start cycle takes place.
DS13481 - Rev 2 page 23/62

A6986I
Closing the loop
6 Closing the loop
The iso-buck, compared to a standard buck, includes the transformer in place of the inductor and all the
components connected to the secondary winding (at least the Schottky diode and the secondary output
capacitor). Nevertheless, the regulation loop does not include the secondary side components. As a first
approximation the control loop of an iso-buck can be assimilated to the one of a standard buck. Therefore,
the block diagram in the figure below can still be used (where the inductor symbol identifies the inductance of the
primary winding) as well as all the equations and calculations in the following sections.
Figure 26. Block diagram of the loop
6.1 GCO(s) control to output transfer function

The accurate control to output transfer function for a buck peak current mode converter can be written as:
1+ ωs
1 Z
GCO(s)= RLOAD∙gCS∙ ∙ s ∙FH(s (7)
RLOAD∙TSW
1+ ∙ mC∙ 1‐D ‐0.5 1+ ωp
L
where RLOAD represents the load resistance, gCS the equivalent sensing transconductance of the current sense
circuitry, wp the single pole introduced by the power stage and wz the zero given by the ESR of the output
capacitor.
FH(s) accounts for the sampling effect performed by the PWM comparator on the output of the error amplifier that
introduces a double pole at one half of the switching frequency.
1
ωZ= ESR∙C (8)
OUT
1 m ∙ 1‐D ‐0.5
ωp= R ∙ C (9)
LOAD∙COUT L∙COUT∙f SW
where:
S
mC=1+ S e
n
Se=VPP∙gCS∙f SW (10)
VIN − VOUT
Sn= L
DS13481 - Rev 2 page 24/62

A6986I
Error amplifier compensation network
Sn represents the on-time slope of the sensed inductor current, Se the on-time slope of the external ramp (VPP
peak-to-peak amplitude) that implements the slope compensation to avoid sub-harmonic oscillations at duty cycle
over 50%.
Se can be calculated from the parameter VPP × gCS given in Section 3 .
The sampling effect contribution FH(s) is:
1
FH s = (11)
s
1+
s2
ωn∙Qp + 2
ωn
where
ωn=π∙f SW
1 (12)
Qp=
π∙mC∙ 1−D − 0.5
6.2 Error amplifier compensation network

The typical compensation network required to stabilize the system is shown in the figure below:
Figure 27. Transconductance embedded error amplifier
RC and CC introduce a pole and a zero in the open loop gain. CP does not significantly affect system stability but it
is useful to reduce the noise at the output of the error amplifier.
The transfer function of the error amplifier and its compensation network is:
AV0∙ 1+s∙RC∙CC
A0 s = 2 (13)
s ∙R0∙ C0+Cp ∙RC∙CC+s∙ R0∙CC+R0∙ C0+Cp +RC∙CC +1
where AV0=Gm∙R0.
The poles of this transfer function are (if CC >> C0 + CP)
f PHF= 2∙π∙R1 ∙C (14)

0 C
DS13481 - Rev 2 page 25/62

A6986I
Voltage divider
whereas the zero is defined as:

1
f PHF= (15)
2∙π∙R0∙ C0+Cp
6.3 Voltage divider

The contribution of the internal voltage divider for fixed output voltage devices is:
R2 VFB
GDIV(s)=
R1+R2 = VOUT (16)
A small signal capacitor in parallel to the upper resistor (see figure below) of the voltage divider implements a
leading network (fzero < fpole), sometimes necessary to improve the system phase margin:
Figure 28. Leading network example
The Laplace transformer of the leading network is:
1+ s
R2 fZ
GDIV(s)= R +R ∙ (17)
1 2 1+ s
fP
where
f Z= 2∙π∙R1 ∙C (18)
1 R1
1
f P= R ∙R
2∙π∙ R 1+R2 ∙CR1
1 2
fZ < fP
6.4 Total loop gain

In summary, the open loop gain can be expressed as:
G (s)= GDIV(s)∙GC0(s)∙A0(s) (19)
DS13481 - Rev 2 page 26/62

A6986I
Compensation network design
6.5 Compensation network design

The maximum bandwidth of the system can be designed up to fSW/6, up to 150 kHz maximum to guarantee a
valid small signal model
2∙π∙BW∙COUT∙VOUT
RC= (20)
0.85V∙gCS∙gm_typ
where:
ωP
f POLE= 2∙π (21)
ωP is defined by eq. (9) , gCS represents the current sense transconductance (see Section 3 ) and gm TYP the
error amplifier transconductance.
CC= 2∙π∙R5 ∙ BW (22)

C
Example 1:
VIN = 12 V, VOUT_pri = 5.3 V, ROUT_pri = 5.6 Ω (corresponding to almost 1 A load).
Selecting the A6986I with VOUT_pri = 5.3 V, fSW = 500 kHz, Lpri = 18 µH, COUT_pri = 10 µF and ESR = 3 mΩ,
RC = 56 kΩ, CC = 680 pF, CP = 4.7 pF (please refer to Table 11), the gain and phase bode diagrams are plotted
respectively in Figure 29 and Figure 30. Bode plot (phase).
Figure 29. Bode plote (magnitude)
DS13481 - Rev 2 page 27/62

A6986I
Compensation network design
Figure 30. Bode plot (phase)
The blue solid trace represents the transfer function including the sampling effect term (see equation (11)), the
dotted blue trace neglects the contribution.
Considering this example, bandwidth and phase margin are:
BW ≈ 50 kHz
Phase Margin → between 53° and 70°
DS13481 - Rev 2 page 28/62

A6986I
Application notes
7 Application notes
7.1 Output voltage adjustment

Primary output voltage
The error amplifier reference voltage is 0.85 V typical. The output voltage is adjusted accordingly to the equation
below:
R
VOUT_pri= 0.85∙ 1+ 1 (23)
R2
where R1 and R2 are the resistors used in the output divider (see figure below).
Figure 31. A6986I application circuit
The integration of a P-channel MOSFET as high-side switch theoretically allows duty cycle up to 100%.
Nevertheless, in an iso-buck architecture some restrictions should be considered. A general recommendation
is to keep the duty-cycle below 50-60%. A higher duty cycle would limit off-time, limiting the time in which the
energy transfer to the secondary side takes place.
Other restrictions in the duty cycle selection arise due to the minimum on-time (see Section 7.2 Switching
frequency), generally summarized by the following equation:
D ≥ DMIN = TON MIN∙f SW (24)
Secondary output voltage

In the iso-buck converter, the secondary output voltage is not included in the regulation loop. Nevertheless, a
good regulation of the secondary output voltage is achieved by relying on the primary output voltage regulation,
the selection of a proper turn ratio of the transformer as well as considering the voltage drops due to the
secondary winding resistance and the Schottky diode. That can be summarized by the following equation:
VOUT_sec=N∙ VOUT_pri+IOUT ∙ RDS on LS+Rwind_pri ‐Rwind_sec∙IOUT_sec‐VFD1 (25)

pri
where N is the turn ratio, Rwind_prim and Rwind_sec are the winding resistances of the primary and secondary side
respectively and VFD1 is the forward voltage of the Schottky diode.
If no current is drawn from the primary output, equation (25) can be simplified as follows:
VOUT_sec=N∙VOUT − Rwind_sec∙IOUT_sec − VFD1 (26)
pri
DS13481 - Rev 2 page 29/62

A6986I
Switching frequency
Equation (26) emphasizes how the selection of the transformer and, to some extent, the Schottky diode plays a
crucial role in the accurate regulation of the secondary output voltage. The figure below shows instead the effect
of the current drawn from the primary output on the isolated voltage, as described by equation (9).
Figure 32. Isolated voltage variation due to the primary output current
10%
9%
8%
7%
6%
%
5%
ΔV OUT_sec
4%
3%
2%
1%
0%
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
IOUT_pri [mA]
Another factor affecting the secondary output voltage regulation comes from the leakage inductance of the
transformer. As described later on, the leakage inductance determines the peak current that can be reached in
the secondary winding. This peak current defines the maximum current from the secondary isolated output by
limiting the amount of charge delivered to the output. When the current demand from the secondary isolated
output exceeds the maximum deliverable charge limited by the peak current, the isolated output voltage drops.
Figure 33. Secondary output maximum current
To some extent also the duty cycle can affect the secondary output voltage. Since the energy transfer from
primary to secondary occurs only during the TOFF, a too high duty cycle could reduce the achievable peak
current, hence limiting the deliverable current to the secondary output. Under this condition the secondary output
could drop.
7.2 Switching frequency

A resistor connected to the FSW pin features the selection of the switching frequency. The pinstrapping is
performed at power-up, before the soft-start takes place. The FSW pin is pinstrapped and then driven floating in
order to minimize the quiescent current from VIN. Please refer to Table 6 to identify the pull-up / pull-down resistor
value.
Setting fSW = 250 kHz or fSW = 500 kHz does not require any external resistor.
The selection of the switching frequency must take into account the minimum on-time of the device (TON MIN, as
indicated in the electrical characteristics table), as described by the following equation.
VOUT
f SW_max≤ (27)
TON MIN∙VIN∙η
The switching frequency affects the selection of the primary inductance as well as the transformer construction.
DS13481 - Rev 2 page 30/62

A6986I
Voltage supervisor
7.3 Voltage supervisor

The embedded voltage supervisor (composed of the RST and the DELAY pins) monitors the regulated output
voltage and keeps the RST open collector output in low impedance as long as the VOUT is out of regulation (i.e.
lower than 93% of the target output voltage). In order to ensure a proper reset of digital devices with a valid power
supply, the device can delay the RST assertion with a programmable time.
Figure 34. Voltage supervisor operation
When the RST comparator detects the output voltage is in regulation, a 2 mA internal current source starts to
charge an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then
released as soon as VDELAY = 1.234 V (see Figure 34). The CDELAY is dimensioned as follows.
I ∙T 2μA∙TDELAY
CDELAY= SSCH DELAY = (28)
VDELAY 1.234V
The maximum suggested capacitor value is 270 nF.

The A6986I also activates internal pull-down on the RST pin in case overvoltage protection is triggered. As soon
as the output voltage goes below the OVP threshold (20% typ.), the 2 µA internal current source starts to charge
an external capacitor to implement a voltage ramp on the DELAY pin. The RST open collector is then released as
soon as VDELAY = 1.234 V (see figure below).
Figure 35. Voltage supervisor operation during OVP
DS13481 - Rev 2 page 31/62

A6986I
Synchronization
7.4 Synchronization
The synchronization feature helps the hardware designer to prevent beating frequency noise that is an issue
when multiple switching regulators populate the same application board.
7.4.1 Embedded master - slave synchronization

The A6986I synchronization circuitry features the same switching frequency for a set of regulators simply
connecting their SYNCH pin together, so preventing beating noise. The master device provides the
synchronization signal to the others since the SYNCH pin is I/O able to deliver or recognize a frequency signal.
For proper synchronization of multiple regulators, all of them have to be configured with the same switching
frequency (see Table 6), so the same resistor connected at the FSW pin.
In order to minimize the RMS current flowing through the input filter, the A6986I device provides a phase shift of
180° between the master and the slaves. If more than two devices are synchronized, all slaves have a common
180° phase shift with respect to the master.
Considering two synchronized A6986Is which regulate the same output voltage (i.e.: operating with the same duty
cycle), the input filter RMS current is optimized and is calculated as:
IOUT
2 ∙
2D ∙ 1 − 2D if D < 0.5
IRMS (29)
IOUT
2 ∙ 2D − 1 ∙ 2 − 2D if D > 0.5
The graphical representation of the input RMS current of the input filter in the case of two devices with 0°
phase shift (synchronized to an external signal) or 180° phase shift (synchronized connecting their SYNCH pins)
regulating the same output voltage is provided in the figure below. To dimension the proper input capacitor please
refer to the dedicated section (Section 7.5.1 Input capacitor selection).
Figure 36. Input RMS current
The figure below shows two not synchronized regulators with unconnected SYNCH pin.
DS13481 - Rev 2 page 32/62

A6986I
Synchronization
Figure 37. Two regulators not synchronized
The figure below shows the same regulators working synchronized having the SYNCH pins connected. The
MASTER regulator (LX_reg2 trace) delivers the synchronization signal to the slave device (LX_reg1). The SLAVE
regulator works in phase with the synchronization signal, which is out of phase with the master switching
operation.
Figure 38. Two regulators not synchronized
7.4.2 External synchronization signal

Multiple A6986I can be synchronized to an external frequency signal fed to the SYNCH pin. In this case the
regulator set is phased to the reference and all the devices work with 0° phase shift.
Considering that the minimum synchronization pulse width coincides with the TON MIN (typ. 340 ns), it is
recommended to synchronize with a frequency not higher than 1 MHz.
Since the internal slope compensation contribution that is required to prevent subharmonic oscillations in peak
current mode architecture depends on the oscillator frequency, it is important to select the same oscillator
frequency for all regulators (all of them operate as slave) as close as possible to the frequency of the reference
signal (please refer to Table 6). As a consequence, all the regulators have the same resistor value connected
to the FSW pin, so the slope compensation is optimized accordingly with the frequency of the synchronization
signal. The slope compensation contribution is latched at power-up and so fixed during the device operation.
DS13481 - Rev 2 page 33/62

A6986I
Synchronization
The A6986I normally operates in MASTER mode, driving the SYNCH line at the selected oscillator frequency as
shown in Figure 39 and Figure 37.
In SLAVE mode the A6986I sets the internal oscillator at 250 kHz typ. (see Table 6) and drives the line
accordingly.
Figure 39. A6986I synchronization driving capability
In order to safely guarantee that each regulator recognizes itself in SLAVE mode when synchronized, the external
master must drive the SYNCH pin with a clock signal frequency higher than the maximum oscillator spread of the
selected line in Table 6 for at least 10 internal clock cycles.
Example 1: selecting RFSW = 0 Ω to VCC
Table 9. Example of oscillator frequency selection
Symbol RVCC (E24 series RGND (E24 series) fSW min. fSW typ. fSW max.
fSW NC 0Ω 225 250 275
The device enters in SLAVE mode after 10 pulses at frequency higher than 275 kHz.
As anticipated above, in SLAVE mode the internal oscillator operates at 250 kHz typ. but the slope compensation
is dimensioned accordingly with FSW resistors so it is important to limit the switching operation around a working
point close to the selected oscillator frequency (FSW resistor).
As a consequence, to guarantee the full output current capability and to prevent the subharmonic oscillations, the
master may limit the driving frequency range within ± 5% of the selected frequency.
A wider frequency range may generate subharmonic oscillation for duty > 50% or limit the peak current capability
(see IPK parameter in Section 3 ) since the internal slope compensation signal may be saturated.
The device keeps operating in SLAVE mode as far as the master is able to drive the SYNCH pin faster than 275
kHz, otherwise the A6986I goes back into MASTER mode at the programmed RFSW oscillator frequency after
successfully driving one pulse 250 kHz typ. (see Figure 40) in the SYNCH line.
DS13481 - Rev 2 page 34/62

A6986I
Synchronization
Figure 40. Slave-to-master mode transition
The external master can force a latched SLAVE mode driving the SYNCH pin low at power-up, before the
soft-start begins the switching activity. So the oscillator frequency is 250 kHz typ. fixed until a new UVLO event
is triggered regardless of FSW resistor value, that otherwise counts to design the slope compensation. The same
considerations above are also valid.
The master driving capability must be able to provide the proper signal levels at the SYNCH pin (see Section 3 ):
• Low level < VSYN THL = 0.7 V sinking 5 mA
• High level > VSYN THH = 1.2 V sourcing 0.7 mA
Figure 41. Master driving capability to synchronize the A6986I
DS13481 - Rev 2 page 35/62

A6986I
Design of the external components
7.5 Design of the external components
7.5.1 Input capacitor selection

The input capacitor, just like in a standard buck, should limit the input voltage ripple. Key parameters of the input
capacitor are, together with its value, the maximum operating voltage and the RMS current capability.
The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
During the switching activity a pulsed current flows into the input capacitor and so its RMS current capability must
be selected according to the application conditions. Internal losses of the input filter depend on the ESR value
so usually low ESR capacitors (like multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, a lower ESR input filter has lower losses and so contributes to higher
conversion efficiency.
The maximum RMS input current flowing through the capacitor can be calculated as:
I
IRMS= IOUT_pri+ OUT_sec 1‐ D D
∙ η ∙η
(30)
N
In the ideal case of efficiency η = 1, the RMS current reaches its maximum value when D = 0.5.
In general, the maximum and minimum duty cycles can be calculated as:
VOUT_pri+ΔVLS
DMAX= (31)
VINmin+ΔVLS − ΔVHS
VOUT_pri + ΔVLS
DMIN= (32)
VINmax+ΔVLS − ΔVHS
where ΔVHS and ΔVLS are the voltage drop across the high-side and low-side MOSFETs respectively.
The AC component of the input current (see Figure 41) flows in the input capacitor, generating the input voltage
ripple.
Figure 42. Input capacitor AC current
The peak-to-peak voltage across the input capacitor can be calculated as follows:
N
IOUT_pri+IOUT_sec∙ Nsec
pri D ∆IL
VPP= ∙ η ∙ 1− D
η +ESR∙ IOUT_pri+IOUT_sec+ 2
(33)
CIN∙f SW
In the case of negligible ESR (e.g. in case of MLCC capacitors) equation (33) can be simplified. The value of the
input capacitor can be then derived:
N
pri D D
CIN = ∙ η ∙ 1− η (34)
VPP∙f SW
Considering the ideal case of η = 1, the equation above reaches its maximum value when D = 0.5. Therefore, the
minimum input capacitance value can be defined as follows:
DS13481 - Rev 2 page 36/62

A6986I
N
pri
CIN≥CINmin = ∙ (35)
4∙VPP∙f SW
Typically, CIN is dimensioned to keep the maximum peak-to-peak voltage across the input filter in the order of 5%
of VINmax.
DS13481 - Rev 2 page 37/62

A6986I
7.5.2 Transformer selection

The transformer has two essential tasks:
• Providing the isolation between primary and secondary side in accordance with the application requirements
• Generating the necessary secondary output voltage from the regulated primary voltage with the most
suitable turn ratio
The transformer selection implies defining the following parameters:
• Isolation voltage
• Turn ratio
• Primary inductance
• Peak and RMS currents
• Windings resistance
• Leakage inductance
• Parasitic capacitances
Isolation voltage
The isolation of the transformer in terms of voltage capability (1.5 kV, 4 kV, and so on) and type (functional basic,
reinforced, etc.) is mainly driven by the application. Both parameters normally affect the size of the transformer as
well as other electrical characteristics (e.g. winding resistance, leakage inductance, etc.).
Turn Ratio
Naming Npri and Nsec the number of turns of the primary and secondary windings respectively, the turn ratio is so
defined:
Npri
N= (36)
Nsec
Considering equation (25), the turn ratio must be defined so that the voltage at the secondary output is the
desired one over the whole secondary output current range:
VOUT_sec+ Rwind_sec∙IOUT_sec + VFD1
N≥ (37)
VOUT_pri+IOUT ∙ RDS on LS+Rwind_pri
pri
If no current is drawn from the primary output, the turn ratio should be only chosen to compensate the drops due
to the secondary winding resistance and the Schottky diode.
The effect of the leakage inductance on the secondary output voltage regulation (not included in the equation
above) should be taken into account too. Figure 17 clearly shows how the secondary output voltage can drift due
to the leakage inductance.
Primary inductance
The choice of the primary inductance does not differ so much from a standard buck. The magnetizing current,
(see figure below) which combines the two winding currents, has the same shape of the buck inductor current and
can be defined as:
IL_mag = Ipri+N∙Isec (38)
DS13481 - Rev 2 page 38/62

A6986I
Figure 43. Primary (blue) winding current, secondary (pink) winding current and magnetizing current
(black)
ILpri_pos_peak
ILpri
ILpri_neg_peak
ILsec_peak
ILsec
LX
Therefore, setting the current ripple ΔIL, the inductance is so defined:
VIN − VOUT_pri ∙VOUT_pri

Lpri = (39)
VIN∙f SW∙∆IL
For example, assuming IOUT_prim = 500 mA, IOUT_sec = 100 mA, N= 5, the current ripple can be set around 30%
of the total current IOUT_pri + N×IOUT_sec = 1A, therefore 300 mA. If VIN = 12 V, VOUT_pri = 5 V and fSW = 500 kHz,
the inductor value should be 19.4 µH (and 18 µH or 22 µH the closest standardized value).
Peak and RMS current
As any inductor, peak and RMS current for each winding must be calculated in order to define saturation and
RMS currents that the transformer should fulfill.
For the primary winding, the equations below are valid:
I ΔIpri
Ipri_pos_peak = IOUT_pri+ OUT_sec + 2 (40)
N
I ΔIpri∙N
Ipri_RMS = IOUT_pri+ OUT_sec ∙ 1+ 12
1∙
N N∙IOUT_pri+IOUT_sec (41)
For the secondary winding the peak current can change depending on the leakage inductance. In the image
below secondary winding current waveforms with different leakage inductances are simulated. It is evident
how the peak current can significantly vary. Considering the target leakage inductance value for an iso-buck
(recommended up to 1% of the primary inductance), the waveform can be approximated with a sawtooth shape
and the peak and RMS currents can be hence estimated as:
2∙IOUT_sec
Isec_pos_peak = (42)
1−D
Isec_RMS = Isec_pos_peak∙ 1−D (43)

3
A duty cycle higher than 50-60% significantly increases the peak current in the secondary winding. Furthermore,
this affects the negative peak current at the primary side (see Figure 44).
DS13481 - Rev 2 page 39/62

A6986I
Figure 44. Secondary winding positive peak current dependency on duty cycle (IOUT_sec = 100 mA)
2.5
Secondary positive peak current [A]
1.5
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Duty cycle
Figure 45. Primary negative peak current dependency on duty cycle (VOUT_pri = 5 V, IOUT_pri = 0, IOUT_sec =
100 mA, N = 6, fSW = 500 kHz, L = 19 µH)
5
4.5
|Primary negative peak current| [A]
4
3.5
3 typ. reverse current
limit threhsold
2.5
2
1.5 Reverse current
1 limit already
triggered
0.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
Duty cycle
Windings resistance
Winding resistances should be minimized as much as possible since they affect the secondary output load
regulations. They also contribute to power losses, therefore affecting the efficiency of the total solution.
Leakage inductance
The leakage inductance of a transformer can be defined as an undesired inductive component due to the not
perfect magnetic linking of the two windings. Leakage inductance is inherent to the transformer construction and
can only be reduced but not eliminated.
DS13481 - Rev 2 page 40/62

A6986I
As shown in Figure 45 (resulting from a simulation), the leakage inductance affects the shape of the secondary
winding current. In general, a very low leakage inductance implies that the current in the secondary winding can
quickly ramp up, allowing the charge of the secondary output capacitor and supporting the load current demand.
A high leakage inductance slows down the secondary winding current rise, limiting the charge delivery to the
output. Comparing solutions with different values of transformer leakage inductance shows that higher leakage
inductance transformers are characterized by poorer load regulation performances.
In addition, higher leakage inductance means a reduction of the effective current slope in the primary winding,
therefore increasing the duty cycle. As a consequence, the Schottky diode conduction time shortens, and higher
peak and RMS current are present at the secondary winding. Higher peaks at light load negatively impact the load
regulation.
Figure 46. Secondary winding current according to different leakage inductances (simulation)
LLEAKAGE = 200nH
LLEAKAGE = 50nH
LLEAKAGE = 2µH
Another effect of the leakage inductance is the ringing observed when the transition from the off-phase to
on-phase occurs. These oscillations are due to the LC circuit represented by the leakage inductance and the total
parasitic capacitance observed by the primary winding. This capacitance consists of several contributions:
• Primary winding capacitance
• Secondary winding capacitance, reflected in the primary side LLEAKAGE = 2µH
• Reverse capacitance of the Schottky diode, reflected in the primary side
The ringing at primary side could affect the regulation loop and falsely trigger the internal comparator, turning off
the high-side MOSFET, although it should be kept on. This might result in undesired jitter at switch node.
A proper masking time (TON MIN) filters these oscillations, which otherwise can affect the loop on the primary side.
Nevertheless, a snubber circuit to dump this ringing is always recommended, as shown in the figure below.
Figure 47. Snubber circuit
Capacitance
DS13481 - Rev 2 page 41/62

A6986I
The parasitic capacitance of a real transformer mainly consists of the following contributions:
• Capacitance across each winding (CP and CS, in the image below) due to the capacitve coupling between
the coil and the core. As already mentioned, the winding capacitances are involved in the ringing observed
during transition from the off- to on-phase of the primary side
• Interwinding capacitance (CWW), which is the capacitance between windings. The interwinding capacitance
should be reduced in order to limit disturbance on the primary side due to possible steep voltage transitions
present in the load connected to the secondary output.
Figure 48. Transformer parasitic capacitances
CWW
CP CS
7.5.3 Schottky diode

The selection of the Schottky diode should consider the following parameters:
• Maximum forward current, mainly defined by the secondary output current demand (see equation (43));
• Forward voltage drop, which affects the secondary output voltage regulation
• Maximum peak reverse voltage. During the on-phase of the primary side, when in the secondary side no
current flows, the diode is reverse biased and must withstand this voltage:
VD1_rev = N∙ VINmax − VOUT_pri +VOUT_sec (44)
• Junction capacitance, which should be as low as possible in order to reduce the ringing described in the
previous section
7.5.4 Output capacitors selection

Primary output capacitor
As in a standard buck converter, the primary output capacitor is involved in:
• Determining the output voltage ripple
• Supporting load transient
• The loop stability, by setting one pole and one zero in the transfer function
Considering the ouput voltage ripple requirement, the primary output capacitance should be selected according to
the following equation:
ΔIpri
COUT_pri= (45)
8∙f SW∙ ΔVOUT_pri − ESR∙ΔIpri
Normally, MLCC capacitors are the best choice for the output capacitor, therefore the ESR contribution is
negligible and equation (46) can be simplified.
Secondary output capacitor
The secondary output capacitor supplies the secondary output load current during the tON (when diode D1 is
reverse biased) and its value defines the secondary output voltage ripple (ΔVOUT).
I ∙D
COUT_sec= OUT_sec (46)
ΔVOUT_sec∙f SW
DS13481 - Rev 2 page 42/62

A6986I
Application example
8 Application example
The target of this section is to show a typical application example as well as to describe the expected
performances.
The schematic below depicts a typical application where an isolated voltage (single) together with a not isolated
voltage is required.
Figure 49. Typical schematic with load applied to both the isolated and not isolated outputs
This application generates 5 V at the primary output (not isolated) with a switching frequency of 500 kHz. The
secondary voltage (isolated) is generated by a transformer with a 1:5.8 turn ratio. The voltage between VOUT_sec+
and VOUT_sec- changes with the current drawn from the load. A post-regulation is necessary to keep this voltage
stable.
Maximum deliverable current in an iso-buck topology must take into account equations (5) and (6). According to
how much current is drawn from the isolated and not isolated outputs, IPEAKHS or IPEAKLS is the most stringent
parameter.
DS13481 - Rev 2 page 43/62

A6986I
Application example
Considering the schematic above and the components included, the graph below gives an idea about how much
current, under these application conditions, can be drawn at the same time from the not isolated and isolated
outputs, with different input voltages.
Figure 50. Maximum deliverable currents to the isolated and not isolated outputs
0.5
VIN = 9 V
0.45 VIN = 12 V
VIN = 18 V
0.4 VIN = 24 V
0.35
0.3
IOUT_sec [A]
0.25
0.2
0.15
0.1
0.05
0
1 10 100 1000
IOUT_prim [mA]
DS13481 - Rev 2 page 44/62

A6986I
Application board
9 Application board
The reference evaluation board schematic is shown in the figure below.
Figure 51. STEVAL-A6986IV1 evaluation board schematic
optional circuitry
for improved load regulation
EMI FIlter
TP12
R16 VOUT2 Q1 VISO+ TP8 VISO+
R11
R8 C15
4 1 U1
U2
L4 L3 SYNCH RST D1 C21 R12
13 1 8 2 1
TP5 15 LX 14 1 8
VIN VIN LX 2 7 U3
2 2 7
C20 C19 VCC 3 6
C18 R18 3 6 C13
5 R13
FSW 16 GND1 4 5
6 VBIAS 4 5 C17
TP4 R1
MLF 9
GNDpri 3 FB
SS/INH TP6 GNDisoTP9
7 GNDiso
8 COMP VOUT1
R17 DELAY C5
C4 D3
C8
C9
EP SGND PGND PGND

C1
C11 C12
R2
17 10 11 12
R3 GND2 VISO- TP10 VISO-
C2
GND1 TP7 TP11

GND1
GND2
C16
GND1 GND2
Figure 52. STEVAL-L6986IV1 evaluation board schematic
optional circuitry
TP12 Q1
EMI FIlters VOUT2
VOUT2
R16
U1 C15 R11
U4 R8
4 1 VISO+ TP8 VISO+
1 10
1 10 C21 R12
L4 L3 SYNCH RST 13 2 9 2 1
TP5 LX 2 9
15 14 U3
VIN VIN LX 3 8 D1
2 3 8
C20 C19 VCC 4 7
C18 R18 4 7 C13
5 R13
FSW 16 GND1 5 6
TP4 6 VBIAS 5 6 C17
MLF R1
9 GNDiso TP9
GNDpri 3 FB VOUT1 GNDiso
SS/INH 7 TP6
8 COMP
R17 DELAY C5
D3
C8
C9
C1
EP SGND PGND PGND

C12
C4 R2
17 10 11 12
R3 C11 GND2 VISO- TP10 VISO-
C2
TP7
GND1 TP11
GND1
GND2
C16
GND1 GND2
Figure 53. STEVAL-A6986IV2 evaluation board schematic
optional circuitry
EMI FIlter
TP12
Q1
R16 VOUT2 VISO+ TP8 VISO+
R11
R8 C15
4 1 U1
U2
L4 L3 SYNCH RST D1
13 1 8 2 1 R12
TP5 15 LX 14 1 8 U3
VIN VIN LX 2 7 C21
2 2 7
C20 C19 VCC 3 6
C18 R18 3 6 C17 C13
5
FSW 16 GND1 4 5 R13
6 VBIAS 4 5
TP4 R1
MLF 9
GNDpri 3 FB
SS/INH TP6 GND2 GNDiso TP9
7 GNDiso
8 COMP VOUT1
R17 DELAY C5 TP11
C4 GND2
C8
C9
EP SGND PGND PGND

C1
C11
R2
17 10 11 12
R3
C2
GND1 TP7
GND1
C16
GND1 GND2
The additional input filter (C20, L4, C18, L3, C19) limits the conducted emission on the power supply. In case the
filter is not necessary or should be by-passed for any test, a 0 Ω resistor can be placed at R16.
The evaluation board of the iso-buck is available with three different assemblies, mainly differentiated by the
isolation of the transformer (3.3 kV / 1.5 kV) and the isolated output options (single or dual voltage), as
summarized in the following table.
DS13481 - Rev 2 page 45/62

A6986I
Application board
Table 10. Type of the evaluation boards
Single/dual isolated
Assembly Board name Available isolated voltages
output(s)
#1 STEVAL-A6986IV1 Dual VISO+ = 18 V, VISO- = -4.5 V
#2 STEVAL-L6986IV1 Dual VISO+ = 18 V, VISO- = -4.5 V
#3 STEVAL-A6986IV2 Single VISO+ = 5 V
Table 11. BOM of the evaluation boards
Reference Part number Description Manufacturer
#1, #3 A6986I
U1 STM
#2 L6986I
C1 470 nF, 10 V, 0603
C2 68 nF, 10 V, 0603
C4 4.7 pF, 10 V, 0603
C5 680 pF, 10 V, 0603
C8, C11 CGA5L1X7R1H106K160AC 10 µF, 50 V, 1206 TDK
C9 CEU4J2X7R1H104K125AE 100 nF, 50 V, 0805 TDK
#1, #2 CGA4J3X7R1H105K125AB 1 µF, 50 V, 0805 TDK
C12
#3 N/A
C13 CGA4J3X7R1H105K125AB 1 µF, 50 V, 0805 TDK
#1, #2 82 pF, 10 V, 0603
C15
#3 68 pF, 10 V, 0603
C16 not mounted
C17 CNA6P1X7R1H106K250AE 10 µF, 50 V, 1210 TDK
C18 CGA5L3X5R1H475K 4.7 µF, 50 V, 1206 TDK
R1 6.8 kΩ, 1%
R2 1.3 kΩ, 1%
R3 56 kΩ, 1%
#1, #2 620 Ω, 1%
R8
#3 180 Ω, 1%
#1, #2 430 Ω, 1%
R11
#3 100 Ω, 1%
#1 36 kΩ, 1%
R12 #2 22 kΩ, 1%
#3 10.7 kΩ, 1%
#1 5.6 kΩ, 1%
R13 #2 4.3 kΩ, 1%
#3 11 kΩ, 1%
R16 Not mounted
DS13481 - Rev 2 page 46/62

A6986I
Fine tuning of the evaluation boards
Reference Part number Description Manufacturer
R17
R18
L3 XAL4030-472MEC 4.7 µH Coilcraft
L4 MPZ2012S221A Ferrite bead TDK
D1 STPS1150AY Schottky diode, 150 V, 1 A STM
#1, #2 BZT52B4V3-HE3-08 Zener diode 4.3 V Vishay Semiconductor
D3
#3 - N/A
Q1 2STR1215 NPN power transistor STM
Transformer, N = 5.8,
#1 ZA9668-AE Coilcraft
3.3 kV isolation
Transformer, N = 5.6,
U2 #2 2106.0007 Magnetica
1.5 kV isolation
Transformer, N = 1.53, 3.3
#3 ZB1175-AE Coilcraft
kV isolation
U3 TL431AIL3T Adjustable voltage reference STM
9.1 Fine tuning of the evaluation boards

The evaluation boards can be customized to better match the user demands.
1. If a different dual isolated voltage is necessary (e.g. 15 V / - 6 V), the replacement of two components is
enough to adapt the board: the Zener diode D3 (with a diode providing the most suitable Zener voltage) and
the resistor divider (one of the two resistors) R12 - R13, in accordance with the equation:
R +R
VISO+= 2.49V∙ 12 13 (47)
R13
Obviously, the total voltage VISO+ + |VISO-| must be compatible with the available voltage at the secondary
winding of the transformer.
2. STEVAL-A6986IV1 and STEVAL-L6986IV1 can be also turned into a single isolated voltage board by
soldering a 0 Ω resistor in place of the capacitor C12.
Any of the above-mentioned fine tunings could require an adjustment of the resistor R11.
DS13481 - Rev 2 page 47/62

A6986I
Figure 54. STEVAL-A6986IV1 (top layer)
Figure 55. STEVAL-A6986IV1 (bottom layer)
DS13481 - Rev 2 page 48/62

A6986I
Figure 56. STEVAL-L6986IV1 (top layer)
Figure 57. STEVAL-L6986IV1 (bottom layer)
DS13481 - Rev 2 page 49/62

A6986I
Figure 58. STEVAL-A6986IV2 (top layer)
Figure 59. STEVAL-A6986IV2 (bottom layer)
DS13481 - Rev 2 page 50/62

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Load regulation of the evaluation boards
9.2 Load regulation of the evaluation boards
Figure 60. STEVAL-A6986IV1, VIN = 12 V, fSW = 500 kHz
19
18.9
18.8
18.7
18.6
V ISO+ [V]
18.5
18.4
18.3
18.2
18.1
18
0 20 40 60 80 100
Output current [mA]
4.9
4.8
4.7
4.6
V ISO - [V]
4.5
4.4
4.3
4.2
4.1
4
0 20 40 60 80 100
Output current [mA]
DS13481 - Rev 2 page 51/62

A6986I
Load regulation of the evaluation boards
Figure 62. STEVAL-L6986IV1, VIN = 12 V, fSW = 500 kHz
19
18.9
18.8
18.7
18.6
V ISO+ [V]
18.5
18.4
18.3
18.2
18.1
18
0 20 40 60 80 100
Output current [mA]
Figure 63. STEVAL-L6986IV1, VIN = 12 V, fSW = 500 kHz
5
4.9
4.8
4.7
4.6
V ISO - [V]
4.5
4.4
4.3
4.2
4.1
4
0 20 40 60 80 100
Output current [mA]
5.25
5.2
5.15
5.1
5.05
VISO+ [V]
4.95
4.9
4.85
4.8
4.75
0 50 100 150 200 250 300 350 400 450 500
Output current [mA]
DS13481 - Rev 2 page 52/62

A6986I
Package information
10 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
10.1 HTSSOP16 package information
Figure 65. HTSSOP16 package outline
DS13481 - Rev 2 page 53/62

A6986I
HTSSOP16 package information
Table 12. HTSSOP16 mechanical data
mm
Symbol
Min. Typ. Max.
A 1.20
A1 0.15
A2 0.80 1.00 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.00 5.10
D1 2.8 3 3.2
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
E2 2.8 3 3.2
e 0.65
L 0.45 0.60 0.75
L1 1.00
K 0.00 8.00
aaa 0.10
DS13481 - Rev 2 page 54/62

A6986I
Ordering information
11 Ordering information
Table 13. Ordering information
Part number Package Packing
A6986I Tube
HTSSOP16
A6986ITR Tape and reel
DS13481 - Rev 2 page 55/62

A6986I
Revision history
Table 14. Document revision history
Date Version Changes
26-Mar-2021 1 First release.

26-May-2021 2 Updated Features on the cover page.
DS13481 - Rev 2 page 56/62

A6986I
Contents
Contents
1 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Parameters over the temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1 Primary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1.1 Power supply and voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1.2 Switchover feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.3 Voltage monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1.4 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.2 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.4 Iso-buck operation principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.5 Soft-start and inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.6 Minimum on-time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.7 Output voltage line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8 Output voltage load regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.9 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.10 Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.11 Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6 Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

6.1 GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.2 Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

6.3 Voltage divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Total loop gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.5 Compensation network design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7 Application notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

7.1 Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
DS13481 - Rev 2 page 57/62

A6986I
Contents
7.2 Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

7.3 Voltage supervisor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4.1 Embedded master - slave synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4.2 External synchronization signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7.5 Design of the external components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

7.5.1 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.5.2 Transformer selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
7.5.3 Schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
7.5.4 Output capacitors selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

9 Application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9.1 Fine tuning of the evaluation boards. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2 Load regulation of the evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
10 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

10.1 HTSSOP16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
DS13481 - Rev 2 page 58/62

A6986I
List of tables
List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 4. ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 5. Electrical characteristics (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . 5
Table 6. fSW selection (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 7. RST threshold selection (TJ = -40 to 135°C, VIN = 12 V unless otherwise specified).. . . . . . . . . . . . . . . . . . . . . . 7
Table 8. Uncompensated error amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Example of oscillator frequency selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 10. Type of the evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 11. BOM of the evaluation boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 12. HTSSOP16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 13. Ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 14. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
DS13481 - Rev 2 page 59/62

A6986I
List of figures
List of figures
Figure 1. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 3. Circuit RVCC, RGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Iso-buck general schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Internal circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Iso-buck basic operating principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Iso-buck primary and secondary current waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Soft-start phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Enable the device with external voltage step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Tracked soft-start at secondary side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Simulation with insufficient masking time (< 100 ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 13. Simulation with appropriate masking time (330 ns) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. Remaining oscillations filtered by the masking time and RC snubber circuit VIN = 12 V, N = 1.58, IOUTiso = 100 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 15. Schematic used for line and load regulation tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 16. Primary line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 17. Secondary output line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 18. Secondary winding current at different input voltages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 19. Load regulation of the non isolated output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Effect of the transformer leakage inductance on the isolated output load regulation . . . . . . . . . . . . . . . . . . . . 19
Figure 21. Input voltage effect on the load regulation of the isolated voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 22. Valley current sense operation in short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 23. Peak current sense operation in overcurrent condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 24. Peak currents depending on the secondary output current (VIN = 12 V, VOUT_pri = 5.3, N = 6, fSW = 500 kHz, no
primary output current) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. Overvoltage operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 26. Block diagram of the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 27. Transconductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 28. Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 29. Bode plote (magnitude) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 30. Bode plot (phase) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 31. A6986I application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 32. Isolated voltage variation due to the primary output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 33. Secondary output maximum current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 34. Voltage supervisor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 35. Voltage supervisor operation during OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 36. Input RMS current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 37. Two regulators not synchronized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 38. Two regulators not synchronized. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 39. A6986I synchronization driving capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. Slave-to-master mode transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 41. Master driving capability to synchronize the A6986I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 42. Input capacitor AC current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 43. Primary (blue) winding current, secondary (pink) winding current and magnetizing current (black) . . . . . . . . . . 39
Figure 44. Secondary winding positive peak current dependency on duty cycle (IOUT_sec = 100 mA). . . . . . . . . . . . . . . . 40
Figure 45. Primary negative peak current dependency on duty cycle (VOUT_pri = 5 V, IOUT_pri = 0, IOUT_sec = 100 mA, N = 6,
fSW = 500 kHz, L = 19 µH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 46. Secondary winding current according to different leakage inductances (simulation) . . . . . . . . . . . . . . . . . . . . 41
Figure 47. Snubber circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 48. Transformer parasitic capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 49. Typical schematic with load applied to both the isolated and not isolated outputs. . . . . . . . . . . . . . . . . . . . . . 43
DS13481 - Rev 2 page 60/62

A6986I
List of figures
Figure 50. Maximum deliverable currents to the isolated and not isolated outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 51. STEVAL-A6986IV1 evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 52. STEVAL-L6986IV1 evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 53. STEVAL-A6986IV2 evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 54. STEVAL-A6986IV1 (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 55. STEVAL-A6986IV1 (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 56. STEVAL-L6986IV1 (top layer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 57. STEVAL-L6986IV1 (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 58. STEVAL-A6986IV2 (top layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 59. STEVAL-A6986IV2 (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 60. STEVAL-A6986IV1, VIN = 12 V, fSW = 500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 62. STEVAL-L6986IV1, VIN = 12 V, fSW = 500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 63. STEVAL-L6986IV1, VIN = 12 V, fSW = 500 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 65. HTSSOP16 package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DS13481 - Rev 2 page 61/62

A6986I
IMPORTANT NOTICE – PLEASE READ CAREFULLY

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2021 STMicroelectronics – All rights reserved
DS13481 - Rev 2 page 62/62

Automotive 38 V, 5 W Synchronous Iso-Buck Converter For Isolated Applications

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A6986I

Automotive 38 V, 5 W synchronous iso-buck converter for isolated applications

• AEC-Q100 Grade 1 qualified

DS13481 - Rev 2 - May 2021 www.st.com

Figure 1. Application schematic

DS13481 - Rev 2 page 2/62

Figure 2. Pin connection (top view)

Table 1. Pin description

DS13481 - Rev 2 page 3/62

2.1 Maximum ratings

Table 2. Absolute maximum ratings

Symbol Description Min. Max. Unit

DELAY -0.3 VCC + 0.3 V

SS /INH -0.3 VIN + 0.3 V

RST -0.3 VIN + 0.3 V

TSTG Storage temperature range - -65 to 150 °C

TLEAD Lead temperature (soldering 10 s.) - 260 °C

IHS, ILS High-side / low-side switch current - 2 A

Table 3. Thermal data

Symbol Parameter Value Unit

Thermal resistance junction ambient (device soldered

Table 4. ESD protection

Symbol Test conditions Value Unit

DS13481 - Rev 2 page 4/62

Symbol Parameter Test condition Min. Typ. Max. Unit

VIN Operating input voltage range 4 38

VIN_H VCC UVLO rising threshold 2.7 3.5 V

VIN_L VCC UVLO falling threshold 2.4 3.5

Duty cycle < 20% 2.55

IVY_SNK Reverse current limit TJ = 25°C 1.285 1.9 2.61

TJ = 135°C 1.385 1.9 2.425

RDS(on)HS High-side RDSON ISW = 1 A 0.18 0.36

fSW Selected switching frequency FSW pinstrapping before SS See Table 6

IFSW FSW biasing current SS ended 0 500 nA

IMLF MLF biasing current SS ended 0 500 nA

D Duty cycle (1) 0 100 %

TJ = - 40°C 267 325 379

TON MIN Minimum on-time TJ = 25°C 281 330 383 ns

TJ = 135°C 330 400 461

VBIAS = GND (no switchover) 2.9 3.3 3.6

VSS < VINH or t < TSS SETUP or VEA + > VFB(1) 1

DS13481 - Rev 2 page 5/62

Symbol Parameter Test condition Min. Typ. Max. Unit

SS/INH to internal error amplifier

IFB FB biasing current 50 500 µA

AV Error amplifier gain (1) 100 dB

Inner current loop

VOVP HYST Overvoltage hysteresis 0.5 2 5 %

Synchronization (fanout: 6 slave devices typ.)

ISYN SYNCH pull-down current VSYN = 1.2 V 0.7 mA

High level output 5 mA sinking load 1.40

VTHR HYST RST hysteresis (1) 2 %

ID CH CDELAY charging current VFB > VTHR 1 2 3 µA

1. Not tested in production.

DS13481 - Rev 2 page 6/62

0Ω NC (1) 225 250 275

NC 3.3 kΩ (3) 900 1000 1100

1. Synchronization as slave between 275 kHz and 1000 kHz.

Figure 3. Circuit RVCC, RGND