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MAX3232E

SLLS664E – AUGUST 2005 – REVISED JUNE 2021

MAX3232E 3-V to 5.5-V Multichannel RS-232 Line Driver and Receiver


With ±15-kV IEC ESD Protection

1 Features 3 Description
• ESD protection for RS-232 bus pins The MAX3232E device consists of two line drivers,
– ±15 kV (HBM) two-line receivers, and a dual charge-pump circuit
– ±8 kV (IEC61000-4-2, Contact discharge) with ±15-kV IEC ESD protection pin to pin (serial-port
– ±15 kV (IEC61000-4-2, Air-gap discharge) connection pins, including GND).
• Meets or exceeds the requirements of TIA/ The device meets the requirements of TIA/EIA-232-
EIA-232-F and ITU V.28 standards F and provides the electrical interface between
• Operates with 3-V to 5.5-V VCC supply an asynchronous communication controller and the
• Operates up to 250 kbit/s serial-port connector. The charge pump and four small
• Two drivers and two receivers external capacitors allow operation from a single 3-V
• Low supply current: 300 μA (typical) to 5.5-V supply. The devices operate at data signaling
• External capacitors: 4 × 0.1 μF rates up to 250 kbit/s and a maximum of 30-V/μs
• Accepts 5-V logic input with 3.3-V supply driver output slew rate.
• Pin compatible to alternative high-speed devices
(1 Mbit/s) Device Information(1)
– SN65C3232E (–40°C to +85°C) PART NUMBER PACKAGE BODY SIZE (NOM)
– SN75C3232E (0°C to 70°C) SOIC (D) (16) 9.90 mm × 3.91 mm
SSOP (DB) (16) 6.20 mm × 5.30 mm
2 Applications MAX3232E
SOIC (DW) (16) 10.30 mm × 7.50 mm
• Industrial PCs
TSSOP (PW) (16) 5.00 mm × 4.40 mm
• Wired networking
• Data center and enterprise computing (1) For all available packages, see the orderable addendum at
• Battery-powered systems the end of the data sheet.
• Notebooks
• Palmtop PCs
• Hand-held equipment

3.3 V, 5 V POWER

2 2 DOUT
DIN TX
RS232

2 2 RIN
ROUT RX
RS232

Simplified Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MAX3232E
SLLS664E – AUGUST 2005 – REVISED JUNE 2021 www.ti.com

Table of Contents
1 Features............................................................................1 8.1 Overview..................................................................... 9
2 Applications..................................................................... 1 8.2 Functional Block Diagram........................................... 9
3 Description.......................................................................1 8.3 Feature Description.....................................................9
4 Revision History.............................................................. 2 8.4 Device Functional Modes..........................................10
5 Pin Configuration and Functions...................................3 9 Application and Implementation.................................. 11
6 Specifications.................................................................. 4 9.1 Application Information..............................................11
6.1 Absolute Maximum Ratings........................................ 4 9.2 Typical Application.................................................... 11
6.2 ESD Ratings............................................................... 4 10 Power Supply Recommendations..............................12
6.3 ESD Ratings - IEC Specifications............................... 4 11 Layout........................................................................... 13
6.4 Recommended Operating Conditions(1) .................... 4 11.1 Layout Guidelines................................................... 13
6.5 Thermal Information....................................................5 11.2 Layout Example...................................................... 13
6.6 Electrical Characteristics — Device(1) ........................5 12 Device and Documentation Support..........................14
6.7 Electrical Characteristics — Driver(1) ......................... 5 12.1 Receiving Notification of Documentation Updates..14
6.8 Electrical Characteristics — Receiver(2) .................... 6 12.2 Support Resources................................................. 14
6.9 Switching Characteristics(1) ....................................... 6 12.3 Trademarks............................................................. 14
6.10 Typical Characteristics.............................................. 7 12.4 Electrostatic Discharge Caution..............................14
7 Parameter Measurement Information............................ 8 12.5 Glossary..................................................................14
8 Detailed Description........................................................9

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (May 2017) to Revision E (June 2021) Page
• Added Applications: Industrial PCs, Wired networking, and Data center and enterprise computing..................1
• Added the ESD Ratings - IEC Specifications table. Added a table note about 1-uF capacitor requirement
between VCC and GND for D, DB and PW packages......................................................................................... 4
• Changed the thermal parameter values for D, DB and PW packages in the Thermal Information table............5

Changes from Revision C (June 2015) to Revision D (May 2017) Page


• Changed 3 V ± 5.5 V to 3 V to 5.5 V in the VCC column of Table 9-1 .............................................................. 11

Changes from Revision B (December 2013) to Revision C (May 2015) Page


• Added Device Information table, Pin Configuration and Functions section, ESD Ratings table, Feature
Description section, Device Functional Modes, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ..................................................................................................1

Changes from Revision A (April 2007) to Revision B (December 2013) Page


• Updated document to new TI data sheet format.................................................................................................1
• Deleted Ordering Information table.....................................................................................................................1
• Added Thermal Information table....................................................................................................................... 5

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5 Pin Configuration and Functions

C1+ 1 16 VCC
V+ 2 15 GND
C1− 3 14 DOUT1
C2+ 4 13 RIN1
C2− 5 12 ROUT1
V− 6 11 DIN1
DOUT2 7 10 DIN2
RIN2 8 9 ROUT2

Figure 5-1. D, DW, DB and PW Package, 16-Pin SOIC, SSOP and TSSOP, Top View

Table 5-1. Pin Functions


PIN
I/O DESCRIPTION
NAME NO.
C1+ 1 — Positive lead of C1 capacitor
V+ 2 O Positive charge pump output for storage capacitor only
C1– 3 — Negative lead of C1 capacitor
C2+ 4 — Positive lead of C2 capacitor
C2– 5 — Negative lead of C2 capacitor
V– 6 O Negative charge pump output for storage capacitor only
DOUT2 7 O RS232 line data output (to remote RS232 system)
RIN2 8 I RS232 line data input (from remote RS232 system)
ROUT2 9 O Logic data output (to UART)
DIN2 10 I Logic data input (from UART)
DIN1 11 I Logic data input (from UART)
ROUT1 12 O Logic data output (to UART)
RIN1 13 I RS232 line data input (from remote RS232 system)
DOUT1 14 O RS232 line data output (to remote RS232 system)
GND 15 — Ground
VCC 16 — Supply Voltage, Connect to external 3-V to 5.5-V power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(2) –0.3 6 V
V+ Positive output supply voltage(2) –0.3 7 V
V– Negative output supply voltage(2) 0.3 –7 V
V+ – V– Supply voltage difference(2) 13 V
Drivers –0.3 6 V
VI Input voltage
Receivers –25 25 V
Drivers –13.2 13.2 V
VO Output voltage
Receivers –0.3 VCC + 0.3 V
TJ Operating virtual junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime
(2) All voltages are with respect to network GND.

6.2 ESD Ratings


VALUE UNIT

Human body model (HBM), per ANSI/ All pins except RIN and DOUT ±2000
ESDA/JEDEC JS-001(1) RIN and DOUT Pins ±15,000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
All pins ±1500
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings - IEC Specifications


VALUE UNIT
IEC61000-4-2, Contact RS232 port pins (RIN,
±8000
Discharge(1) DOUT)
V (ESD) Electrostatic discharge V
IEC61000-4-2, Air-Gap RS232 port pins (RIN,
±15,000
Discharge(1) DOUT)

(1) For D, DB and PW packages only: Minimum of 1-µF capacitor is required between VCC and GND to meet the specified IEC 16000-4-2
rating.

6.4 Recommended Operating Conditions(1)


See Typical Operating Circuit and Capacitor Values.
MIN NOM MAX UNIT
VCC = 3.3 V 3 3.3 3.6
Supply voltage V
VCC = 5 V 4.5 5 5.5
VCC = 3.3 V 2 5.5
VIH Driver high-level input voltage DIN V
VCC = 5 V 2.4 5.5
VIL Driver low-level input voltage DIN 0 0.8 V
VI Receiver input voltage RIN –25 25 V

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6.4 Recommended Operating Conditions(1) (continued)


See Typical Operating Circuit and Capacitor Values.
MIN NOM MAX UNIT
MAX3232EC 0 70
TA Operating free-air temperature °C
MAX3232EI –40 85

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.

6.5 Thermal Information


MAX3232E
THERMAL METRIC(1) PW (TSSOP) D (SOIC) DW (SOIC) DB (SSOP) UNIT
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 108.2 85.9 72.3 103.1 °C/W
RθJCtop Junction-to-case (top) thermal resistance 39.0 43.1 33.5 49.2 °C/W
RθJB Junction-to-board thermal resistance 54.4 44.5 37.1 54.8 °C/W
ψJT Junction-to-top characterization parameter 3.3 10.1 7.5 12 °C/W
ψJB Junction-to-board characterization parameter 53.8 44.1 37.1 54.1 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.6 Electrical Characteristics — Device(1)


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical
Operating Circuit and Capacitor Values).
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
ICC Supply current No load, VCC = 3.3 V or 5 V 0.3 1 mA

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

6.7 Electrical Characteristics — Driver(1)


over operating free-air temperature range (unless otherwise noted) (see Typical Operating Circuit and Capacitor Values).
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
VOH High-level output voltage DOUT at RL = 3 kΩ to GND, DIN = GND 5 5.4 V
VOL Low-level output voltage DOUT at RL = 3 kΩ to GND, DIN = VCC –5 –5.4 V
IIH High-level input current VI = VCC ±0.01 ±1 μA
IIL Low-level input current VI at GND ±0.01 ±1 μA
VCC = 3.6 V, VO = 0 V
IOS (3) Short-circuit output current ±35 ±60 mA
VCC = 5.5 V, VO = 0 V
rO Output resistance VCC, V+, and V– = 0 V, VO = ±2 V 300 10M Ω

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) Short-circuit durations should be controlled to prevent exceeding the device absolute power dissipation ratings, and not more than one
output should be shorted at a time.
(3) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

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6.8 Electrical Characteristics — Receiver(2)


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical
Operating Circuit and Capacitor Values).
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
VOH High-level output voltage IOH = –1 mA VCC – 0.6 VCC – 0.1 V
VOL Low-level output voltage IOL = 1.6 mA 0.4 V
VCC = 3.3 V 1.5 2.4
VIT+ Positive-going input threshold voltage V
VCC = 5 V 1.8 2.4
VCC = 3.3 V 0.6 1.2
VIT– Negative-going input threshold voltage V
VCC = 5 V 0.8 1.5
Vhys Input hysteresis (VIT+ – VIT–) 0.3 V
ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ

(1) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(2) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.

6.9 Switching Characteristics(1)


over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Typical
Operating Circuit and Capacitor Values)
PARAMETER TEST CONDITIONS MIN TYP(2) MAX UNIT
RL = 3 kΩ, CL = 1000 pF,
Maximum data rate 150 250 kbit/s
One DOUT switching, see Driver Slew Rate
RL = 3 kΩ to 7 kΩ,
tsk(p) Driver pulse skew(3) CL = 150 pF to 2500 pF, 300 ns
see Driver Pulse Skew
Driver slew rate, transition CL = 150 pF to 1000 pF 6 30
RL = 3 kΩ to 7 kΩ,
SR(tr) region V/μs
VCC = 3.3 V CL = 150 pF to 2500 pF 4 30
(see Driver Slew Rate)
Receiver propagation delay
tPLH 300 ns
time, low- to high-level output CL = 150 pF,
Receiver propagation delay see Receiver Propagation Delay Times
tPHL 300 ns
time, high- to low-level output
tsk(p) Receiver pulse skew(3) 300 ns

(1) Test conditions are C1–C4 = 0.1 μF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 μF, C2–C4 = 0.33 μF at VCC = 5 V ± 0.5 V.
(2) All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
(3) Pulse skew is defined as |tPLH – tPHL| of each channel of the same device.

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6.10 Typical Characteristics


6 0

5 ±1
DOUT Voltage (V)

DOUT Voltage (V)


4 ±2

3 ±3

2 ±4

1 ±5
VOH VOL
0 ±6
0 5 10 15 20 25 0 5 10 15 20 25
DOUT Current (mA) C001 DOUT Current (mA) C001

VCC = 3.3 V VCC = 3.3 V


Figure 6-1. DOUT VOH vs Load Current, Both Drivers Loaded Figure 6-2. DOUT VOL vs Load Current, Both Drivers Loaded

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7 Parameter Measurement Information


3V
Input 1.5 V 1.5 V
RS-232
Output 0V
Generator
(see Note B) 50 Ω
CL tTHL tTLH
RL (see Note A)
VOH
3V 3V
Output
−3 V −3 V
VOL

TEST CIRCUIT 6V VOLTAGE WAVEFORMS


SR(tr)
t or t
THL TLH
A. CL includes probe and jig capacitance

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns

Figure 7-1. Driver Slew Rate

3V
RS-232 Input 1.5 V 1.5 V
Generator Output 0V
(see Note B) 50 Ω
CL tPHL tPLH
RL (see Note A)
VOH
Output 50% 50%
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns

Figure 7-2. Driver Pulse Skew

3V
Input 1.5 V
1.5 V
Output −3 V
Generator
(see Note B) 50 Ω tPHL tPLH
CL
(see Note A) VOH
Output 50% 50%
VOL
TEST CIRCUIT VOLTAGE WAVEFORMS
A. CL includes probe and jig capacitance

B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns

Figure 7-3. Receiver Propagation Delay Times

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8 Detailed Description
8.1 Overview
The MAX3232E device consists of two line drivers, two-line receivers, and a dual charge-pump circuit with
IEC61000-4-2 ESD protection terminal to terminal (serial-port connection terminals, including GND). The device
meets the requirements of TIA/EIA-232-F and provides the electrical interface between an asynchronous
communication controller and the serial-port connector. The charge pump and four small external capacitors
allow operation from a single 3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s
and a maximum of 30-V/μs driver output slew rate. Outputs are protected against shorts to ground.
8.2 Functional Block Diagram

3.3 V, 5 V POWER

2 2 DOUT
DIN TX
RS232

2 2 RIN
ROUT RX
RS232

8.3 Feature Description


8.3.1 Power
The power block increases, inverts, and regulates voltage at V+ and V– pins using a charge pump that requires
four external capacitors.
8.3.2 RS232 Driver
Two drivers interface standard logic level to RS232 levels. Both DIN inputs must be valid high or low.
8.3.3 RS232 Receiver
Two receivers interface RS232 levels to standard logic levels. An open input will result in a high output on ROUT.
Each RIN input includes an internal standard RS232 load.

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8.4 Device Functional Modes


Table 8-1 and Table 8-2 list the functional modes of the drivers and receivers of MAX3232E.
Table 8-1. Each Driver(1)
INPUT OUTPUT
DIN DOUT
L H
H L

(1) H = high level, L = low level

Table 8-2. Each Receiver(1)


INPUT OUTPUT
RIN ROUT
L H
H L
Open H

(1) H = high level, L = low level,


Open = input disconnected or connected driver off

11 14
DIN1 DOUT1

10 7
DIN2 DOUT2

12 13
ROUT1 RIN1

9 8
ROUT2 RIN2

Figure 8-1. Logic Diagram

8.4.1 VCC Powered by 3 V to 5.5 V


The device is in normal operation.
8.4.2 VCC Unpowered, VCC = 0 V
When MAX3232E is unpowered, it can be safely connected to an active remote RS232 device.

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9 Application and Implementation


Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information


For proper operation, add capacitors as shown in Table 9-1.
9.2 Typical Application
ROUT and DIN connect to UART or general-purpose logic lines. RIN and DOUT lines connect to a RS232
connector or cable.

1 VCC 16
C1+
+ CBYPASS
− = 0.1µF
+ 2 15
C1 V+ GND
(1) +
− C3

14
3 DOUT1
C1−

13
4 RIN1
C2+
+
C2 5 kΩ

5 C2−

12
ROUT1
6
V− 11

C4 DIN1
+
7 10
DOUT2 DIN2

8 9
RIN2 ROUT2

5 kΩ

A. C3 can be connected to VCC or GND


A. Resistor values shown are nominal.
B. Nonpolorized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be connected
as shown.

Figure 9-1. Typical Operating Circuit and Capacitor Values

Table 9-1. VCC vs Capacitor Values


VCC C1 C2, C3, C4
3.3 V ± 0.3 V 0.1 µF 0.1 µF
5 V ± 0.5 V 0.047 µF 0.33 µF
3 V to 5.5 V 0.1 µF 0.47 µF

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9.2.1 Design Requirements


The recommended VCC is 3.3 V or 5 V. 3 V to 5.5 V is also possible
The maximum recommended bit rate is 250 kbit/s.
9.2.2 Detailed Design Procedure
All DIN inputs must be connected to valid low or high logic levels.
Select capacitor values based on VCC level for best performance.
9.2.3 Application Curve
Figure 9-2 curves are for 3.3-V VCC and 250-kbit/s alternative bit data stream.
6
5
4
3
2
1
Voltage (V)

0
±1
±2
±3
±4
±5
±6
±7 DIN
DOUT to RIN
±8
ROUT
±9
0 1 2 3 4 5 6 7 8 9 10
Time ( s) C001

Figure 9-2. 250 kbit/s Driver to Receiver Loopback Timing Waveform, VCC = 3.3 V

10 Power Supply Recommendations


The supply voltage, VCC, should be between 3 V and 5.5 V. Select the values of the charge-pump capacitors
using Table 9-1.

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11 Layout
11.1 Layout Guidelines
Keep the external capacitor traces short, specifically on the C1 and C2 nodes that have the fastest rise and fall
times.
11.2 Layout Example

Ground

1 C1+ VCC 16 VCC


C3
0.1µF
C1 2 V+ GND 15 Ground

3 C1– DOUT1 14

4 C2+ RIN1 13
C2
5 C2– ROUT1 12

Ground 6 V– DIN1 11
C4
7 DOUT2 DIN2 10

8 RIN2 ROUT2 9

Figure 11-1. Layout Diagram

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12 Device and Documentation Support


12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

Mechanical, Packaging, and Orderable Information


The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.

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PACKAGE OPTION ADDENDUM

www.ti.com 15-Dec-2023

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

MAX3232ECDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP232EC Samples

MAX3232ECDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232EC Samples

MAX3232ECDRE4 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232EC Samples

MAX3232ECDW LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232EC


MAX3232ECDWG4 NRND SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232EC
MAX3232ECDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3232EC Samples

MAX3232ECPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 MP232EC Samples

MAX3232EIDBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP232EI Samples

MAX3232EIDBRE4 ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP232EI Samples

MAX3232EIDR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232EI Samples

MAX3232EIDW LIFEBUY SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232EI
MAX3232EIDWG4 NRND SOIC DW 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232EI
MAX3232EIDWR ACTIVE SOIC DW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3232EI Samples

MAX3232EIPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP232EI Samples

MAX3232EIPWRG4 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 MP232EI Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 15-Dec-2023

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MAX3232E :

• Automotive : MAX3232E-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 14-Dec-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS


K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)


QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal


Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MAX3232ECDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
MAX3232ECDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232ECDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MAX3232ECPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232ECPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
MAX3232EIDBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
MAX3232EIDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
MAX3232EIDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
MAX3232EIPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 14-Dec-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal


Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MAX3232ECDBR SSOP DB 16 2000 356.0 356.0 35.0
MAX3232ECDR SOIC D 16 2500 356.0 356.0 35.0
MAX3232ECDWR SOIC DW 16 2000 350.0 350.0 43.0
MAX3232ECPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232ECPWR TSSOP PW 16 2000 356.0 356.0 35.0
MAX3232EIDBR SSOP DB 16 2000 356.0 356.0 35.0
MAX3232EIDR SOIC D 16 2500 356.0 356.0 35.0
MAX3232EIDWR SOIC DW 16 2000 350.0 350.0 43.0
MAX3232EIPWR TSSOP PW 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 14-Dec-2023

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal


Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
MAX3232ECDW DW SOIC 16 40 506.98 12.7 4826 6.6
MAX3232ECDWG4 DW SOIC 16 40 506.98 12.7 4826 6.6
MAX3232EIDW DW SOIC 16 40 506.98 12.7 4826 6.6
MAX3232EIDWG4 DW SOIC 16 40 506.98 12.7 4826 6.6

Pack Materials-Page 3
PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
PACKAGE OUTLINE
DB0016A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1

2X
6.5
4.55
5.9
NOTE 3

8
9
0.38
16X
0.22
5.6
B 0.1 C A B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN


0 -8 0.55

DETAIL A
A 15

TYPICAL

4220763/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
EXAMPLE BOARD LAYOUT
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

1 (R0.05) TYP

16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

LAND PATTERN EXAMPLE


EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK


METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN


ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK


DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220763/A 05/2022
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.


6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM


(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220763/A 05/2022
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

www.ti.com
PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE


TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SEE


SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP

(9.3)

LAND PATTERN EXAMPLE


SCALE:7X

SOLDER MASK SOLDER MASK METAL


METAL OPENING OPENING

0.07 MAX 0.07 MIN


ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK


DEFINED DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.


7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP
(9.3)

SOLDER PASTE EXAMPLE


BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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