2076 Journal of Power Electronics, Vol. 16, No. 6, pp.

2076-2084, November 2016

http://dx.doi.org/10.6113/JPE.2016.16.6.2076
JPE 16-6-9 ISSN(Print): 1598-2092 / ISSN(Online): 2093-4718

Common-Mode Voltage Elimination

for Medium-Voltage Three-Level NPC Inverters
Based on an Auxiliary Circuit
Quoc Anh Le*, Sangmin Lee*, and Dong-Choon Lee†
*,†
Department of Electronic Engineering, Yeungnam University, Gyeongsangbuk, Korea

Abstract

In this paper, a novel scheme to eliminate common-mode voltage (CMV) is proposed for three-level neutral-point clamped
(NPC) inverters. In the proposed scheme, a low-power full-bridge converter is utilized to produce compensatory voltage for
CMV, which is injected into an NPC inverter through a single-phase four-winding transformer. With the proposed circuit, the
power range for applications is not limited, and the maximum modulation index of the inverter is not reduced. These features are
suitable for high-power medium-voltage machine drives. The effectiveness of the proposed method is verified by simulation and
experimental results.

Key words: Active circuit, Common-mode voltage, High-power medium-voltage drives, Neutral-point clamped inverter, Space
vector modulation

peak and root mean square (RMS) values of CMV are reduced,
whereas the fundamental voltage component is retained.
I. INTRODUCTION However, these methods cannot fully eliminate the CMV of
High-power medium-voltage induction machine drives are inverters. Other CMV elimination methods have been
widely utilized in industrial applications because of the proposed to cancel leakage current by utilizing only the zero-
development of multilevel inverters with high-speed and medium-voltage vectors of three-level NPC inverters [20,
switching devices [1]-[4]. Pulse-width modulation (PWM) 21]. Although the leakage current can be fully cancelled by
voltage-source inverters (VSIs), especially neutral-point these techniques, the use of the DC-link voltage is only 86.6%
clamped (NPC) inverters, are popularly used; these inverters due to the exclusion of large-voltage vectors. Another
present high output performance [1]-[5]. However, PWM drawback of modulation approaches is the increase in the
inverters generate common-mode voltage (CMV), which may switching losses and total harmonics distortion (THD) of the
cause serious problems, such as leakage current through stray output voltage.
capacitors, bearing current, shaft voltage, and motor winding- Meanwhile, CMV elimination methods based on auxiliary
to-ground voltages [6]-[17]. Therefore, the CMV of VSIs circuits with complementary-symmetry transistors have been
must be reduced or eliminated to preserve the life time of recommended for two-level inverters [7, 9]. With additional
motors and transformers. circuits, the CMV of inverters can be fully eliminated without
Many of the solutions proposed to reduce or cancel CMV any adverse effect on the fundamental component of the
can be classified into modulation approaches and auxiliary output voltage. However, auxiliary circuits cannot be applied
circuit schemes. In modulation techniques, only voltage to medium-voltage inverters because of the power limit of the
vectors producing low CMV are utilized [6], [18], [19]. The complementary-symmetry transistors. In addition, the
transformer in the auxiliary circuit must be carefully designed
Manuscript received May 13, 2016; accepted Jul. 9, 2016 because of the power dissipation constraint of the transistors.
Recommended for publication by Associate Editor Kyo-Beum Lee.
†
Corresponding Author: [email protected] In this study, a novel scheme for CMV elimination in three-
Tel: +82-53-810-2582, Fax: +82-53-810-4767, Yeungnam University level NPC inverters is proposed; the scheme involves the use
*
Dept. of Electrical Engineering, Yeungnam University, Korea of an auxiliary circuit and modified space-vector pulse-width
© 2016 KIPE
 Common-Mode Voltage Elimination … 2077

(a) (b)
Fig. 1. Three-phase three-level NPC inverters. (a) Circuit. (b)
Space voltage vector diagram. Fig. 2. Voltage vector in sector 1 for SVPWM of three-level NPC
inverters.
TABLE I TABLE II
SWITCHING STATES OF THREE-LEVEL NPC INVERTERS CLASSIFICATION OF VOLTAGE VECTORS FOR NPC INVERTERS
Switching states SA1 SA2 Pole voltage (vAO) Voltage Vector
Group CMV value
P 1 1 Vdc/2 vectors magnitude
O 0 1 0 NNN −Vdc/2
Zero-voltage
OOO 0 0
N 0 0 −Vdc/2 vector
PPP Vdc/2
ONN
modulation (SVPWM) [17] and is applicable to medium- NNO −Vdc/3
voltage inverter systems. The auxiliary circuit consists of a NON
OON
common-mode transformer (CMT) and a low-power H-bridge
NOO −Vdc/6
converter to generate compensatory CMV. The modified Small voltage ONO
SVPWM of the NPC inverter is utilized to reduce the peak Vdc/3
vector POO
value of CMV. The proposed method is verified by simulation OPO Vdc/6
results for a high-power three-level NPC inverter and OOP
experimental results for a prototype hardware. PPO
OPP Vdc/3
POP
PON
II. THREE-LEVEL NPC INVERTERS OPN
Medium NPO Vdc
A. Structure of NPC Inverters 0
voltage vector NOP 3
NPC inverters are widely utilized in high-power medium- ONP
voltage applications [1]-[5]. The simplified structure of three- PNO
phase, three-level NPC inverters (Fig. 1(a)) includes two PNN
common capacitors arranged in a series for the DC link and NPN −Vdc/6
Large voltage PPN
three phase legs. Each phase leg involves four active switches 2Vdc/3
vector NNP
with antiparallel diodes connected in a series and two clamped NPP Vdc/6
diodes connected to the neutral point of the DC link. The four PNP
active switches are separated into two complementary pairs,
namely, S A 1 and S A1 and S A 2 and S A2 . The switching four small triangular regions composed of three voltage
vectors at the vertices (Fig. 1(b) and Fig. 2, respectively) [4].
states and pole voltages of phase leg “A” are provided in
Therefore, the reference voltage vector can be synthesized by
Table I, where “1” and “0” denote the on-state and off-state of
the nearest three voltage vectors based on the “voltage-second
the switches, respectively.
balance,” which is expressed as
   
B. SVPWM with Seven-Segment Switching Pattern Vref TS  VxTx  VyTy  Vz Tz , (1)
An NPC inverter produces 27 voltage vectors for TS  Tx  Ty  Tz
modulation (Fig. 1(b)) [4] generated from the switching states
where Tx, Ty, and Tz are the dwell times of vectors
of the three phase legs. These voltage vectors are classified as   
zero, small, medium, and large according to their magnitude Vx , V y , and Vz , respectively, at the vertex of the triangle where
(Table II). the reference voltage vector is located. The voltage vectors
For modulation, the hexagon in the space vector diagram is and their dwell time are determined. Then, the seven-segment
divided into six triangular sectors, which are further split into SVPWM of the NPC inverter is selected to reduce the THD
2078 Journal of Power Electronics, Vol. 16, No. 6, November 2016

PWM CMV elimination circuit Induction

inverter 1:1:1:1 machine
A A’
+
- B B’
Vdc + O n
C C’
-
C1
P P’
N’
+
Q1 Vdc/2
-

E +
Q2 Vdc/2 -

Fig. 4. Active circuit with linear devices for CMV elimination [7].

transistors, Q1 and Q2, operate in the linear region. Therefore,

the emitter voltage of the transistors to the DC link mid-point,
vEO, is equal to the detected CMV of vN’O and the CMV of vnO.
Fig. 3. Pole voltages and CMV in three-level NPC inverters with
seven-segment switching sequence. The three secondary windings of the CMT are connected in
series between the inverter output and the load terminals; thus,
and switching losses of the inverter, the pole voltage of which the CMV of the induction motor drive system, vnO, can be
is shown in Fig. 3. eliminated by adding compensatory voltage for CMV to the
primary winding of CMT.
C. CMVs
An improved active circuit that can compensate for CMV
For the machine drive system, the CMV of the NPC through CMT with an appropriate turn ratio was presented in
inverter, vnO, is defined as the voltage difference between the [9]. In the circuit, the voltage rating of the transistors is
neutral point of the machine and the mid-point of the DC link reduced compared with the DC-link voltage of the inverter,
in the inverter; it is expressed as the average of the three- but the current rating of transistors is increased due to the
phase pole voltages as follows: change in the transformer turn ratio.
v  v BO  vCO , (2) Although active circuits can successfully eliminate CMV,
v CMV  v nO  AO
3 their application is limited because of the power rating of the
where vAO, vBO, and vCO are the pole voltages of the inverter transistors operating in the linear region. Furthermore, the
[18]. CMT in these circuits requires a large magnetizing inductance.
As listed in Table II, the large voltage vectors produce a Thus, active circuits are inapplicable to medium-voltage
CMV of –Vdc/6 or Vdc/6. The CMV generated by the small motor drive systems.
voltage vectors varies from –Vdc/3 to Vdc/3, except for the
value of 0 V with a step change of Vdc/6. The medium voltage
IV. PROPOSED CMV ELIMINATION METHOD
vectors and voltage vector [OOO] generate zero CMV.
Normal seven-segment SVPWM for three-level NPC inverters A. Modification of SVPWM for CMV Reduction
usually produces four voltage levels of CMV in a switching To reduce CMV, instead of using all 27 voltage vectors in
cycle. As shown in Fig. 3, CMV, which includes four voltage the regular SVPWM, only 19 voltage vectors possessing a low
levels, varies from –Vdc/6 to Vdc/3 with a voltage step of Vdc/6. CMV value are utilized [18]. The division of triangle regions
By selecting other redundant small voltage vectors, the CMV for SVPWM is rearranged to reduce the level change in the
of the inverters varies from –Vdc/3 to Vdc/6. With normal CMVs. Therefore, the CMV varies only by two voltage levels,
seven-segment SVPWM, a three-level NPC inverter generally such as 0 V and Vdc/6 in a switching cycle or –Vdc/6 and 0 V in
produces CMV varying from –Vdc/3 to Vdc/3 with a voltage another cycle. However, this SVPWM method incurs
step of Vdc/6. increments in switching losses and THD because the three
nearest voltage vectors are not utilized in several regions.
In this research, SVPWM was modified by dividing each
III. EXISTING CMV ELIMINATION METHODS BASED sector into four equilateral triangles (Fig. 5) and utilizing 19
ON ACTIVE CIRCUITS voltage vectors only. The three nearest voltage vectors were
An active circuit for CMV elimination that utilizes a pair of applied to the region of equilateral triangles; reduced THD
complementary transistors (Q1 and Q2), three capacitors (C1), and switching losses were thus obtained. With the modified
and a CMT (shown in Fig. 4) was introduced in [7]. In this SVPWM, the CMVs of the inverter vary among –Vdc/6, 0 V,
circuit, the capacitors, C1, are connected to detect the CMV at and Vdc/6, as shown in Fig. 6. In addition, the switching losses
the inverter output terminals. The complementary-symmetry of the NPC inverter with the five-segment switching pattern is
 Common-Mode Voltage Elimination … 2079

Fig. 5. Modified SVPWM utilizing only 19 voltage vectors for a Fig. 6. Pole voltages and CMV in a three-level NPC inverter with
three-level NPC inverter. a five-segment switching pattern in the modified SVPWM.

1 :1 :1 :1

Fig. 7. Induction motor drive system with an auxiliary circuit for CMV elimination.

further reduced to two-thirds of those of the seven-segment H-bridge converter feeds the primary winding of the CMT
pattern under identical PWM periods [4], [22]. Furthermore, indicated as PP’. The secondary windings of the CMT are
the fundamental component of the output voltage is connected in series with the output terminal of the inverter to
maintained similar to that in the normal seven-segment insert the compensatory CMV to the inverter output voltage.
SVPWM. The neutral-point voltage can be balanced by
C. Operating Principle of the Auxiliary Circuit
adjusting an offset voltage [18].
The H-bridge circuit can generate compensatory voltage,
B. Proposed Auxiliary Circuit which is similar to the CMV produced by the NPC inverter
The CMV generated by the inverter can be eliminated with with the modified SVPWM. That is,
an auxiliary circuit, which can produce compensatory voltage vAA  vBB '  vCC '  vPP  vCMV . (3)
for the CMV of the NPC inverter. For the three-level NPC With the auxiliary circuit, the CMV of the NPC inverter
inverter with the modified SVPWM, CMV varies among system is modified from Equation (2) to
three-level voltages of −Vdc/6, 0, and Vdc/6, which can be fully v  v B 'O  vC 'O .
vCMV '  A'O (4)
eliminated by the auxiliary circuit generating the three-level 3
voltages. In this work, an H-bridge converter with a DC input Substituting Equation (2) into Equation (4) yields
voltage of Vdc/6 is used to compensate for CMV, which can  (v AA '  v BB '  vCC ' )
generate three-level voltages of −Vdc/6, 0, and Vdc/6. vCMV '   vCMV . (5)
3
The proposed circuit, shown in Fig. 7, is composed of an H- Substituting Equation (3) into Equation (5) yields
bridge converter with a DC voltage of Vdc/6 and a CMT. The vCMV '  0 . (6)
H-bridge converter consists of X1, X 1 , X2, and X 2 switches
The resulting expressions indicate that the CMV of the NPC
with two complementary pairs of X1 and X 1 and X2 and X 2 . inverter is eliminated successfully with the proposed method.
Notably, the additional DC source and H-bridge converter are The line-to-line voltage of the converter is unaltered and
rated at low power due to their low current requirements. The verified as
2080 Journal of Power Electronics, Vol. 16, No. 6, November 2016

TABLE III
SYSTEM PARAMETERS FOR SIMULATION
Parameters Values
DC input voltage 6,500 V
DC-link capacitance 3,000 F
Switching frequency 2,000 Hz
Rated output frequency 60 Hz
Rated output voltage (Vll rms) 4,160 V
Rated output power 2,000 kW

(Van+Vbn+Vcn)/3
2K

CMV (V)
1K

0K

-1K

-2K
Vgs1+2 Vgs2
4

H-bridge gating
3

signals (A)
2
1
0
-1
V_cmn
2K

Compensating
voltage (V)
1K

0K

-1K

Fig. 8. Operating principle of the proposed method. -2K

V_CMV
2K
System CMV

1K
v A'B '  v A' A  v AB  vBB'  v AB . (7)
(V)

0K
-1K
Eq. (3) can be implemented by a single-phase four-winding -2K
0.298 0.2985 0.299 0.2995 0.3
transformer supplied by an H-bridge circuit (Fig. 7). Time (s)

To generate the compensatory voltage, the gating signals of Fig. 9. Voltage waveforms for CMV compensation. (a) CMV
the H-bridge converter depend on the switching states of NPC generated. (b) Gating signals of the H-bridge converter. (c)
inverter voltages. The gating signal of gX1 is ON and that of Output voltage of the H-bridge converter. (d) CMV of the load.
gX2 is OFF for the voltage vectors producing a CMV of Vdc/6.
Meanwhile, the gating signal gX2 is ON and that of gX1 is OFF V. SIMULATION RESULTS
for the voltage vectors generating a CMV of –Vdc/6. During PSIM simulation tests were conducted for the high-power
the interval of the CMV with 0 V, the gating signals of gX1 medium-voltage NPC inverter system to verify the
and gX2 are either ON or OFF. By requiring these gating effectiveness of the proposed scheme. The parameters of the
signals of the H-bridge converter, the dwell times of gX1 and inverter used for simulation are listed in Table III.
gX2 can be obtained from Tx, Ty, and Tz given by the modified Fig. 9 shows the voltage waveforms for the proposed
SVPWM of the NPC inverter. method in four switching cycles. Fig. 9(a) displays CMV,
Fig. 8 shows the operating principle of the proposed which varies among three voltage levels of −1,083, 0, and
scheme. The three pole voltages, the CMV of the inverter, the 1,083 V. Fig. 9(b) shows the gating signals of the H-bridge
gating signals of the H-bridge circuit, and compensatory converter, in which only gX1 is ON during positive CMV and
voltage waveform vPP’ are illustrated when the voltage only gX2 is ON during negative CMV. Meanwhile, both gX1
reference is located in region  in Fig. 5. For voltage vector and gX2 are OFF when the CMV value is zero. Fig. 9(c) shows
OON with a CMV of –Vdc/6, the gating signal gX1 is OFF and the output voltage waveform of the H-bridge converter
gX2 is ON during Tz. During the dwell time of Ty (state PON), applied to the primary windings of the CMT, vPP’, by which
the gating signals of gX1 and gX2 are OFF. For voltage vector the CMV of the load can be eliminated (Fig. 9(d)).
PPN, by generating a CMV of Vdc/6, the gating signals of gX1 Fig. 10 illustrates the voltages and currents of the three-
and gX2 are ON and OFF, respectively, during Tx. With these level NPC inverter with the normal seven-segment SVPWM
gating signals, the generated compensatory voltage vPP’ is method. The line-to-line voltage is shown in Fig. 10(a), in
similar to the CMV of the NPC inverter, vCMV, in terms of which five voltage levels of −Vdc, −Vdc/2, 0, Vdc/2, and Vdc
phase and magnitude. Therefore, CMV and its effects on the exist. The THD of the line-to-line voltage is 33.2%. Fig. 10(b)
load are eliminated. shows the three phase currents, which are sinusoidal and
 Common-Mode Voltage Elimination … 2081
Van-Vbn
Van-Vbn
10K
10K
5K
5K
0K
0K
-5K
-5K
-10K
-10K
ias ibs -ias-ibs
ias ibs -ias-ibs 600
600
300
300 0
0 -300
-300 -600

-600 V_CMV
4K
V_CMV
4K 2K

2K 0K

0K -2K

-2K -4K

-4K V_cmn
0.25 0.26 0.27 0.28 0.29 0.3 2K
Time (s) 1K

Fig. 10. Output performance of the NPC inverter with normal 0K

seven-segment SVPWM. (a) Line-to-line voltage. (b) Three- -1K

phase currents. (c) CMV of the load. -2K

0 25 0 26 0 27 0 28 0 29 03
Van-Vbn 10
10
10K
5
5K
0
0K
-5
-5
-5K -10
-10
-10K
Vdc1 Vdc2
ias ibs -ias-ibs 3.35K
600 3.3K

300 3.25K
3.2K
0
3.15K
-300 0.25 0.26 0.27 0.28 0.29 0.3
Time (s)
-600
V_CMV Fig. 12. Output performance of the NPC inverter with the
4K proposed scheme. (a) Line-to-line voltage. (b) Three-phase
2K currents. (c) CMV of the load. (d) Output of the H-bridge
0K converter. (e) Primary-side current of CMT. (f) DC-link capacitor
-2K voltages.
-4K
0.25 0.26 0.27 0.28 0.29 0.3 contains five voltage levels. The THD of the voltage is about
Time (s)
33.2%, which is similar to that of the normal seven-segment
Fig. 11. Output performance of the NPC inverter with the
modified SVPWM. (a) Line-to-line voltage. (b) Three-phase
SVPWM method. The three phase currents are shown in Fig.
currents. (c) CMV of the load. 12(b); they are sinusoidal and balanced as in Fig. 10(b). The
current THD with the auxiliary circuit operation is 3.10%,
balanced, with a THD of 2.25%. Fig. 10(c) shows the CMV of which is slightly reduced due to the increase in load
the inverter that varies from −2,167 V to 2,167 V with five inductance when the CMT windings are connected in series.
voltage steps. The RMS value of the CMV is 1,045 V. The effect of the proposed scheme is shown in Fig. 12(c). The
The simulation results for the NPC inverter with the CMV of the NPC inverter is almost eliminated. The RMS
modified SVPWM without the auxiliary circuit are illustrated value of the CMV for the proposed scheme is 14.5 V, which is
in Fig. 11. Fig. 11(a) shows the line-to-line voltage, which is about 1.8% and 1.4% compared with that of the modified
similar to that that in Fig. 10(a); its THD is 33.2%. Fig. 11(b) SVPWM without the auxiliary circuit and the normal seven-
displays the three phase currents, which are sinusoidal and segment SVPWM method, respectively. Fig. 12(d) shows the
balanced; their THD increases to 3.25% because of the five- compensatory voltage generated by the H-bridge converter.
segment switching pattern. Fig. 11(c) shows the CMV of the The primary-side current of the CMT consists of the
inverter that varies from −1,063 V to 1,063 V with three voltage magnetizing current only as shown in Fig. 12(e), where the
steps. The RMS value of the CMV of the inverter, vnO, is 797 V. peak value is about 1% that of the load currents, which is a
The simulation results of the proposed technique are shown design parameter for the CMT. The DC-link capacitor
in Fig. 12. Fig. 12(a) illustrates the line-to-line voltage, which voltages of the NPC inverter, vC1 and vC2, are kept balanced.
2082 Journal of Power Electronics, Vol. 16, No. 6, November 2016

3L-NPC
inverter

External circuit

H-bridge

Transformer Load
Fig. 13. Experimental setup.

TABLE IV
PARAMETERS OF THE HARDWARE SETUP
Parameters Values Fig. 14. Output performance of the NPC inverter with the seven-
DC input voltage 200 V segment SVPWM. (a) Line-to-line voltage. (b) Three-phase
DC-link capacitance 3.3 mF currents. (c) CMV of load.
Switching frequency 5 kHz
Output frequency 60 Hz

Line-to-line
voltage (V)
Rated output voltage (Vline rms) 140 V
Rated output power 4 kW
Resistive load 10 
Inductive load 5 mH
CMT turn ratio 2.444:1:1:1
Three-phase
currents (A)

Their fluctuation is less than 1% of the rated value, as shown

in Fig. 12(f).
Common-mode

VI. EXPERIMENTAL RESULTS

voltage (V)

The proposed method was tested on a prototype of an NPC

inverter system (shown in Fig. 13). The parameters of the
hardware setup are listed in Table IV. IGBTs
(SKM75GB12T4) were used for the NPC and H-bridge
Fig. 15. Output performance of the NPC inverter with the
converters. These IGBTs are controlled by a DSP chip modified SVPWM. (a) Line-to-line voltage. (b) Three-phase
(TMS320F28335). The system includes 16 PWM gating currents. (c) CMV of load.
signals implemented by a Xilinx FPGA device (XC3S400-
PQG208EGQ1321), among which 12 and 4 gating signals are the THDs of line-to-line voltage and currents are slightly
arranged for the NPC and H-bridge converters, respectively. higher than those in Fig. 14(b) and 14(c), respectively, since
The switching frequency of the inverter is 5 kHz. in the two SVPWM methods, the PWM sampling periods, not
Fig. 14 shows the output performance in the unity the switching frequencies, are similar [22]. However, the
modulation index with the normal seven-segment SVPWM CMV of the NPC inverter with modified modulation is 33.3
method. Fig. 14(a) shows the line-to-line voltage of the and 22.6 V in the peak and RMS values, respectively. As
inverter, where five voltage levels of –Vdc, −Vdc/2, 0, Vdc/2, shown in Fig. 15(c), the CMV varies only in three voltage
and Vdc exist. Its THD is about 26.7%. The three phase levels of −33.3, 0, and 33.3 V.
currents of the NPC inverter, which are balanced and Fig. 16 shows the performance of the proposed scheme.
sinusoidal, are presented in Fig. 14(b). Fig. 14(c) shows the The line-to-line voltage of the NPC inverter with CMV
CMV of the NPC inverter, which includes five voltage levels eliminated is shown in Fig. 16(a), where the THD is similar to
of −66.7, −33.3, 0, 33.3, and 66.7 V; the RMS value is 26.4 V. that in Fig. 15(a). Fig. 16(b) shows the three phase currents of
The output performance of the NPC inverter with the the NPC inverter, which are balanced and sinusoidal with a
modified SVPWM method is also illustrated in Fig. 15. The THD of 1.48%. Notably, the output performance of the NPC
line-to-line voltage, three phase currents, and system CMV inverter is well maintained with the proposed scheme. Fig.
correspond to those in Fig. 14. Fig. 15(a) and (b) show that 16(c) shows CMV, where the peak and RMS values are
 Common-Mode Voltage Elimination … 2083

the H-bridge converter and CMT. The auxiliary circuit can

overcome the power range drawback of existing methods. The
simulation and experimental results proved the effectiveness
of the proposed method. The RMS value of CMV in the
proposed method is only about 8.0% of that in the seven-
segment SVPWM method. Furthermore, the maximum
modulation index is not reduced with the modified SVPWM.

ACKNOWLEDGMENT
This research was supported by the National Research
Foundation of Korea (NRF-2014R1A2A1A11052748).

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The magnified waveforms of CMV and the compensatory common-mode voltage PWM methods and comparison
voltage in the proposed method are shown in Fig. 17(a) and with standard PWM methods for three-phase voltage-
(b), respectively. CMV contains small ripples, and the source inverters,” IEEE Trans. Power Electron., Vol. 24,
compensatory voltage involves three voltage levels. No. 1, pp. 241-252, Jan. 2009.
[11] S. K. Mun and S. Kwak, “Reducing common-mode voltage
of three-phase VSIs using the predictive current control
VII. CONCLUSION method based on reference voltage,” Journal of Power
Electronics, Vol. 15, No. 3, pp. 712-720, May 2015.
A novel method to eliminate CMV in three-level NPC [12] M. M. Renge and H. M. Suryawanshi, “Five-level diode
inverters is proposed. This method utilizes not only the clamped inverter to eliminate common mode voltage and
modified SVPWM method but also the proposed circuit with reduce dv/dt in medium voltage rating induction motor
2084 Journal of Power Electronics, Vol. 16, No. 6, November 2016

drives,” IEEE Trans. Power Electron., Vol. 23, No. 4, pp. Quoc Anh Le was born in Can Tho, Vietnam,
1598-1607, Jul. 2008. in 1988. He received his B.S. degree in
[13] G. Scelba, A. Testa, M. Cacciato, S. D. Caro, and G. electrical engineering from Can Tho
Scarcella, “Improved space-vector modulation technique University, Can Tho, Vietnam, in 2010. He
for common mode currents reduction,” IET Power received his M.S. degree from Ho Chi Minh
Electron., Vol. 6, No. 7, pp. 1248-1256, Aug. 2013. City University of Technology, Ho Chi Minh
[14] A. K. Gupta and A. M. Khambadkone, “A space vector City, Vietnam, in 2013. He is presently
PWM scheme to reduce common mode voltage for a working to complete his Ph.D. degree in the
cascaded multilevel inverter,” in 37th IEEE Power Department of Electrical Engineering, Yeungnam University,
Electronics Specialists Conference, pp. 1-7, 2006. Gyeongbuk, Korea. In 2011, he was an assistant lecturer in the
[15] A. Ojha, P. Chaturvedi, A. Mittal, and S. Jain, “Carrier College of Technology, Can Tho University. His current research
based common mode voltage reduction techniques in interests include high-power converters and multi-level
neutral point clamped inverter based AC-DC-AC drive converters.
system,” Journal of Power Electronics, Vol. 16, No. 1, pp.
142-152, Jan. 2016.
[16] Z. Zhao, Y. Zhong, H. Gao, L. Yuan, and T. Lu, “Hybrid Sangmin Lee was born in 1990. In 2015, he
selective harmonic elimination PWM for common-mode received his B.S. degree in electrical
voltage reduction in three-level neutral-point-clamped engineering from Yeungnam University,
inverters for variable speed induction drives,” IEEE Trans. Gyeongsan, Korea, where he is currently
Power Electron., Vol. 27, No. 3, pp. 1152-1158, Mar. 2012. working to accomplish his M.S. degree in
[17] Q. A. Le and D. C. Lee, “Common-mode voltage Power Electronics and Machine Control
elimination in three-level NPC inverters for medium Laboratory. His research interests include
voltage motor drives,” in ISEE 2015, pp. 272-278, 2015. high-power DC–DC converters and energy
[18] H. J. Kim, H. D. Lee, and S. K. Sul, “A new PWM strategy storage systems.
for common-mode voltage reduction in neutral-point-
clamped inverter-fed AC motor drives,” IEEE Trans. Ind.
Appl., Vol. 37, No. 6, pp. 1840-1845, Aug. 2002. Dong-Choon Lee received his B.S., M.S.,
[19] A. Videt, P. Le Moigne, N. Idir, P. Baudesson, and X. and Ph.D. degrees in electrical engineering
Cimetière, “A new carrier-based PWM providing common- from Seoul National University, Seoul, Korea,
mode-current reduction and DC-bus balancing for three- in 1985, 1987, and 1993, respectively. He
level inverters,” IEEE Trans. Ind. Electron., Vol. 54, No. 6, was a research engineer in Daewoo Heavy
pp. 3001-3011, Jan. 2008. Industry, Korea, from 1987 to 1988. He has
[20] M. C. Cavalcanti, A. M. Farias, K. C. Oliveira, F. A. S. been a faculty member in the Department of
Neves, and J. L. Afonso, “Eliminating leakage currents in Electrical Engineering, Yeungnam University,
neutral point clamped inverters for photovoltaic Gyeongsan, Korea, since 1994. As a visiting scholar, he joined
systems,”IEEE Trans. Ind. Electron., Vol. 59, No. 1, pp. the Power Quality Laboratory, Texas A&M University, College
435-443, Jan. 2012. Station, TX, USA, in 1998; the Electrical Drive Center,
[21] J.-S. Lee and K.-B. Lee, “New modulation techniques for a University of Nottingham, Nottingham, UK, in 2001; the
leakage current reduction and a neutral-point voltage Wisconsin Electric Machines and Power Electronic Consortium,
balance in transformerless photovoltaic systems using a University of Wisconsin, Madison, WI, USA, in 2004; and the
three-level inverter,” IEEE Trans. Power Electron., Vol. 29, FREEDM Systems Center, North Carolina State University,
No. 4, pp. 1720-1732, Apr. 2014. Raleigh, NC, USA, from September 2011 to August 2012. His
[22] L. Helle, S. Munk-Nielsen, and P. Enjeti, “Generalized current research interests include AC machine drives, power
discontinuous DC-link balancing modulation strategy for converter control, wind power generation, and power quality.
three-level inverters,” in Proc. Power Convers. Conf. 2002, Professor Lee is currently the Editor-in-Chief for the Journal of
Vol. 2, pp. 359-366, 2002. Power Electronics of the Korean Institute of Power Electronics.