Lin 2013
Lin 2013
Lin 2013
org
Published in IET Power Electronics
Received on 19th March 2012
Revised on 1st September 2012
Accepted on 30th September 2012
doi: 10.1049/iet-pel.2012.0127
ISSN 1755-4535
Abstract: This study presents a new DC/DC converter with series-connected transformers to achieve zero voltage switching
(ZVS) for power switches, less transformer secondary winding and partial ripple current cancellation. Two three-level circuits
using the same active switches are operated with interleaved half switching cycle. The voltage stress of all switches is
clamped at Vin/2. The transformers secondary windings are connected in series to balance the primary side currents. The
current-doubler rectier is adopted on the output side. Thus, the output inductor ripple currents can be partially cancelled
each other and the resultant ripple current at the output capacitor is reduced compared with the output ripple current of the
centre-tapped rectier topology. Based on the resonant behaviour by the output capacitance of active switches and the leakage
inductance (or external inductance), all power switches are turned on at ZVS. Laboratory experiments with a 1 kW prototype,
verifying the effectiveness of the proposed converter, are described.
2 Circuit configuration and Css are large enough to be treated as three constant
voltages VC1 = VC2 = VCss = Vin/2 and (7) Co is large enough
The circuit conguration of the proposed three-level ZVS to be considered as a constant output voltage. Based on the
PWM converter is given in Fig. 1. Input capacitances Cin1 on/off states of S1 S4, Da Db and D1 D2, the proposed
and Cin2 are equal and large enough to share the input converter has ten operation modes in a switching period.
voltage vCin1 = vCin2 = Vin/2. S1 S4 are power MOSFETs The equivalent circuits of these modes are shown in Fig. 3.
and the voltage stresses of S1 S4 are clamped at Vin/2. Prior to time t0, S1, S2 and D1 are conducting. Inductor
Cr1 Cr4 are the output capacitances of MOSFETs S1 S4, currents iLr1(t0) < 0 and iLr2(t0) > 0.
respectively. Da and Db are the clamped diodes. Css is the Mode 1 [t0 t < t1, Fig. 3a]: At time t0, S1 is turned off.
ying capacitor and its voltage equals Vin/2. C1 and C2 are Since iLr1(t0) < 0 and iLr2(t0) > 0, Cr1 is charged and Cr4 is
the DC blocking capacitances. The average DC blocking discharged through the ying capacitor Css. The rising slope
voltages VC1 = VC2 = Vin/2. Lr1 and Lr2 are the resonant of the drain-to-source voltage of S1 is limited by Cr1 and
inductances. Lm1 and Lm2 are the magnetising inductances Cr4. Thus, S1 is turned off at ZVS. Since iLm1 (Io iLo1 )/n
of the transformers T1 and T2, respectively. D1 and D2 are and iLm2 (Io iLo1 )/n and Lo1 and Lo2 are large enough,
the rectier diodes. Lo1 and Lo2 are the output lter the primary currents iLr1 and iLr2 are almost constant in this
inductances. Ro and Co denote the load resistance and mode. Therefore Cr1 is charged linearly from zero voltage
output capacitance. There are two three-level ZVS PWM
circuits with the same power switches, the ying capacitor
and the clamped diodes in the proposed converter. The
components of the rst three-level circuit include Cin1, Cin2,
Da, Db, Css, S1 S4, Cr1 Cr4, C1, Lr1, T1, D1, D2, Lo1 and
Lo2. The second three-level PWM circuit includes the
components of Cin1, Cin2, Da, Db, Css, S1 S4, Cr1 Cr4,
C2, Lr2, T2, D1, D2, Lo1 and Lo2. The phase-shift PWM
scheme is used in the proposed converter. S1 and S4 are the
leading switches, and S2 and S3 are the lagging switches.
Three voltage levels Vin, Vin/2 and 0 are generated on the
terminal voltages vAB and vBC. Since the average voltages
VC1 = VC2 = Vin/2, three voltage levels Vin/2, 0 and Vin/2
are generated on the terminal voltages vp1 and vp2. The
primary and secondary windings of transformers T1 and T2
are connected in series in order to ensure that the primary
currents of T1 and T2 are balanced. The current-doubler
rectier with the series transformers is adopted at the
secondary side to obtain a stable output voltage Vo with one
diode conduction loss and to cancel partially the output
ripple current.
3 Operation principle
The theoretical PWM waveforms of the proposed converter in
a switching period are shown in Fig. 2. The following
assumptions are made to simplify the system analysis. (1)
Power semiconductors S1 S4, D1 D2 and Da Db are
ideal, (2) Lm1 = Lm2 = Lm, Lr1 = Lr2 = Lr Lm and Lo1 =
Lo2 = Lo, (3) Cin1 = Cin2 are large enough to be considered
as two voltage sources, (4) turns ratio of transformers T1
and T2 is n = np/ns, (5) Cr1 = Cr2 = Cr3 = Cr4 = Cr, (6) C1, C2 Fig. 2 Key waveforms of the proposed converter
Fig. 3 Operation modes of the proposed converter during one switching cycle
a Mode 1 f Mode 6
b Mode 2 g Mode 7
c Mode 3 h Mode 8
d Mode 4 i Mode 9
e Mode 5 j Mode 10
Vin nVo C V2
iLr1 (t) = iLr1 (t4 ) + (t t4 ),
2Lr + n2 Lo Lr i2Lr1 (t7 ) + i2Lr2 (t7 ) r in (15)
(11) 2
Vin nVo
iLr2 (t) = iLr2 (t4 ) (t t4 )
2Lr + n2 Lo This mode ends at t8 when vCr2 = 0 and vCr3 = Vin/2. The time
interval in mode 8 is expressed as
Power is delivered from input voltage source Vin to output
load Ro in this mode. In mode 5, the semiconductor losses Cr Vin nC V
are the conduction losses of S3, S4 and D2. This mode ends Dt78 = t8 t7 = = r in (16)
iLr1 (t7 ) iLr2 (t7 ) iLo, min
at t5 when S4 is turned off.
Mode 6 [t5 t < t6, Fig. 3f]: At time t5, S4 is turned off.
Since iLr1(t5) > 0 and iLr2(t5) < 0, Cr1 is discharged linearly The time delay td between S2 and S3 should be greater than the
from Vin/2 and Cr4 is charged linearly from zero voltage time interval t78. Thus, S2 can be tuned on at ZVS. In mode
through capacitor Css in this mode. Thus, the rising slope of 8, the semiconductor losses are the conduction losses of S1,
the drain-to-source voltage of S4 is limited by Cr1 and Cr4. D1 and D2.
Thus, S4 is turned off at ZVS. Since Lo1 and Lo2 are large Mode 9 [t8 t < t9, Fig. 3i]: After t8, vCr2 = 0. Since
enough, the primary currents iLr1 and iLr2 are almost iLr2(t8) iLr1(t8) < 0, the anti-parallel diode of S2 is
constant in this mode. The ZVS condition of S1 is given as conducting. Therefore S2 can be turned on at this moment
to achieve ZVS. In this mode, the voltages vAB = 0, vBC =
C V2 Vin, vp1 = Vin/2 and vp2 = Vin/2. Since D1 and D2 are still
(Lr + n2 Lo ) i2Lr1 (t5 ) + i2Lr2 (t5 ) r in (12) conducting, the inductor currents iLo1 and iLo2 both decrease
2 in mode 9. The inductor voltages vLr1 = Vin/2 and vLr2 =
Vin/2 such that the primary currents and the slopes of the
This mode ends at t6 when vCr1 = 0 and vCr4 = Vin/2. The time diode currents are given as
interval of mode 6 is given as
ID1,av = ID2,av Io /2, iD1,rms = iD2,rms Io / 2 (29)
Fig. 5 Measured waveforms of the gate voltages of S1 and S2 and Fig. 6 Measured waveforms of the gate voltage, drain voltage and
the primary side voltages vp1 and vp2 at full load switch current at the nominal input voltage Vin = 530 V and 25%
a Vin = 480 V load
b Vin = 530 V a Switches S1 and S2
c Vin = 580 V b Switches S3 and S4
iLo2,max dVin Ts LI I
iS2,max = iS3,max = iS4,max = iS1,max (32) iLr2 (t0 ) = iLm2,max + = ro + o
n 4Lm 2nLm 2n
If the ripple currents of active switches can be neglected, the (Vo + Vf ) 2Lr Io fs
+ 1d+ (34)
rms currents of S1 S4 are given as 2nLo fs nVin
I
iS1,rms = iS4,rms iS2,rms = iS3,rms o (33) In the same manner, the primary side inductor currents iLr1(t2)
n 2
Fig. 7 Measured waveforms of the gate voltage, drain voltage and Fig. 8 Measured waveforms of the gate voltage, drain voltage and
switch current at the nominal input voltage Vin = 530 V and 50% switch current at the nominal input voltage Vin = 530 V and 100%
load load
a Switches S1 and S2 a Switches S1 and S2
b Switches S3 and S4 b Switches S3 and S4
Fig. 11 Measured waveforms of the proposed converter at full Fig. 12 Measured waveforms of the proposed converter at full
load and Vin = 530 V load and Vin = 580 V
a Primary side currents a Primary side currents
b Secondary side currents b Secondary side currents
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