Chapter 2

Diode Applications
By Wan Rosmaria binti Wan Ahmad
ELE424 – OCT 2022 – FEB 2023
PART 2
Content
PART 1
• Introduction
• Series Diode Configurations
• Parallel and Series- Parallel Configurations
• Diode as Rectifier
• Power Supply
• Half-Wave and Full-Wave Rectifications
• Clippers
PART 2
• Clampers and Design of Clampers
PART 3
• Zener Regulators
 CLAMPER
• A clamper is a network constructed of a diode, a resistor and a
capacitor that shifts a waveform to a different dc level without
changing the appearance of the applied signal.
• Additional shifts can be obtained by introducing a dc supply to
the basic structure.
 Two Types of Clamper
1. Positive (+ve) clamper
• Diode is pointing downward
• Diode is ON during the +ve cycle of the input
• Output waveform is shifted downward relative to the
input waveform
• Do the +ve input cycle first to define the polarity of
the capacitor
2. Negative (-ve) clamper
• Diode is pointing upward
• Diode is ON during the -ve cycle of the input
• Output waveform is shifted upward relative to the
input waveform
• Do the -ve input cycle first to define the polarity of
the capacitor
 Clamper: Important Notes
1. From diode position, you’ll know whether the circuit is a
positive (+ve) or negative (–ve) clamper.
2. Total output swing = the total input swing
3. The amount of shift from input waveform to output
waveform = Vc
Steps for Clamper Analysis
Step 1: start the analysis by examining the response of the portion of
input signal that will forward bias the diode.
Step 2: During the period the diode is “ON” state, assume that the
capacitor will charge up instantaneously to a voltage level determined by
the surrounding network.
Step 3: Assume that the period when the diode is in “OFF” state the
capacitor holds on to its established voltage level.
Step 4: Throughout the analysis, maintain a continual awareness of the
location and the polarity of Vo to ensure the proper levels are obtained.
Step 5: Check that the total swing of the output matches that of input.
Example 1: Positive (+ve) Clamper
• The capacitor is connected directly
between input and output, the resistor
and the diode are in parallel with the
output signal.
• The diode may or may not have a
series dc supply as an added element.
• A diode and capacitor can be combined
to “clamp” an AC signal to a specific
DC level.
 Step 1 & Step 2
• For the interval 0 → T/2 (positive
input cycle) the diode is “ON” and
the capacitor charged up to V. Hence
vo = 0 V for this interval.
• The time constant,  = RC is
considered so small coz of the shorting
out of resistor R from the circuit.
• The Result - the capacitor is quickly
charge to the peak value of V volts
with the polarity as indicated beside.
 Step 3 & Step 4
• For the interval T/2 → T (negative input cycle)
the diode is “OFF” when the input switches to
negative state.
• The voltage, vo across the open-circuit KVL:
terminal diode is determined by the applied
voltage, Vi and the stored voltage across Vi + Vc + vo = 0
capacitor, Vc which both “pressuring” current vo = - (Vi +Vc)
through the diode from cathode to anode.
• Now R is back in the circuit and  is
sufficiently large to establish a discharge
period of 5 so that capacitor holds onto all its
charge, V=Q/C during the non-conducting
the diode.
Step 5
• The output is clamped to 0 V for the total swing
interval 0 → T/2 (positive input
cycle) but maintains the same total
swing of 2V as the input.
• This property gives excellent check
on the results obtained.

total swing
Example 2: Negative (-ve) Clamper
Using Ideal diode
• Determine vo for the circuit below.

Vdc is added into

the clamper network
 Step 1 & Step 2
• The input has a period of 1 ms and
an interval of 0.5 ms between levels.
• The analysis begins with t1 to t2
(negative cycle) since the diode is in
its short-circuit state.
• The output vo is across R and a
battery of 5 V, hence vo = 5 V. (1) Negative input cycle

• Applying KVL:
-20 – 5 + VC = 0
VC = 25 V
 (2) Positive input cycle

Step 3 & Step 4

For the period t2 → t3 (positive cycle), the diode is in
open-circuit state.
The battery 5 V is removed from the circuit and does
not have any effect on vo.
Applying KVL:
-10 – VC + vo = 0 (Vc=25V)
vo = 35 V
The time constant of fully discharging determined by
5 = RC = 50 ms << 0.5 ms
Good approximation that capacitor holds all its
charged during the non-conducting state.
Step 5
• The output total swing of 30 V matches that of the input.

Negative Clamper
Example 3: Negative (-ve) Clamper Using Si diode

• Now repeat Example 2 using silicon diode with VK = 0.7 V

 Step 1 & Step 2 Step 3 & Step 4

Analyze the negative input cycle (t1-t2) • For the period t2 → t3 (positive cycle),
first,
Applying KVL in the input section: The diode is in open-circuit state.
-20 - 5 + 0.7 + VC = 0 Vc=24.3V
VC = 24.3 V Applying KVL:
Applying KVL in the output section: -10 – 24.3 + vo = 0
vo = –0.7 + 5 vo = 34.3 V
vo = 4.3 V
 Step 5
Compare the output waveform of clamper network
that using Si diode to the clamper network that using Si diode
using Ideal diode.

Using ideal diode

The output total swing of 30

V matches that of the input.
Variety of Clamping Circuits
Clamping Network with a Sinusoidal Input

Shape of the output signal and voltage swing must be the same as in input signal.
 Negative Clamper Positive Clamper
• Diode is ON during the negative input cycle • Diode is ON during the positive cycle
• Output waveform is shifted downward relative to
• Output is shifted upward relative to the input the input.
• Analyze the NEGATIVE input cycle first, so • Analyze the POSITIVE input cycle first so that
that the polarity of the capacitor, hence the the polarity of the capacitor, hence the value of Vc
value of Vc can be determined. can be determined.
• Note: Once we defined the polarity, it will be
• Note: Once we defined the polarity of C, then fixed. Unless it is discharged.
itwill be FIXED! Unless the capacitor is
discharged. C
VC
- +
+ +
+ +
Si
ideal Vi R Vo
Vi R Vo
VDC VDC = 4.5V
- -
- = 6V -
Negative Clamper: Example 1
VC
Vi - + (2) During positive input cycle
+ + C
5 - +
ideal
t Vi R Vo + +
VDC VC
ideal
-10 - = 6V - Vi= 5V R Vo
VDC
- = 5V -
(1) During negative input cycle
- C + The polarity of Vc is
Diode is OFF, diode is open
-
VC
+ refer to the polarity
s/c ideal
of the diode, and it
Vi= 10V R Vo KVL to find Vo
VDC is the same in the
-Vi -VC + VO = 0
+ = 6V - positive input cycle
VO = Vi + VC
Diode is ON = 5 +16
VO = 0 + (6) = 6V = 21V
KVL to find VC
-Vi - Vo +Vc = 0
VC = Vi + Vo Therefore, the output waveform will
= 10 + 6 be shifted upward by Vc= 16V.
= 16V
(3) Sketch the output waveform

VO

Vi 21 The output waveform is

shifted upward by Vc=16V in
negative clamper

5 6V
5
t t

-10 -10
Negative Clamper: Example 2
Vi (2) During positive input cycle
C Diode is OFF (open)
20 + + KVL to find Vo
Si -Vi -VC + VO = 0
t Vi= 20V R Vo VO = Vi + VC
VDC =
-20 - 10V -
= 20 +9.3
= 29.3V

This is negative clamper, then do the analysis of negative

input cycle first to determine the polarity of C and VC. (3) Sketch the output waveform

(1) During negative input cycle VO

Vi
Diode is ON
C
- + VO = - 0.7 - 10 = -10.7V 29.3
- + 20 VC=9.3V
KVL to find VC 20
Si
Vi= 15V -Vi - Vo +Vc = 0
R Vo
VC = Vi + Vo t t
+
VDC = 10V
- = 20 + -10.7 -10.7
-20 -20
= 9.3V VC=9.3V
 Positive Clamper: Example (2) During negative input cycle

Vi C Diode is OFF (open)

+ - KVL to find Vo
C - +
Vi + VC + VO = 0
open
15 + + Vi= 15V R Vo VO = - Vi - VC
Ideal
VDC = 5V
= -15 - 20
t Vi R Vo + - = -35V
VDC = 5V
-15 - -
(3) Sketch the output waveform
VO
This is positive clamper, then do the analysis of positive Vi
input cycle first to determine the polarity of C and VC.

(1) During positive input cycle 15 20

Diode is ON
+ C - VO = - Vd - Vdc = -5V t -5 t
+ + KVL to find VC
Ideal -15 -20
Vi= 15V Vo
-Vi + VC +Vo = 0
R
VC = Vi - Vo
VDC = 5V -35
- - = 15 – (-5) VC=20V
= 20V The output waveform will be shifted
downward by Vc= 20V.
Clamper Network: Exercise 1
Using a Silicon diode, sketch the output waveform of the clamper network indicated in the
Figure 1 given.
Vi - +
C
25 + +
Si
Vi R Vo
t
-5 -
VDC = 4.5V
-

Figure Q1
Clamper Network: Exercise 2
Using a Silicon diode, sketch the output waveform of the clamper network indicated in the
Figure Q2 given.
Vi
VC

20 + +
Si
t Vi R Vo
3V
-20 - -

Figure Q2
Design A Clamper
 Design a Clamper (Negative Clamper)
Vi Vo
14.3

5 Design a 5) Then, we determine VDC based on the

t clamper using t circuit,
Si diode -5.7 VO = -VD – VDC
-15 = - 5.7 – VDC
= -VD - VO
1) Determine the type of clamper from the output = -0.7 – (-5.7) = 5V
waveform.
• The output waveform shifting upward → it is a negative If the value of VDC is positive, the polarity of
clamper
VDC drawn is correct
2) In the negative input cycle, we determine If the VDC value is negative, then the VDC
• VC=VO – Vin = - 5.7 – (-15) = 9.3V
• Vin = -15V, and Vo = -5.7V (from the given output waveform)
polarity in your circuit is incorrect!
You need to redraw the circuit by correcting
3) In the positive input cycle (from the input and output
waveform), we determine, the VDC polarity.
• Vin = 5V, Vo = 14.3V
4) Sketch your clamper design, 6) Justify your clamper design

This is negative clamper, so we must start the

First, we draw any polarity of analysis with the negative input cycle, and
VDC in the design circuit determine Vc.
 During negative cycle During positive cycle
C
C Vi - +
Vi - +
+ - +
+ VC Si
5 VC 5
Si t
t Vi= 15V Vi = 5V R Vo
R 5V
VDC V
= 5V -15 + -
-15 - o

-
Diode is ON
Diode is OFF, diode is open
VO = - 0.7 - (5) = 5.7V
KVL to find VC
KVL to find Vo
-Vi + 5 + 0.7 + VC = 0
-Vi - VC + VO = 0
VC = Vi – 5.7
VO = Vi + VC
= 15 – 5.7
Output waveform will be = 5 + 9.3
= 9.3V shifted upward by Vc= 9.3V. = 14.3V
After analysis done, verify the answer
with the given waveform in the
Conclusion: The clamper design is justified. question, then make a conclusion.
 Design a Clamper (Positive Clamper)
Vi Vo Vo = output voltage at
positive input cycle
+10 Design a 5
t clamper using t
ideal diode Vo = output voltage at
-10
-15 negative input cycle

1) Determine the type of clamper from the output Vi

C
waveform. +
• The output waveform shifting downward → it is a positive +
5
clamper ideal
t Vi= 10V Vo
R
2) In the positive input cycle, we determine VDC
• VC=Vin – VO= - 10 – (5) = 5V -15 - = 5V -
• Vin = 10V, and Vo = 5V (from the given output waveform)
3) In the negative input cycle (from the input and
output waveform), we determine,
• Vin = -10V, Vo = -15V
This is positive clamper, so we must
4) Sketch your clamper design, → start the analysis with the positive
5) Determine VDC from the design circuit input cycle, and determine Vc.
VO = VD + VDC = 0 + 5 = 5V
6) Justify your clamper design
During positive cycle During negative cycle

C + C -
+ -
+ + - +
VC s/c ideal VC
ideal
Vi= 10V R Vo Vi= -10V R Vo
VDC VDC
- = 5V - + = 5V -

Diode is ON
Vo = output voltage at Diode is OFF, diode is open
VO = 0 - (5) = 5V positive input cycle
KVL to find VC
KVL to find Vo
-Vi + VC +VO = 0
+Vi +VC + VO = 0
VC = Vi – Vo
VO = - Vi - VC
= 10 - 5
= -10 - 5 Vo = output voltage at
= 5V
= -15V negative input cycle

Output waveform will be After analysis done, verify the answer with the given
shifted downward by Vc= 5V. waveform in the question, then make a conclusion.

Conclusion: The clamper design is justified.

Exercise 3: Design a clamper
Using a Silicon diode, construct a clamper circuit that results in the desired output waveform as shown
in Figure Q3. Show overall analysis. Verify your clamper design and state the type of your clamper.

Vi Vo
9.3
4 Design a
t clamper using t
Si diode
-4.7
-10

Figure Q3
End of Part 2