A Novel Differential Ramp Generator Circuit with

PVT Compensation Structure

Mohsen Padash and Mostafa Yargholi
Department of Electrical Engineering, University of Zanjan, Zanjan, Iran.
[email protected]

Abstract— Applications like counter ADC demanded single-ended ramp generator [13]. Further, current source
accurate ramp signal with low power dissipation. This paper ramp generator has less complexity and switches than the
presents a novel approach of low power differential ramp resistor ladder ramp generator [4, 13-15]; therefore, in this
generator with negative feedback for the compensation of the paper, we present a differential ramp generator structure
variations in process, voltage, and temperature (PVT). The
using two current sources. The current sources are calibrated
derived equations of the proposed ramp generator circuit show
that PVT compensation is enhanced significantly. Additionally, continually by a negative feedback loop, which makes the
the circuit design and simulations were done in TSMC 0.18-μm proposed structure very stable with variations in the process,
CMOS technology. The Monte Carlo simulation results and voltage, and temperature. For instance, 50 percent mismatch
corner analysis show that the linearity of the ramp signal is between the capacitors does not change the linearity of the
about 9-bit while power dissipation of the circuit is about ramp voltages predominantly. For proving the robustness of
2.61μW. the proposed structure, the mathematical representation of
this model is expressed and a ramp generator with 9-bit
Index Terms—Counter ADC; Differential Ramp Generator; linearity is designed and simulated in TSMC 0.18-μm CMOS
PVT Compensation; Single Slope.
technology. The operation of the proposed ramp generator
I. INTRODUCTION circuit is illustrated in the following section.

Recently, scientists have shown great interests in single slope

analog to digital converters (SS-ADCs), or counter ADCs, II. PROPOSED RAMP GENERATOR
because of the reducing channel length in new technologies
[1-3]. In the past, SS-ADCs were not proper for high Figure 1 shows the proposed differential ramp generator
sampling rate applications, as counters sampling frequency schematic. The ramp circuit consists of two linear current
was limited; but nowadays SS-ADCs are more useful because sources, two charging capacitors (C0 and C1), and two
of the existing high sampling rate, low power, and digital feedback loops for compensation of the current sources. The
counters [4,5]. The ramp generator block defines the feedback loops include eight transmission gates (TGs), four
resolution of SS-ADC; so stable linear ramp generators are capacitors (C2, C3, C4 and C4), two analog multiplexers and
significantly required for this purpose [6]. Also, linear ramp one op-amp; TGs are used as switches in this structure. The
voltages are used in applications such as buck converter [7], proposed circuit works as follows. First, the ICSp current
proportional–integral–derivative (PID) controller system test charges the C0 capacitor linearly, to make positive ramp
[8], and ADC test [9]. On the other hand, the ramp generator voltage (Vrp). Simultaneously, discharging the C1 capacitor
circuit must be stable with variations in process, voltage, and with the ICSn produces negative ramp voltage (Vrn).
temperature (PVT) for these applications; so a low power, Furthermore, the two negative feedbacks in this structure
linear ramp generator circuit, which is very useful for adjust the desired slopes of output ramps. Ideally, the slope
applications like SS-ADCs, is presented in this paper errors of differential ramp voltages (Vrp and Vrp), is zero if the
Numerous attempts are made for the improvement of PVT maximum ramp voltage (Vramp Max(Ideal)) and minimum ramp
compensation in ramp generators [9-11]. Snoeij et al., 2007 voltage (Vramp Min(Ideal)) have constant values. For this purpose,
used a resistor ladder digital to analog converter, for making bandgap voltage reference or external constant voltages must
ramp voltages, which are utilized in a 10 bit ADC [12]. As be used. If the maximum voltage of Vrp is more than the ideal
the resistor ladder divides the supply voltage and generates voltage, then the Vrp of the next cycle increases using the
the output ramp in this structure, it shows robustness against negative feedback and vice versa; the negative feedback
supply voltage variations; however, the proposed structure is changes ICSp current with varying Vp voltage. Negative ramp
not differential. Danesh et al., 2013 proposed a similar voltage slope is also modified by changing Vp voltage in the
structure for counter ADC that used a differential ramp negative feedback loop.
generator using the resistor ladder [13]. To decrease the As shown in lower part of Figure 1, two negative feedback
number of resistors in the ramp generator structure, they used loops were used. Both of the feedbacks work in odd and even
a low pass filter. Generating differential ramps using resistor cycles by "Select" controlling voltage, that results in the use
ladder has been proposed previously by Danesh et al.. of one op-amp for two feedback loops. In this figure M3, M4
Additionally, Sordo et al., 2014 proposed a calibration and M8, M9 transistors are used as current sources, while M1,
method for PVT compensation of a single-ended ramp M2, and M6, M7 transistors are use as the two transmission
generator [11]. gates. Further, M0 and M5 transistors are used for
The differential ramp generator has smore merits than the discharging of the C0 and C1, respectively.

ISSN: 2180 – 1843 e-ISSN: 2289-8131 Vol. 12 No. 1 January – March 2020 63
Journal of Telecommunication, Electronic and Computer Engineering

Opamp
VDD
+ Opamp_Out
C1 +
_ - Voffset Vp M4
+
IC2 Vp Vrn
Multiplexer I CSp
-
C2 M5
IC3 M3
Vn
Multiplexer

C3 Select M7 M6 VCLKV
VCLK M2 M1
VCLK VCLKV
Clk1 Clk1

IC5 Vramp
Min(Ideal) Vn M8
C5
+
C0
M0 Vrp
ClkV1 ClkV1 I CSn
Clk2 Clk2
+ -
M9 Voffset -
Vrn

ClkV2 ClkV2

Clk
Clk1 Clk1
ClkV
IC4 Vramp
Max(Ideal) Clk1
C4

ClkV1 ClkV1 ClkV1

Clk2 Clk2
Clk2
Vrp ClkV2

Select
ClkV2 ClkV2

Figure 1: Proposed structure of the ramp generator with PVT compensation feedbacks

The differential ramp voltages for the SS-ADCs must have

the same voltage ranges [13]. For that reason, offsets are vital V p  V p 0  
C4
C2

VRMIp  VRMp  (6)
for the proposed ramp generator because the current sources
must be in the saturation region. Further, an offset (Voffset) that
is equal to 0.45V is used for both of the ramp voltages. Vn  Vn0  
C5
VRMIn  VRMn  (7)
Following the mathematical equations of the feedback C3
loop, a ramp generator the charging current (I) is equal to:
Vp(0) and Vn(0) in these equations are the initial values of Vp
V and Vn. These equations reveal the negative feedback effects
I C (1)
T on Vp and Vn. In fact, according to (6) and (7), V p and Vn
change, until VRM and VRMI become equal. To consider these
In this equation, C is the charging capacitor, ΔV and ΔT periodic manners, the following equations are derived from
are the voltage and time differences, respectively. By (6) and (7):
considering the clocks from Figure 1 and neglecting the


 V 
negative input current of the op-amp, we have the following C4
equations for the charging currents of the capacitors: V p i   V p i 1  RMIp  VRMp i  (8)
C2 i 1
IC 2  IC 4 (2)


 V 
C5
IC3  IC5 Vni   Vni 1  RMIn  VRMni  (9)
(3) C3 i 1

According to (1), (2), (3) and Figure 1, by substituting IC2,

These equations reveal the gradual variations of Vp and Vn for
IC3, IC4, and IC5, the following equations are achieved:
satisfying the circuit conditions to reach the ideal ramps
slopes. More information about (8) and (9) are available in
0  Vp VRMIp  VRMp
C2  C4 (4) Figure 3. By considering Vn, the start time of Figure 3 (b),
t t equals to 0.9V, while VRMIn, VRMn(1), C3 and C5 equal to
0.45V, 0V, 0.951pF and 57fF, respectively. According to (9),
0  Vn V V for i equals to 1, Vn(1) will be achieved at 873mV. This
C3  C5 RMIn RMn (5)
t t calculation is well matched with the simulation results from
Figure 3, and it can be continued to reach the Vn steady.
In these equations, VRMp, VRMn, VRMIp and VRMIn are the Similarly, the Vp steady can be calculated using (8). Also
maximum positive ramp, the minimum negative ramp, ideal according to (8) and (9), the settling times of Vp steady and
value of the maximum positive ramp and the ideal value of Vn steady decrease by increasing the C4/C2 and C5/C3,
the minimum negative ramp, respectively. Integrations of (4) respectively, leading to the increasing slope errors of the final
and (5) yields: ramps

64 ISSN: 2180 – 1843 e-ISSN: 2289-8131 Vol. 12 No. 1 January – March 2020
 A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

III. SIMULATION RESULTS

1.5
The proposed ramp generator is designed in TSMC 0.18- 1.2
μm CMOS. The size of the transistors and capacitors of the
proposed differential ramp generator is given in Table 1. The 0.9

Vrp(V)
ramp generator is designed for 1.8V differential range; this
means that each positive and negative ramp has an output 0.6
range of 0.9V. Figure 2 depicts the integral non-linearity 0.3
(INL) of the positive ramp (INLp), negative ramp (INLn) and 0 10 20 30 40
differential ramp (INLt). The differences of the positive ramp Time (μs)
and negative ramp yield the differential ramp. As illustrated
in this figure, INLt is less than 3.5mV. Moreover, Figure 3(a) (c)
and 3(b), respectively show thevariations of controlling
voltages Vp and Vn to reach the stable values. Also, Figure 1.5
3(c) and 3(d) show the positive and negative ramp voltages, 1.2
respectively, in whin both ramps have the same ranges 0.9
between 0.45V and 1.35V.

Vrn(V)
0.6
Table 1 0.3
Size Of Transistors And Capacitors Of The Proposed Ramp Generator
0
Transistor W/L μm Capacitor fF 0 10 20 30 40
Time (μs)
M0, M5 0.4/0.18 C0, C1 570
(d)
M1-M4 1.0/1.0 C2, C3 951

M6-M9 1.0/1.0 C4, C5 57 Figure 3: Simulation results of the proposed ramp: (a) Vp, (b) Vn, (c) Vrp,
and (d) Vrn.

Table 2 shows the corner analysis of the proposed ramp

4
INLt generator. Linearity, Vp steady and Vn steady are investigated
INLn
2 in these simulations. Corner TT shows the best result for
INLp
linearity parameter, while corner FF shows the worst case.
INL (mV)

0
Table 2
-2 Corner Analysis of the Proposed Ramp Generator

-4 Corner TT FF SS FS SF
99 99.1 99.2 99.3 99.4 99.5 99.6 99.7
Time (μs)
Ramp INL +/- 3.5mV 4.5mV 4.05mV 4mV 4.1mV

Figure 2: INL simulation results of the proposed differential ramp

Vp Steady (V) 1.118 1.164 1.074 1.085 1.154
generator
Vn Steady (V) 0.536 0.493 0.579 0.502 0.569

1.2

1.1 In the conventional ramp generator circuit, the INL

variations in different corners are mostly due to the deviations
1 of the charging current (ICS). For a better understanding of the
Vp(V)

variations of this current, ΔICS is written as:

0.9

0.8 I I 
0 10 20 30 40 I CS   CSI CS   100
 (10)
Time (μs)  I CSI 

(a) In this equation, ICS is the value of the charging current and
0.9 ICSI is the ideal value of charging current that can be
0.8 calculated from (1)Δ. In this case, ICS is represented as a
percentage of ICS variations. A comparison of ΔICS between
0.7
Vn(V)

the conventional and proposed ramp generator circuit was

0.6 made, and the results are shown in Table 3. It is worth
mentioning that, while the proposed ramp circuit generates
0.5
two ramp voltages, its power consumption is less than the
0 10 20 30 40
Time (μs) conventional ramp circuit due to the removal of the circuit in
the the proposed structure[4]. Charging capacitor and
(b) transistors of the conventional ramp circuit were chosen

ISSN: 2180 – 1843 e-ISSN: 2289-8131 Vol. 12 No. 1 January – March 2020 65
Journal of Telecommunication, Electronic and Computer Engineering

similar to the charging capacitor and the transistors of the 100

proposed circuit. Additionally, the conventional ramp
generator was simulated with the same technology of the 80
proposed circuit. The full scale of the conventional ramp

# of occurrences
generator is 1.16V, while the maximum INL of the output 60
ramp is 4mV and the power consumption of the circuit is
about 3.6μW. Table 3 shows a better comparison of the 40
proposed and conventional ramp generators in different
corners. 20

Table 4 shows the capacitor mismatch analysis of the

proposed ramp generator. As indicated in this table, the 0
-5 -4 -3 -2 -1 0 1 2 3 4 5
proposed ramp generator tolerates the mismatches between INL (mV)

capacitors. This mismatch is due to the existing negative Figure 4: Monte Carlo simulation results of the proposed ramp
feedback that changes the ramp slope to reach the ideal ramp generator
voltages. The simulation results also show that while 50
percent mismatch between the capacitors in the proposed Figure 4 depicts the Monte Carlo analysis results of the
ramp generator leads to maximum INL deviations of 1mV; proposed ramp generator with PVT compensation structure.
this mismatch for the conventional ramp generator leads to The channel length modulation, device mismatches,
more than 550mV INL deviations. variations of the threshold voltage and temperature are
considered in the Monte Carlo analysis. As shown in Figure
Table 3 4 the INL variations are between -5mV and +5mV.
Conventional Ramp Generator And The Proposed Ramp Generator
Comparison
IV. CONCLUSION
Corner FF SS FS SF
In this paper, a new technique for increasing the robustness
Conventional ΔICS +4.4% -5.6% -4.8% +4.2% of the ramp generator is proposed. The proposed method
generally can be used for PVT compensation of the similar
Proposed ΔICS +0.4% -0.3% -0.35% +0.3% cases; analytic formulas of this technique were derived to
determine the constraints that should be used for optimizing
Conventional INL +/- 4.5mV 4.05mV 4mV 4.1mV
the output ramp. Further, by combining and sharing the two
current source ramp generators, a fully differential ramp
Proposed INL +/- 42mV 64mV 51mV 47mV
generator circuit, which can be used for counter ADCs, is
invented. The results of a simulation that considers capacitor
Table 4 mismatches verified good performances in all corners. The
Performance of the Proposed Ramp Generator with Capacitor Mismatches power dissipation of the proposed circuit is about 2.61μW for
1MS/s differential output ramp, while it has 9-bit resolution.
CMOS Technology 0.18-μm The analysis and simulation results of the proposed method
show that this technique is completely general, and therefore
Supply (V) 1.8 it can be used in processes below 0.18-µm.
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