APPLICATION NOTE 323

Input filter design - digital

Point of Load
 Abstract Content
Our digital Point of Load products Input filter design...............................................................3
can be configured, controlled and Introduction....................................................3
monitored through a digital serial Stability............................................................4
interface using the PMBus® power Input ripple and noise source.......................4
management protocol. This Input DC bus extra low ripple& noise..........8
application note provides Phase spreading............................................8
information on how to design input
filters for these digital PoL regulators. Design examples .............................................................10
This application note applies to the Single-phase (standalone product)..........10
following products: Two-phase system (paralleled products).12

• BMR461
Appendices.....................................................................14
• BMR462 Appendix A..........................................................14
Appendix B ..........................................................14
• BMR463

• BMR464

• BMR465

• BMR466

• BMR467

• BMR469

• BMR473

• BMR474

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 Input filter design
switching regulator.
Introduction
In many applications, a fairly conventional
Flex Power Modules’ digital PoL regulators are intermediate bus architecture (IBA) is used as
implemented by using a non-isolated synchronous shown in Fig. 2.
buck topology as shown in Fig. 1.

Figure 1a: Simplified schematics Figure 2: In a IBA board IBC feeds multiple PoLs

In an IBA, a board-level intermediate bus

converter (IBC) feeds multiple PoL regulators which
are located in proximity to the load circuitry and
supply the final operating voltages.

All these switching converters generate ripple and

noise on the common DC input bus which should
be suppressed. If it isn’t filtered, input ripple and
noise of a regulator can reach levels high enough
to interfere with other devices powered from the
Figure 1b: Input waveforms of a buck converter
same source.

In addition to the input ripple and noise generated

by the PoL converters, the IBC has its own output
voltage ripple and noise.
During normal operation of a buck power stage,
So the input filter on a PoL regulator may play two
QH and QL are alternatively switched on and off
important roles. One is to prevent electromagnetic
with the on and off times governed by a control
interference, generated by the switching source
circuit with a fixed frequency PWM scheme.
from reaching the power line and affecting other
Output current for a buck power stage is smooth
equipment. The second purpose of the input filter is
as a result of the inductor/capacitor combination
to protect the converter and its load from
on the output side. But input current for a buck
transients that appear in the input voltage thereby
power stage is pulsating or chopped due to the
improving the system reliability. This application
power switch QH current that pulses from zero to
note describes sources of input ripple and noise in
full load every switching cycle. Obviously, the input
PoL regulators and design of input filters to
capacitor is critical for proper operation of the
attenuate its occurrence.
regulator and to minimize noise emissions from a

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 Stability regulator, Zi,PoL,min over the controller bandwidth is
computed as follows.
A filter having attenuation sufficient to meet noise
and ripple specifications is constructed and
added to the input. If the input filter consisting of
(E:2)
only capacitors (C), stability is not a problem. If
the input filter also includes inductors (LC), the
stability must be checked: the input filter changes
the dynamics of the regulator. The output where
impedance may become large over some
• Vi is the input voltage,
frequency range, possibly exhibiting resonances.
The audio susceptibility may be degraded. The • Vo is the output voltage,
problem is that an LC input filter can affect the • Io is the steady state output load current,
dynamics of the converter, often in a manner that
degrades regulator performance. • η is efficiency of the regulator.

An important yet often overlooked aspect of Appendix A permits calculation of the input
input filter design is meeting the Middlebrook impedance of a buck converter with more
criterion. According to the criterion, the input filter details.
does not significantly modify the converter loop
gain if the output impedance curve of the input
filter is far below the input impedance curve of Input ripple and noise sources
the converter, see Equation (1). In other words to For a PoL regulator, the input ripple and noise has
avoid oscillations it is important to keep the peak three components. The first occurs at the
output impedance of the filter, Zo,filter, below the fundamental switching frequency commonly
input impedance of the converter, Zi,PoL. See Fig. referred to as ripple. The second component is
3 for an example AC voltage excursions on the input bus due to
load transient changes at the output of PoL
modules. This is usually a low frequency
phenomenon with settling times of the order of
several hundred microseconds with equivalent
frequencies in the few tens of kHz.

The third noise component is associated with the

very high frequency ringing that occurs during
switching transitions. This type of noise is created
due to the switching action of the PoL when it
draws power from the input source in
Figure 3: Example output impedance of Input filter and
discontinuous current pulses. The frequency of this
input impedance of regulator— waveforms of a buck
component is equal to the switching frequency of
converter: the two curves are separated
the PoL and it has several harmonics, expanding
well into the MHz frequency region.
(E:1)
Another source for high frequency noise on the
DC bus is the IBC. The reflected ripple and noise
from the source converter is usually much smaller
A PoL regulator is designed to supply constant
than the ripple and noise caused by the PoL
voltage to a load, (almost) independently of load
modules.
currents. So the minimum input impedance of the

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 This is due to the fact that typical IBC has an LC
filter at its output which reduces the ripple and (E:4)
noise significantly. Therefore, most of the ripple
and noise created on the input bus is mainly due
to the PoL regulators.
where
Note that all Flex Power Modules’ digital PoL
regulators have ceramic filter capacitors placed • ΔVi,ESR is the input voltage ripple caused by
on the module which reduces the ripple and noise ESR of the input capacitor,
significantly. However, this ripple and noise can be • ESRi is the ESR of input capacitor,
reduced further by placing extra capacitors on
• ΔIpp is the maximum output current ripple.
the input bus of the PoL modules.
According to Equations (3) and (4), to reduce the
input ripple, either increase the capacitance or
Fundamental switching frequency input ripple
decrease the ESR of the input capacitor. Ceramic
For a buck converter, the output inductor capacitors typically have a very low ESR, and
connects to the input during the on portion of the contribute little to the input voltage ripple.
switching cycle and disconnects during off
The input filter capacitors carry the AC
periods. For a constant DC voltage on the input,
component of the current. Most of the ripple
the input capacitor charge at QH on-time must be
current flows through the input ceramic
equal and opposite to the capacitor charge at
capacitors already placed inside the module.
QH off-time. Fig. 1 displays the input capacitor
However, a portion of the AC ripple current is also
wave-shapes and Equation (3) details the amount
drawn from the input bus where most of it is
of ceramic capacitance required to reduce the
supplied by the external input capacitors. It is
ripple voltage amplitude to an acceptable level.
therefore crucial not to exceed the RMS current
The ripple magnitude varies with the input voltage
rating of the external capacitor chosen.
and is a maximum at 50% duty cycle.
The RMS total current distributed between external
(E:3) and internal input capacitors, I Ci,RMS, is calculated
as follows

Note that the input RMS current can be

calculated by sync/phase spreading function in
where
Flex Power Designer (FPD) tool.
• Ci,min is the minimum required ceramic input
capacitance,
(E:5)
• ΔVi,pp is the maximum allowed peak-peak
input ripple voltage,

• fsw is the switching frequency,

• D is the duty cycle as defined above.

The input voltage ripple contributed by the

equivalent series resistance, ESR, can be
estimated as:

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 Low frequency noise due to output transient High frequency noise
When designing a system consisting of a single PoL High frequency input noise in DC/DC converters is a
or multiple PoL modules that make use of a shared product of high frequency ringing or oscillation
bulk input capacitor bank, the first step is to associated with parasitic elements of the converter
calculate the magnitude of the input transient power stage. Energy stored in the parasitic elements
current. This is done by calculating the reflected oscillates or rings during the switching transitions. This
input transient for each PoL module’s output type of noise is usually hundreds of MHz.
transient. After calculating the individual input
Aluminum electrolytic and tantalum capacitors
transients for each module, add them up to get the
have high ESR values and thus are generally not
total transient current. When calculating, one must
suitable for decoupling the switching noise and
determine the worst case transient combination of
ripple of the PoL module. However, they can be
all modules and proceed accordingly. The
used in combination with ceramic capacitors for
magnitude of the input current transient, ΔIi, is
other purposes such as suppressing the lower
calculated from Equation (6):
frequency ripple caused by load transients.

For high frequency attenuation, capacitors with low

(E:6)
ESL and low ESR for ripple current capability must be
selected. To reduce high frequency voltage spikes
at the input of the module, small-package ceramic
where capacitors should be placed at the input of the
• ΔIi is the input transient current, module. Layout is also important in dealing with high
frequency switching ripple and noise. The ceramic
• ΔIo is the output transient current.
capacitors should be placed as close to the PoL
Next, determine the maximum allowable voltage regulator as possible as shown in Fig. 4, followed by
deviation, ΔVtr, on the input bulk capacitors. This is low ESR polymer and aluminum electrolytic
the maximum allowable dip during the peak capacitors if needed. Stray inductance should be
transient step that was calculated in step one. The minimized by using wide traces or shapes and
following equation calculates the minimum required parallel planes.
input bulk capacitance, Ci,tr,min.

(E:7)

where Lftotal is a series filter inductor plus stray

inductance. If not using filter inductor, stray
inductance, Lsrc, should be accounted in the
calculation.

Note that this equation is an approximation. The

value it produces should be considered to be an Figure 4: Example layout of BMR463 module showing
absolute minimum amount. The value of capacitors placing of input capacitors
selected to meet required total capacitance should
take an account impact of the temperature and
other factors such as DC bias and ripple current
derating that can reduce an actual value.

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 Since the RMS current will be shared by the input As can be seen, the X7R capacitor varies only
capacitors, it is recommended that ceramic ±15% over the temperature range of -55 °C to
capacitors be selected such that their impedance 125 °C. Then it finds applications where stability
is considerably lower than the impedance of the over a wide temperature range is required. So X7R
tantalum and/or aluminum electrolytic capacitors is a preferred dielectric due to its good
at the switching frequency. This will ensure that temperature and voltage coefficients. MLCCs
most of the RMS ripple current will flow through the larger than 1210 should be avoided due to
ceramic capacitors and not through the high ESR cracking issues and capacitor manufacturers’
tantalum and/or aluminum electrolytic capacitors. soldering and handling instructions should also be
observed.
Note that X5R multi-layer ceramic capacitors
(MLCCs) offer high capacitance, but
capacitance decreases significantly above 50%
of rated voltage. Typical capacitance change of
X7R capacitor versus DC voltage and
temperature are shown in Figs. 5 and 6.

Figure 5: Typical capacitance change of X7R capacitor

vs. DC voltage

Figure 6: Typical capacitance change of X7R capacitor

vs. temperature

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 The input DC bus with extra-low
ripple and noise The angles are evenly distributed so that a
maximum ripple current cancellation can be
Depending on the application, sometimes the achieved. A general equation for the input
designer’s choice is to insert an inductor between capacitor RMS current, ICi,RMS, can be
the distributed bus and the input of a switching approximated as:
regulator to isolate noise from being coupled to
other circuits on the board. In such cases, the best (E:8)
cost and space saving approach for decoupling is
to use a filter with combination of a small inductor
and capacitors, see Fig. 7.
where m=floor(N*D). The floor function returns the
greatest integer less than or equal to the input
value, N*D, and N is the number of active phases.

Fig. 8 shows the normalized input ripple current

RMS value over the load current versus duty cycle
with different number of active phases.

As can be seen from Equation (8) and Fig. 8, the

input ripple current cancellation is related to the
number of phases and duty cycle. Greater ripple
reduction is generally achieved with additional
Figure 7: Circuit diagram showing a filter with the
combination of an inductor and capacitors phases. Large ripple current will cause very high
power dissipation in the input capacitors due to
the capacitor ESR. The capacitor lifetime also will
The inductor in the filter circuit increases the source
be reduced. In addition to the reduction of the
impedance of the input bus. The value of the
input RMS current, the peak-to-peak current is also
inductor should be chosen in such a way that
reduced due to interleaving.
Equation (1) is satisfied. Appendix B explains how
to choose and design the optimal input filter to
have extra-low noise.

Phase spreading
When multiple PoL regulators share a common DC
input supply, it is desirable to adjust the clock
phase offset of each device such that not all
devices have coincident rising edges. In order to
enable phase spreading, all converters must be Figure 8: Normalized RMS input ripple current vs duty
synchronized to the same switching clock. cycle
Note that Application Note AN309 provides
information on how to synchronize the digital PoL
regulators and use phase spreading for optimized
performance.

In the phase spreading supply, the parallel

regulators are switched at specific phase angles.

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 The switching current in the input capacitor is
typically a large source of high frequency noise.
With the reduced switching current amplitude,
the current slew rate is reduced while providing
the AC current to the high-side MOSFET. Hence,
the noise is reduced. The input ripple frequency
will also be higher than that of single-phase
operation. The higher frequency makes the input
filter smaller and less costly.

The required input capacitance to reduce the

ripple voltage amplitude to an acceptable level
with phase spreading is defined in Equation (9).

(E:9)

The ΔVi,pp is the acceptable input voltage ripple

contributed by the amount of input capacitance,
of which is the input capacitors that filter most of
pulsating currents.

The input voltage ripple induced by the ESR of the

input capacitor, ESRi, can be estimated with
Equation (10).

(E:10)

As can be seen from Equation (9), phase

spreading can dramatically reduce input
capacitance requirements.

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 Design examples
Single-phase (standalone product) (E:13)

Assume a BMR4630008/001 PoL product to

analyze input voltage ripple. The BMR463 is a
single-phase 25 A digital PoL product. It supports a
The distribution of the input RMS current on each
wide range of output voltages (0.6 V to 3.3 V)
single capacitor depends on component
operating from input voltages as low as 4.5 V up
characteristics and module design. The ripple
to 14 V. According to the Technical Specification
current is assumed to divide between capacitors
of the BMR463 series, the product has 70 μF
in proportion to their capacitance. So the RMS
internal input capacitor and the efficiency of the
current through one of the three 22 μF MLCCs will
product is almost η = 94% at Vi = 12 V, Vo = 3.3 V, Io
approximately be 1.84 A (11.37 A * 22 μF / 136 μF).
= 25 A and fsw = 320 kHz.
In the data sheet, the capacitor manufacturer
It is assumed that the input filter should limit the specifies the maximum RMS current through that
peak-to-peak input voltage ripple to 1% of its DC capacitor as 4.55 A which is above the
value, i.e., ΔVi,pp = 120 mV and allowable voltage calculated value.
deviation due to 50% output transient current is
Therefore, there should be no problem with the
ΔVtr = 100 mV.
ripple current flowing through the capacitors.
This section shares a step-by-step guide to
4. Calculate the minimum required input bulk
designing the input filter.
capacitance, Ci,tr,min, to determine 100 mV
1. Calculate the duty cycle, D, of the PoL voltage deviation due to 50% load transient, see
regulator: Equations (6) and (7):

(E:11)
(E:14)

2. Calculate the total input filter capacitance,

Ci,min, needed based on the required peak-to- (E:15)
peak input voltage ripple, see Equation (3):

(E:12)
It is assumed that there is no series filter inductor
and a value of 50 nH is used for Lsrc in the
Since the module has 70 μF internal capacitors, calculation to account for stray inductance in the
minimum required external ceramic input input supply path. According to the calculation
capacitance will be 64.74 μF. So three 22 μF X7R we need 80.91 μF of bulk capacitance as a
external MLCCs in parallel are added to the input minimum. We would use the standard value of
filter in order to get about 1% peak-to-peak input 180 μF. Use low ESR capacitors to implement the
voltage ripple. The spikes caused by the ESL of the bulk network. Capacitors with high ESR induce
input capacitors are decoupled with low ESL 100 voltage drops of their own due to the current
nF ceramic capacitors. flowing in them. Care must be taken when using
very low ESR capacitors together with an input
3. Calculate capacitors’ RMS current,I Ci,RMS, by
inductor as it may cause instability.
Equation (5) or FPD phase spreading function

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 5. Check stability of the system. input inductor in this example, the input current
ripple is reduced to about 150 mA.
The minimum input impedance of the PoL, Zi,POL,min,
under the above operating conditions can be Note that simulation model also helps to plot
calculated using Equation (2). impedance curves and calculate the RMS current
flowing in each capacitor.
The peak output impedance of the input filter,
Zo,max, is

It’s obvious that Zi,POL>> Zo,max, so stability of the

system is guaranteed.

(E:16)

(E:17)

Figure 10: Input voltage ripple for single-phase standalone

module at Vi= 12 V, Vo = 3.3 V and Io = 25 A
Simulation results
The simulated input ripple waveforms at Vi = 12 V,
Vo = 3.3 V and Io = 25 A are shown in Figs. 10 and
11. The simulation indicates a ripple voltage of the
module is about 103 mVp-p which is below 1% of
the input DC bus due to adding a 180 μF bulk
capacitor. The peak to peak input ripple current is
about 1 A. If reflected current ripple is a concern,
use a small input inductor. This is the single most
effective way to confine ripple currents to the
local input bypass capacitors. An input inductor
Figure 11: Input current ripple for single-phase standalone
can reduce the reflected ripple current by an
module at Vi = 12 V, Vo = 3.3 V and Io = 25 A
order of magnitude. A single input inductor can be
shared by multiple PoL modules.

For example, if a 250 nH inductor is used as an

Figure 9: PSpice simulation model for single-phase BMR463 PoL

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 Two-phase system (paralleled 323.63 μF. We would use the nearest standard
value of 470 μF.
products)
Assume two BMR4630008/001 PoL modules are
working in a current sharing group. It is also
Simulation results
assumed that input filter should limit the peak-to- PSpice simulation model of the system is shown in
peak input voltage ripple to 0.5% of its DC value, Fig. 14. The simulated input ripple waveforms at V i =
i.e., ΔVi,pp = 60 mV and allowable voltage 12 V, Vo = 3.3 V and full load are plotted in Figs. 12
deviation due to 50% output transient current is ΔVtr and 13. is about 50 mVp-p which is below 0.5% of
= 100 mV at Vi = 12 V and Vo = 3.3 V and Io = 50 A the input voltage due to adding a 470 μF bulk
and fsw = 320 kHz. Note that N = 2 and m = 0. capacitor. The peak to peak input ripple current is
1. Calculate the total input filter capacitance about 150 mA. The calculations show that by
needed based on the required peak-to- reducing the ripple voltage amplitude the ripple
current will be reduced substantially. With
interleaving, the input ripple frequency will be
(E:18) twice higher than that of single-phase operation as
expected.

peak input voltage ripple, see Equation (9):

Since the system has 140 μF internal capacitors,

minimum required external ceramic input
capacitance will be 18.05 μF. Then only one 22 μF
X7R ceramic capacitor is added to the input filter.

2. Calculate capacitor’s RMS current by

Equation (8) or FPD phase spreading function

3. Calculate the minimum required bulk

capacitance to

(E:19)
Figure 12: Input voltage ripple for dual-phase operation
at Vi = 12 V, Vo = 3.3 V and Io = 50 A.

determine ΔVtr = 100 mV voltage deviation due to

load transient, see Equations (6) and (7):

(E:20)

(E:21)

A value of 50 nH is used for Lsrc in the calculation Figure 13: Input current ripple for dual-phase operation
like the single-phase operation. According to the at Vi = 12 V, Vo = 3.3 V and Io = 50 A
calculation, minimum required bulk capacitance is

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 Figure 14: PSpice simulation model for dual-phase BMR463 PoL

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 Appendices
is ideally infinite. In practice, parasitic elements
such as inductor loss and capacitor ESR limit the
value of QF. Nonetheless, the impedance is very
large close to the filter resonant frequency f0.
Appendix A - input impedance of a
buck converter
Equation (22) permits calculation of the input
impedance of a buck converter, Zi,buck, operating
in continuous conduction mode at any particular
frequency f. It is assumed that the load of the
converter is resistive, where DCR is DC resistance of
an inductor L, RL is resistive load and w = 2πf.

(E:22)

Figure 15: Undamped LC filter

Since the input filter is undamped, it is impossible to

satisfy the Equation (1) close to the input filter cut-
Appendix B – LC filter design off frequency f0. Regardless of the choice of
element values, the input filter changes transfer
As said in Section (4), the combination of a small function of the feedback control loop in the
inductor and capacitors is used to reduce noise vicinity of frequency f0 and causes some
proliferation across the board; however it reduces oscillations at the regulator.
effectiveness of synchronization and phase
spreading in reducing of ripple current stress to To meet the noise filtering requirements the input
local capacitors and also might require increase in filter has to have the cut-off frequency f0 around
a total amount of bulk capacitors. one decade below the bandwidth of the
feedback loop of the PoL regulator.
Undamped LC filter
Damped LC filter
The first simple filter solution is an undamped LC
passive filter shown in Fig. 15. It can be seen that The resonance of the input filter has to be damped
impedance of the filter is given by parallel so that Equation (1) is satisfied at all frequencies.
combination of the inductor and the capacitor. Fig. 16 shows a damped filter made with a resistor
Construction of the Bode diagram of this parallel Rd in series with a capacitor Cd, all connected in
resonant circuit says that the magnitude is parallel with the filter’s capacitor Cf. The purpose
dominated by the inductor impedance at low of resistor Rd is to reduce the output peak
frequency and by the capacitor impedance at impedance of the filter at the cut-off frequency.
high frequency. The inductor and capacitor The capacitor Cd blocks the DC component of the
asymptotes intersect at the filter resonance (cut- input voltage and avoids the power dissipation on
off) frequency, f0. Rd. The capacitor Cd should have lower
impedance than Rd at the resonant frequency and
Since the input filter is undamped, its Q-factor, QF, be a bigger value than the filter capacitor in order
not to affect the cut-off point of the main filter.
(E:23)

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 The optimum damping resistance value, Rd, and
DC blocking capacitor, Cd, can be approximated
as

(E:24)

Note that for the damping block (Cd and Rd), a

capacitor with ESR = Rd and C ≥ Cd can be a good
choice.

Figure 16: Damped filter

Multi-stage LC filter
Most of the time, a multi-stage filter allows higher
attenuation at high frequencies with less volume
and cost, because if the number of single
components is increased, it allows the use of
smaller inductance and capacitance values, see
Fig. 17. Filter inductors should be designed to
reduce parasitic capacitance as much as
possible, the input and output leads should be
kept as far apart as possible and single layer or
banked windings are preferred.

Figure 17: Two stage input filter

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 Flex Power Modules, a business line of Flex, is a leading manufacturer and solution provider of scalable DC/DC power
converters primarily serving the data processing, communications, industrial and transportation markets. Offering a wide
range of both isolated and non-isolated solutions, its digitally-enabled DC/DC converters include PMBus compatibility
supported by the powerful Flex Power Designer.

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