518 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.

2, MARCH 2008

Improved Multilevel Hysteresis Current Regulation

and Capacitor Voltage Balancing Schemes for
Flying Capacitor Multilevel Inverter
Anshuman Shukla, Student Member, IEEE, Arindam Ghosh, Fellow, IEEE, and Avinash Joshi

Abstract—This paper focuses on the development of multilevel

hysteresis current regulation strategies. Two such strategies have
been discussed and some modifications in their control tasks have
been proposed to achieve more reliable and improved perfor-
mance. In general, the multiband concept has been used while Fig. 1. Block diagram of a current controller.
making the proposals. The hysteresis band size considerations
have also been presented by taking into account the desired and
existing system conditions. The proposed modulation schemes
have been applied to a five-level flying-capacitor inverter, whose
deadbeat regulation strategy to create a current regulated mul-
operation under hysteresis current control mode is much less tilevel system, in much the same way that a two-level inverter
established. A new method of flying-capacitor voltage balancing [1], [2]. Harmonics issues with this type of current regulation
is proposed which ensures balanced flying-capacitor voltages system are essentially determined by the voltage PWM strategy
and, at the same time, maintains the desired current profile. It that is used. Linear current controllers are typically character-
uses a time-based approach for controlling the capacitor voltages ized by a limited dynamic response but do have the advantage
and achieves appreciable voltage spectrum under wide range of
load power factor conditions. The performance of the proposed
of a constant switching frequency [1]. In contrast, nonlinear
strategies is confirmed through both simulation and experimental systems use hysteresis comparator to determine the switching
investigations. instants of each switching device and achieve good dynamic
response, unconditional stability and wide command-tracking
Index Terms—Flying-capacitor multilevel inverters (FCMLI),
flying-capacitor voltage, hysteresis, multilevel inverter, time-based bandwidth [1], [2]. The hysteresis control technique has proven
control. to be the most suitable solution for all the applications of
current controlled voltage source inverters where performance
requirements are more demanding, such as active filters, drives
I. INTRODUCTION and high-performance ac power conditioners [1]–[10], albeit
ECENTLY, there have been intense researches devoted to at the expense of variable switching frequency. However,
R the optimization of modulation techniques for the mul-
tilevel inverters. The current controlled pulsewidth modulated
some approaches are available in the literature to obtain fixed
switching frequency under hysteresis control [3].
(PWM) inverters have some advantages compared to the con- The issues associated with hysteresis current control of a two
ventional open-loop voltage source PWM inverters such as: con- level inverter are well known [1]–[3] and the same have also
trol of instantaneous current waveform with high accuracy, peak been dealt with in relation to multilevel inverter systems [4]–[9].
current protection, overload rejection, compensation of effects However, the technique has not yet been effectively applied to
due to load parameter changes and semiconductor voltage drops the flying-capacitor multilevel inverters (FCMLI), where flying-
of the inverters [1], [2]. By comparing a reference and a load capacitor voltage balancing is also an issue in addition to the
current, the current controller generates switching states for the appropriate selection of output voltage level at the band crossing
power electronic devices, which decreases the current error and points of the current error.
provides the desired current waveform for a load. Fig. 1 shows a This paper is the continuation of research on hysteresis mod-
basic diagram of a voltage source PWM inverter with a current ulation strategy of the FCMLI reported in [5]. In the present
control loop. paper, various multilevel hysteresis current control techniques
Current regulation of a multilevel inverter can be imple- have been discussed and corresponding appropriate size of the
mented using either linear or nonlinear strategies. In the linear hysteresis bands have been defined. Additionally, to generalize
strategies, open-loop PWM can be readily used with a syn- the already existing multilevel hysteresis schemes, some im-
chronous frame proportional plus integral (PI) regulator or a provements in the control approach have been proposed. A new
flying-capacitor voltage balancing scheme has also been pro-
posed for the FCMLI. This scheme relies on using the available
Manuscript received June 6, 2007; revised August 20, 2007. Recommended
for publication by Associate Editor B. Wu. redundant switch states more efficiently as compared to those
A. Shukla and A. Joshi are with the Department of Electrical Engineering, In- in the already existing methods. It is shown that this method
dian Institute of Technology, Kanpur 208016, India (e-mail: [email protected]; is particularly attractive for hysteresis current control mode of
[email protected]).
A. Ghosh is with the School of Engineering Systems, Queensland University
operation. Using this scheme, a much improved output voltage
of Technology, Brisbane 4001, Qld, Australia (e-mail: [email protected]). waveform is achieved without in general exceeding the max-
Digital Object Identifier 10.1109/TPEL.2007.915788 imum switching frequency. The principles presented have been
0885-8993/$25.00 © 2008 IEEE
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 519

TABLE I
SWITCHING SCHEME FOR FIVE-LEVEL FCMLI

Fig. 2. Single-phase five-level FCMLI schematic.

verified by both detailed PSCAD/EMTDC simulation and ex-

perimental investigations for a five-level inverter. III. MULTILEVEL HYSTERESIS CURRENT REGULATION
The basic function of a multilevel hysteresis current con-
II. FLYING-CAPACITOR MULTILEVEL INVERTER troller is to generate signals to switch the output of an —level
inverter between the voltage levels to confine the current error
Higher level inverters are able to meet the high voltage and (the measured current minus the reference current) within a
power profiles with better harmonic spectrum at their outputs, specified hysteresis band. At any instant when the current error
without needing higher-rated power semiconductor devices. exceeds a hysteresis limit, the next higher (or lower) voltage
Unfortunately, the number of achievable voltage levels is level should be selected in an attempt to force the current error
limited due to circuit layout, cost and packaging constraints towards zero. However, this new inverter voltage level may not
[11]. Hardware implementation of only upto five-level FCMLI be adequate to achieve this. When this happens, the inverter
has been reported till date in the literature [12]. Fig. 2 shows should switch to the next higher (or lower) voltage level, and
the schematic of one phase of a five-level flying-capacitor the process should cease only when the correct voltage level is
inverter considered in this paper. Each switch in this figure selected that reverses the current error direction. To exemplify,
consists of a power semiconductor device with an antiparallel consider the single-phase five-level inverter of Fig. 2. We can
diode. The switches to are complementary of to then have
respectively. is the dc-link voltage and
and are termed as flying capacitors whose voltages are (2)
regulated using a control scheme at 3 and ,
respectively, to clamp each device voltage stress at . The where and ,
expressions for the currents through and through as a five-level inverter may select from the voltage levels
and the device voltages ( , etc.,) in Fig. 2 use the binary and is the load current,
variables through . These will attain the value 1, if the and are the load inductance and resistance, respectively, and
corresponding switch is closed and 0, otherwise. For any initial is the back emf voltage (Fig. 2). As increases or
state of clamping voltages, the inverter output voltage is given as larger reference current slopes are required, larger average
by values of need to be used. Since the voltage across the load
resistance is often small, this value can often be neglected.
Introducing a term , (where is the reference current
(1) to be tracked using the hysteresis current control), (2) becomes

Using (1), Table I lists the switch combinations used to syn- (3)
thesize five output voltage levels and the corresponding
states of the flying capacitors. Charging of a capacitor is indi- It is evident from (3) that the error can be reduced
cated by , the discharging by , while ‘NC’ indicates neither by increasing or decreasing , depending on the polarity of
charging nor discharging. The switch states given are for the out- . To implement the logic for this correct voltage level
going direction of the current waveform ( in Fig. 2). The states selection logic, two schemes have been discussed in the fol-
( and ) will reverse for the incoming current. It can be seen lowing subsections on the basis of the single-phase five-level
from Table I that the structure offers multiple switch combina- inverter of Fig. 2.
tions for and . As such redundancies are
available, one can choose a preferential switching state for these A. Multi-Offset-Band Multilevel Hysteresis Controller
output voltage levels that will help in maintaining the capacitor A five-level inverter can be current controlled by using the ex-
voltages. The operation and structure details of FCMLI can be tension of the three-level hysteresis control technique proposed
found in [5], [10]–[12], [14]–[18]. in [6] to five-level. As suggested in [6], for an -level inverter,
520 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

Fig. 4. (a) Hysteresis current control with fixed voltage applied at the band
crossings of the current error (A). (b) Inverter switched output voltage (V).
Fig. 3. Multi-offset-band five-level hysteresis current control.

TABLE II
bands are required in this scheme. By following the scheme SIMULATED FIVE-LEVEL FCMLI DEVICE PARAMETERS
of [6], a possible four-band arrangement for control-
ling a five-level inverter is shown in Fig. 3. It is evident from the
figure that as the current error touches the corresponding bound-
aries of , fixed output voltage levels are switched. The
switching takes place when: 1) the error reverses sign and then
crosses the boundary of a band and 2) the error does not reverse
sign but keeps increasing in magnitude and crosses the boundary
of the next higher band for positive error and lower band for
negative error. It can be followed that 0 V is switched at the definition, the voltage level 0 is switched at . However, before
lower limits of and upper limits of at , the output voltage level was and at , the error is
the upper limit of at the lower limit of moving away from the zero line in the negative direction. There-
at the upper limit of and at the lower limit of . fore, was first required to force the error in opposite
Its limitation when using this scheme for a five-level inverter direction. But due to the logical sequence of control, 0 voltage
can be seen by looking at the current error path from to . level is applied at , resulting in rapid increase in the positive
It is evident that a voltage level transition from to 0 V slope of the current error away from the zero-line. The error
occurs at , thereby, skipping the level . This results then touches the upper boundary of and due to more than re-
in bad quality inverter output voltage and large voltage stress quired voltage working on it, crosses and again reaches at the
across the devices at the switching instants. upper boundary of . This results in consecutive switching of
To get a further insight into operational performance of the and , respectively. It is also evident that in this
five-level hysteresis control of Fig. 3, a simulation study is per- process, the intermediate level is skipped as the current
formed using PSCAD/EMTDC software for a five-level inverter error travels from to . This operation is repeated in the con-
(of Fig. 2), supplying an RL-load of and secutive switching cycles and results in degraded voltage wave-
mH. The back emf voltage is taken as zero and the form. It should be noted that since the current error remains in
inverter devices are assumed nearly ideal. The dc-link voltage the allotted bands, the controlled current follows its reference.
is 72 V and flying-capacitor voltages (Fig. 2) are supposed to It is the voltage waveform, which is degraded. However, as is
be balanced at their corresponding reference values using the evident from Fig. 4, the error is bounded within a smaller band
schemes discussed later in Section IV. The output current of the ( or ) in the region when switching the voltage levels 0
inverter ( , Fig. 2) is controlled using the hysteresis scheme and , while due to the control actions of this scheme,
(Fig. 3) to follow a sinusoidal reference having peak-to-peak the error is bounded within a larger band ( or ) in the re-
values of A. Corresponding to Fig. 3, the hysteresis band gion when it is required to output one of the two extreme voltage
sizes are taken to be A and levels . This results in variable tracking performance
A. These values are taken for simplicity by following the con- in a single cycle of the current waveform itself.
siderations presented in Section III-C. Fig. 4 shows the simu- It should be noted that for the simulation studies, the built-in
lation results under this case, where it is evident that this con- IGBT and diode models in the PSCAD/EMTDC software’s
trol results in a poor quality voltage waveform. To justify this master library with the parameters listed in Table II have been
observation, let us first focus on the current error trajectory in used. These parameters are inherent with the device in the soft-
Fig. 4(a). As suggested earlier, between the points and , ware’s library. PSCAD is a graphical front-end to EMTDC for
the error variation outputs the voltages 0 and and as creating models and analyzing results. For building a simulation
the error moves away from , it touches the upper boundary of model of the FCMLI as in Fig. 2, such power semiconductor de-
(Fig. 3) at . By definition, at , the voltage level vice models are accordingly combined with the built-in models
is switched. It causes the current error to reverse its direction, of wires, capacitors, voltage sources, resistances, inductances,
which then reaches the lower boundary of at . Again, by etc. As PSCAD/EMTDC allows the user to develop his own
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 521

Fig. 6. (a) Multi-offset-band five-level hysteresis current control (A).

Fig. 5. Modified multi-offset-band five-level hysteresis current control. (b) Inverter switched output voltage (V).

model in FORTRAN [20], such models have been developed rent error trajectory analysis can be performed in Fig. 6 to justify
for the proposed control schemes implementation. Thus, all the the better waveforms using the control scheme of Fig. 5. A com-
power circuits are implemented using built-in devices models, parison of Fig. 6 with Fig. 4 shows that in the new scheme the
while the proposed control tasks have been achieved using user switching always occurs between adjacent levels and no level
defined FORTRAN programs. is skipped. It should be noted that, in Fig. 4, the controller acts
To overcome the drawbacks of the five-level control of Fig. 3, as desired when switching between , 0 and and
in this paper, a multi-offset-band hysteresis control is proposed. degrades when higher voltage levels are needed to be
The band placement and functioning of the proposed scheme for switched. This indicates that fixed voltage level switching as in
a five-level inverter is shown in Fig. 5. In this scheme, the cur- [6] works fine for the three-level inverter and needs modifica-
rent error is required to be bounded mainly between the bands tion (as in Fig. 5) for higher-level inverters.
and , which are displaced by a small offset . Further, Observing Figs. 3–6, a limitation when using the multi-offset-
two additional offsets of the same width are placed out of band scheme is that this switching process introduces a positive
and to provide a reliable and robust control of the in- or negative dc offset error into the average output current, de-
verter. In general, a total number of offsets are required pending on the polarity of the active output voltage. However,
for an -level inverter in both the positive and negative current this error can be corrected by adding a compensation factor of
error regions. It differs from the method of Fig. 3 in the decision half the hysteresis band offset magnitude to the phase current
logic of the output voltage levels at the crossing points of the [4], [6].
current error and the corresponding boundaries of the hysteresis
bands and also in the total number of bands required. In the B. Time-Based Multilevel Hysteresis Controller
proposed approach, the switched voltage at the band crossing An alternative technique was proposed in [4] to use only one
points of the current error is not fixed but depends on the pre- hysteresis band to detect an out of bounds current error. Digital
vious voltage level, i.e., just before the crossing point. If the cur- logic is used to select the “correct” voltage level in response.
rent error crosses the positive boundary of a band with positive Upon detecting the current error exceeding the upper (or lower)
slope, next lower (than the previous) voltage level is switched hysteresis limit, the inverter output is switched down (or up) one
(e.g., at in Fig. 5). Similarly, if the error crosses the negative voltage level so as to return the error back to zero, as before. But
boundary of a band with negative slope, next higher (than the if the new inverter switched state is inadequate to reverse the
previous) voltage level is switched (e.g., at in Fig. 5). The error back to zero, output is switched further down (or up) until
advantage of the proposed method of Fig. 5 over that of Fig. 3 the current error direction reverses. A possible current error tra-
is evident in the manner that by using the proposed logic, output jectory and inverter switched output for a five-level inverter are
voltage quality is improved and the current follows its reference shown in Fig. 7. Referring to Fig. 7, the objective of this method
with minimum change in voltage levels needed. It should also is to force the current error in a manner so that it remains within
be noted that in this scheme, the number of offset bands is de- band . It is evident that the inverter output is switched one level
cided by the number of steps needed to switch the voltage from up or down as the current error touches the boundary of . If
one extreme ( or ) to another extreme ( this changed output is insufficient to force the error back towards
or , respectively) as the error travels from positive (neg- zero (as at ), next higher or lower voltage level is switched
ative) to negative (positive) region. This can be further under- at the next crossing point of the error and the band limit (as at
stood by following the error trajectory from to in Fig. 5. ). From this figure, it is obvious that the technique does not
Another simulation study is performed using the control of create the steady-state tracking error of the multi-offset-band
Fig. 5 with the same inverter parameters as considered earlier approach (of Figs. 3 and 5). To improve the performance and
and hysteresis band sizes are taken equivalently as robustness of this technique, a current error slope detection algo-
A and A. Fig. 6 shows the results. Similar cur- rithm was used in [8] to switch the voltage levels. An outer band
522 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

a very small value of . Therefore, for varying load and under

high switching frequency operation, this is not a reliable solu-
tion. Another limitation of this scheme is that the two processes:
(i) ceasing of the switching process for after a voltage level
change at and (ii) switching the voltage level if the current
error slope is still positive (negative) after from a voltage level
change at , are locked through . Since is mostly dependent
upon sensor parameters (which are fixed) and the current error
slope is mostly load dependent (which can vary), the approach
certainly lacks the robustness. Further, since this approach needs
to measure the derivative of the current error, noise amplifica-
tion may occur at the sensing end of the controller, which needs
extra hardware to filter it out [7].
Fig. 7. Time-based five-level hysteresis current control. In this paper, an efficient modified time-based multilevel hys-
teresis control scheme has been presented and is shown in Fig. 8.
This approach needs outer bands at from their
was also placed to allow switching to the extreme voltage levels inner ones for an -level inverter and no current error slope de-
for rapid current error reduction during transient conditions (at tection-based control (of [8]) is applied. This implies that, for
out of , Fig. 7). An additional band placement was also example, if the current error crosses with a certain voltage
introduced in [5] for higher-level inverters. Further, a lockout switched at the boundary of , the next voltage level will not
delay (time-based control) was proposed to be added (in [7]) in be switched until the error touches the outer band at from
the switching process for a fixed duration (say, ) immediately . By doing so, the situation like discussed in the above para-
after an inverter state change to compensate for short delay be- graph can be clearly avoided for a sufficient width of . The
tween the generation of gating signals and sensing of the current time-based control, however, is retained in the control process,
error and its derivative. This time-based approach can be seen though, for a different purpose. This is for the case when the
in Fig. 7 between the instants and . It is evident that as the two consecutive crossings of the current error and the band
error keeps on increasing even if a voltage level change has oc- limits are too small time-wise. For example, as shown in Fig. 8,
curred at , after a certain time delay ( , between the instants the time interval between the instants and is considered
and ), another voltage level change at forces the error in smaller than and therefore, another voltage level change does
opposite direction. not occur at . Subsequently, the error reaches at so that a
Although this technique of [4] with the improvements of [5], change in voltage level causes its reversal. Therefore, in effect,
[7], and [8] offers good performance, it needs to be further mod- this method replaces the current error derivative detection con-
ified for better performance under all loading conditions and for trol by a number of bands having fixed widths. Defining it with
very narrow hysteresis band sizes. Under certain loading condi- respect to the method of Fig. 7, it can be said that, the pro-
tions and/or for very narrow hysteresis band sizes, the current posed method replaces the combined monitoring of the vertical
error variations are rapid. In those cases, the error may not re- movement of the current error and horizontal movement of the
verse suddenly at the boundaries of (if it has to) but may take time (of [7]) by only the single monitoring of the vertical move-
some finite time (say, ) depending on the applied voltage level, ment of the current error in deciding to switch the next voltage
hysteresis band size and the load parameters. This type of phe- level out of . This replacement is logical as the main aim of
nomena may also occur under synchronous detuning problem, all the hysteresis control remains to check the vertical move-
which may occur in hysteresis control operation [13]. For those ment of the error (i.e., away from the zero-line). The switching
cases, let us suppose be the time interval for which the cur- decisions are taken only at the boundaries of the bands when
rent error slope is positive (or negative). Now, if is more than the current error moves away from the zero-line. At each such
(defined earlier), the next higher or lower voltage level is crossing, the inverter output is changed by one step (e.g., from
switched after according to the switching logic of [7]. This 0 to , or to , etc.,). In the lower boundary re-
means that unnecessary voltage level transition has taken place gions, the output voltage state changes from lower to higher
as the voltage level appearing just at the boundary of was suf- (i.e., to to 0, 0 to and
ficient enough to force the current error direction (though, after to ) and in the upper boundary regions, from higher to
). Therefore, it can be said that the current error slope detec- lower (i.e., to to 0, 0 to and
tion with time-based control may affect the hysteresis controller to ). At the outermost boundaries, the corresponding
performance depending on various factors. A possible solution extreme output voltage levels are applied
is to set a , which is large enough for any . This means that for rapid current error reduction during transient conditions.
the switching process is ceased for a large , each time after These voltage level transitions ensure that the controlled cur-
the inverter output voltage is switched. However, the value of rent follows its reference with minimum control force needed.
is required to be tuned based on the parameters of the se- The switching strategy can be further understood from Fig. 8. At
lected sensing device and differentiator logic [7]. Further, it has point , the current error crosses the lower boundary of . Be-
to be sufficiently small considering the size of (e.g., for fore this point, the output voltage state was . Therefore,
the case when the error moves from the boundary of towards the next higher voltage level is applied at . The
outer boundaries at , Fig. 7). These considerations result in current error then follows the path as shown and at the crossing
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 523

Fig. 8. Modified time-based five-level hysteresis current control.

Fig. 9. (a) Current error variation across the hysteresis bands (A). (b) Inverter
output voltage (V). (c) Time-difference between consecutive switching (ms).
points shown in the figure (i.e., , etc.,), voltage state transi-
tion takes place as mentioned earlier. A total number of
bands required for an -level inverter in this scheme can be jus-
this scheme, e.g., between and in Fig. 9(a). In Fig. 9(c), the
tified by following the current error trajectory in Fig. 8 and the
time differences between two consecutive switching are plotted.
discussions presented in the earlier presented schemes. It is ev-
This value is checked each time before a next voltage level is
ident from Fig. 8 that this proposed scheme does not need to
applied to have a time-based control. It should be noted that the
measure the derivative of the current error and therefore, does
tuning of along with and should be properly done to
not suffer from noise amplification problem as in [7], [8]. It is
have a good harmonic spectrum of the controlled current and
also clear that it can efficiently work under varying load condi-
voltage, while also taking into consideration the maximum al-
tions as well. The design considerations of and are the
lowable switching frequency (discussed in the next subsection).
same as presented latter in Section III-C.
The time-based control applied in the controlling the current for
To get further insight into the developed hysteresis control
this scheme can also be applied to the other scheme discussed
scheme of Fig. 8 and exemplify its working, simulation studies
earlier corresponding to Figs. 3 and 5.
are performed on a five-level inverter with the current refer-
ence and inverter and load parameters being the same as con- C. Hysteresis Band Size Considerations
sidered in the previous subsection with hysteresis band sizes of
A and A. The value and (delay in the To achieve accurate steady-state reference tracking, precise
time-based control) is taken to be 300 s. This value of is pur- offset tuning of the separation of the hysteresis bands is required
posely taken to be almost equal to the minimum time interval [8]. The size of the hysteresis bands ( in Figs. 3 and 5
between two consecutive switching decisions under the given and in Figs. 7 and 8) is largely determined by the maximum
system conditions to have a better viewing of the controller per- permitted level of current distortion. Generally, under this con-
formance. Note that, for this set of results, the switching fre- dition, a good performance with this scheme can be achieved
quency has been considerably reduced by taking corresponding by simply having the offset band sizes ( , Figs. 3, 5, 7, and
larger hysteresis band sizes, to clearly illustrate the switching 8) equal to the half of the size of the main bands. However, for
process within a fundamental cycle. The simulated waveforms systems requiring more accuracy, the size of should be as
are shown in Fig. 9. The current error variation across the hys- small as possible, as the controlled current and output voltage
teresis bands can be followed from the discussions presented waveform may degrade for a larger , depending on the load
earlier corresponding to Fig. 8. It is evident that at , the error type. The minimum possible size of the bands is mainly deter-
touches the upper boundary of and voltage level 0 is switched mined by the maximum allowable switching frequency of the
at the output of inverter to force the error in the opposite direc- power devices. For example, let us consider the control scheme
tion. However, at , when the error crosses the lower boundary of Fig. 5 and assume that the current error is contained within the
of , the next higher voltage level is not switched as the time main bands using the logic described earlier. At any
interval between the instants and is less than s. point of time, (2) can be rearranged by neglecting the voltage
Therefore, the error crosses at and is forced back in oppo- across the load resistance as
site direction at , i.e., at from the lower boundary of ,
where voltage level is switched. In this way, the cur-
rent is controlled to follow its reference by using the four bands
for a five-level inverter and a five-level output voltage wave-
form is obtained [Fig. 9(b)] for a sinusoidal reference current.
It is also evident that the time-based control is also operative in (4)
524 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

For a certain and (maximum allowable switching

frequency), the smallest size of can be set by
assuming that is equal to its maximum value (i.e., ).
Then, the minimum possible size of can be defined as

(5)

Based on the above analysis, the minimum size of the offset

bands can be similarly defined by the expression of (5).
In a practical circuit, in (4) is the total time delay from
the point of the ac current measurement to the switching of the
power device. This path includes the deadtime of the inverter
switches, the current measurement transducer delay and delays
through the controller and gate driver logic boards.

IV. FLYING-CAPACITOR VOLTAGE BALANCING

The balancing of flying-capacitor voltages is quite important
and dictates both the safe and efficient operation of FCMLI
[9]–[12]. If voltage imbalance occurs, the output voltage quality Fig. 10. (a) Current error and hysteresis band plots with highly inductive load
(A). (b) Inverter output voltage (V). (c) Time-difference between consecutive
degrades and blocking voltages imposed on power devices may switchings (ms).
increase beyond the rated values. Thus, the safe operation of
power devices cannot be guaranteed. Therefore, it is necessary
to take into account the capacitor voltage balancing when de-
signing the control schemes for the FCMLI.
The flying-capacitor voltages are controlled using the inverter
switching states as outlined in Table I. Many studies have shown
that except under certain conditions, a simple open-loop control
guarantees natural balancing of the flying capacitors [14]. How-
ever, the natural balancing property gets very slow, especially
for highly inductive load and/or for low switching frequency.
For those cases, a filter circuit of the type tuned
at the switching frequency and connected in parallel with the
load may be used to achieve the natural balancing [14], [15].
However, the extra filter increases the cost of the overall system
and introduces extra power losses. Although the dynamics of
balancing are improved with the tuned circuit, it may make the
response too slow to follow the rapid variations of the input
voltage [15]. Another method of capacitor voltage balancing is
to vary the duty cycles of the switches to charge or discharge
the corresponding flying capacitor by using redundant switch
states for various voltage levels (Table I) [16]–[19]. To outline
this concept, let us write the flying-capacitor current equation
from Fig. 1 as Fig. 11. (a) Current error and hysteresis band plots with highly resistive load
(A). (b) Inverter output voltage (V). (c) Time-difference between consecutive
(6) switchings (ms).

Further, the capacitor current can also be written as

discharging times of the capacitor become equal. Then, from
(7) (8), the average variation of the flying-capacitor voltages be-
comes zero over a period of time and this keeps their voltages
balanced. These methods, however, are mostly applied to the
Equations (6) and (7) then lead to
carrier-based modulation schemes [16], [17].
Under hysteresis current control mode, it was proposed in
(8) [9] that at each switching instant, a switching sequence chosen
based on the desired output voltage level, direction of load cur-
The methods of capacitor voltage balancing work on the idea rent and capacitor voltage states achieves balanced capacitor
of equating the instantaneous duty cycles of corresponding voltages. The analysis and results presented in [9] confirm that
switches (like, and for , etc.,), so that charging and the scheme balances the flying-capacitor voltages in addition to
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 525

Fig. 13. Control block diagram for one phase leg of a five-level FCMLI.

From the above analysis, it is concluded that flying-capacitor

Fig. 12. (a) Flying-capacitor voltages with highly inductive load (V) and voltages depend on the load parameters and their control mech-
(b) with highly resistive load (V). anism needs to be modified for applications where load power
factor varies. It should be noted that for sufficiently high capac-
itances of the flying capacitors, the voltage variations will not
have desired current tracking using the hysteresis control. How- be too much [as suggested from (8)] and the inverter may work
ever, under varying load impedances, this method needs fur- for large range of inductive parameters of the load. It was sug-
ther improvement. To look into detail of such cases, simulation gested in [5] that by measuring the capacitor voltage states at a
studies are performed for a five-level FCMLI with the same pa- fixed rate, better control over flying-capacitor voltages could be
rameters and current reference as considered earlier. The flying achieved. In the present paper, the scheme is further improved
capacitors are taken of value F for varying load systems by proposing a time-based control of
and the study is performed using hysteresis control of Fig. 8 the capacitor voltages in the following subsection.
with hysteresis band sizes of A and
A. These inverter circuit parameters, reference current value, A. Time-Based Flying-Capacitor Voltage Balancing Control
flying-capacitor capacitances and hysteresis band sizes are the It is evident from Figs. 10(c) and 11(c) that with the increase
same as used in the experimental investigations presented later in inductance of load, switching frequency decreases. It is also
in Section V. Two different loads are considered: 1) one with clear that from the capacitor voltage control perspective, only
H and 2) another with difference between the cases of Figs. 10 and 11 is that in the
and H (inductance in this case is ten times less as latter one, switching operations are faster (the load current in
compared to that in the first case and is accordingly taken to both cases are of the same magnitude). While the average time
keep the total load impedance same in the two cases). The sim- duration between consecutive switching is about 500 s in the
ulation results under these two loading conditions are shown first case (Fig. 10), it is about 80 s in the second case (Fig. 11).
in Figs. 10 and 11, respectively. The flying-capacitor voltages This analysis suggests that if a control action is developed so that
are controlled by using the scheme discussed in [9]. In this switching operations can be done at a predefined rate, flying-ca-
scheme, the controller measures the capacitor voltage states, di- pacitor voltages can be controlled for within a fixed maximum
rection of load current and desired output voltage level (Fig. 8) fluctuation under all load power factor conditions. This is further
to select a proper switch combination (Table I), each time the strengthened from the fact that the available switching states
controlled current crosses any of the defined bands. With ref- (Table I) are sufficient enough to balance flying-capacitor volt-
erence to Fig. 10, these decisions are taken at the band cross- ages over a period of time [5], [14], [18]. The maximum fluc-
ings, e.g., and so on. For a highly inductive load, the rate tuation in the capacitor voltages will be for maximum current
of change of the load current is slower. Therefore, as the in- flowing through the inverter, which is generally decided by the
ductance in the load increases, for same hysteresis band sizes, rating of the inverter.
the time difference between consecutive switching instants in- Based on the above analysis, a flying-capacitor voltage bal-
creases, as between and in Fig. 10 [Fig. 10(c)]. Therefore, ancing technique is proposed in this paper with Fig. 13 showing
the flying-capacitor voltage variation increases as time interval its block diagram representation. In this approach, the current
of (or ) on (or off) increases [from (8)]. This can be fur- error is passed through hysteresis comparators to decide which
ther seen in Fig. 12(a), where the flying-capacitor voltages under output voltage level is required at a particular instant (as in
first loading condition are plotted. It is evident that the capac- Fig. 8). Also, each of the errors between the actual flying-capac-
itor voltages are highly fluctuating resulting in poor quality in- itor voltages ( and ) and their corresponding refer-
verter output voltage waveform [Fig. 10(b)]. It is further evident ence values (denoted as and in Fig. 13) are
from Figs. 11 and 12(b) that for low inductive load, the capac- passed through a zero-band comparator, individually (Note that,
itor voltage fluctuations are less, which result in better quality and , with
inverter output voltage [Fig. 11(b)]. This can be similarly jus- reference to Fig. 2). A time counter is also used, which initiates
tified from the fact the for a highly resistive load, the rate of its counts from zero once a change in the inverter output voltage
change of the load current is faster and therefore, time difference level is requested (e.g., at the points , etc., in Fig. 8). At
between consecutive switching instants are less [Fig. 11(c)]. these points, by following the same logic as discussed earlier,
526 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

the control law decides a most favorable switch state by judging

the outputs of each capacitor voltage comparators, direction of
load current and desired output voltage level. Now, if the counts
of the time counter become more than a pre-specified value be-
fore another voltage level change is requested, the time counter
triggers the sample and hold circuits (S/H) to accordingly set
new desired capacitor voltage states at the input of control law
for the same voltage level output. Based on these desired states
of the capacitors, a most favorable switch state is chosen from
Table I for the corresponding voltage level output. This change
in switch state at the output of control law again initiates and
triggers the time counter. In this manner, this operation is re-
peated at the predefined rate till a next voltage level change is
requested.
To illustrate this voltage balancing proposal, suppose at a cer-
tain instant the current error lies between and (Fig. 8) and
the required output voltage level is 0, which has six switch states
(Table 1). If the time taken by the error to go from to is
larger than a set value (say, ), then multiple samplings of the Fig. 14. (a) Current error and hysteresis band plots with time-based flying-
comparator output can be made between and at the rate capacitor voltage control and with highly inductive load (A). (b) Inverter output
of . In between theses points, if at a particular sampling in- voltage (V). (c) Time counts of the counter with t = 400 s (ms).
stant the situation is such that are overcharged and
is undercharged with a positive , then the switch combina-
tion chosen will be -OFF, -ON, -OFF, and -ON. This
action will lead to discharge and charge (Table I).
The next switch combination at the next switching instant will
be accordingly chosen so that it leads to the most favorable sit-
uation with balanced capacitor voltages. In a similar manner,
for voltage levels , there are four switch combinations
each (Table I), which can accordingly be chosen for these output
voltage levels to force the capacitor voltage error to zero. As
each capacitor has equal number of charging and discharging
operations for the output voltage levels 0 and , balancing
of their voltages can be achieved. There may be a case when not
all the capacitors are involved in a particular switch combina- Fig. 15. (a) Flying-capacitor voltages with t = 200 s (V). (b) Flying-ca-
tion, as is evident from Table I (denoted as NC). In this case, that pacitor voltages with t = 100 s (V).
particular combination will be chosen which offers most favor-
able situation for the capacitors. For example, suppose for the
voltage level “0”, it is required to discharge and charge in Fig. 14 are for s. By comparing the waveforms
. As Table I does not suggest any such switch combination of Fig. 10(b) and Fig. 14(b), it is evident that the inverter output
that can perform all these operations, the most favorable switch voltage profile is much better in the latter case. It can be seen that
combination is selected. The most favorable switch combination if the error does not switch a new voltage level for a time more
is -OFF, -ON, -ON, and -OFF, as it involves desired that , the counter triggers the capacitor voltage comparators to
operation involving two capacitors, while the switch combina- correspondingly output the same voltage level using a different
tion -OFF, -OFF, -ON, and -ON, involves only one. switching states as suggested by Table I. This is exemplified be-
In this manner, by using this strategy the flying-capacitor volt- tween and in Fig. 14. The time counter restarts its count
ages are regulated around their reference values. after each 400 s to maintain the same output voltage level and
The time (defined earlier) can be set at the design stage of execute capacitor voltages balancing as well. However, when
the control by considering the maximum allowable switching the extreme voltage levels are the output, the time
frequency of the power devices. However, in real systems, an counter does not restart its count after every . This is because
additional lockout delay for a fixed duration is also required in does not have redundant switch states and cannot con-
the switching process immediately after a switch state changes tribute in capacitor voltage balancing. The performance of the
to compensate for turn-off time and short delay between the gen- capacitor voltage control proposed above is further evident from
eration of gating signals and sensing of the current and capacitor Figs. 15(a), where much improved capacitor voltage waveforms
voltages. are shown as compared to those in Fig. 12(a). It is also observed
In Figs. 14 and 15, simulation results are shown for FCMLI from Fig. 15(b) that by decreasing , capacitor voltages can
using the hysteresis control of Fig. 8 and capacitor voltage con- be more tightly regulated, which thereby improves the output
trol of Fig. 13. The system conditions are same as considered in voltage quality. One more difference can also be pointed out as
the above section with and H. The plots seen from Fig. 14(a), the error is contained within the main band,
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 527

Fig. 16. Experimental results showing the three flying-capacitor voltages and current error without the time-based capacitor voltage control [14 V/div, 0.15 A/div
(vertical axis), 5.0 ms/div (horizontal axis)].

Fig. 17. Experimental results showing the three flying-capacitor voltages and current error with the time-based capacitor voltage control and t = 1:6 ms [14
V/div, 0.15 A/div (vertical axis), 5.0 ms/div (horizontal axis)].

which improves the controlled current quality as compared with studies, i.e., 72 V and mH, respectively.
Fig. 10(a). This is because in the present case, the “loading ef- The presence of back emf would serve to create more variation
fect” of the capacitors on inverter performance is much less and in the switching frequency but without affecting the nature
the load current is mainly influenced by only the compo- of the current error trajectory. Therefore, for simplicity, back
nent of load. emf voltage source has not been used. The current reference,
It should be noted that the controller of Fig. 13 works on hysteresis band sizes and flying capacitors values are also same
the principle of utilizing the power devices with almost same as considered in the simulation studies presented in Section IV.
switching frequency under all loading conditions. Therefore, Figs. 16–19 show the experimental results of performances
switching frequency limitation is not an issue as can be set at of the flying-capacitor voltage control (Fig. 13) and hysteresis
any suitable value by taking into consideration the flying-capac- current control (Fig. 8). Figs. 16 shows the three flying-capac-
itor values, current rating of inverter and hysteresis band size. It itor voltages and corresponding current error when the capac-
is also to be noted that for sufficiently large capacitances and/or itor voltages are controlled using the method corresponding to
small size of hysteresis bands, the control of Fig. 13 may work the simulation results shown in Figs. 10 and 12(a). As expected
suitably enough without needing the time-based control, i.e., the from the conclusions made above, although the capacitor volt-
time counter block. ages are kept regulated around their corresponding reference
values, they suffer from large fluctuations. This is further justi-
V. EXPERIMENTAL RESULTS fied in Fig. 16(a), where between instants and varies
A prototype of a single-phase five-level IGBT-based FCMLI by a large amount due to large time gap between these instants.
has been built in the laboratory. The experimental investiga- Similar observation can be carried out in Fig. 16(b) between
tions are carried out to validate the proposed flying-capacitor and and in Fig. 16(c) between and . The corresponding
voltage balancing scheme (Fig. 13), while the inverter load output voltage of the inverter is shown in Fig. 19(a), which
current is regulated using the hysteresis control of Fig. 8. The is clearly of poor quality due to large capacitor voltage vari-
flying-capacitor voltages and the load current ations. As the capacitor voltages directly add (or subtract)-up
are sensed using Hall effect voltage and current sensors. with dc-link voltage to generate the intermediate output voltage
These voltage and current signals are acquired by a PC (P-1V, levels, it is evident in Fig. 19(a) that between and , the
2.4 GHz) through analog-to-digital converter (ADC) channels output voltage correspondingly degrades due to large capac-
of a standard data acquisition card (NIDAQmx PCI-6259). itor voltage variation. The results shown in Figs. 17 and 19(b)
Based on these quantities, a program written in Borland C++ are with the control of Fig. 13 with ms. This value
is implemented for the control tasks of Figs. 8 and 13. The of is approximately taken to be four times of the minimum
corresponding switching decision signals are generated at the time duration between two consecutive switching in the case of
digital-output port of the DAQ and are passed to the IGBT Fig. 16(a), i.e., without time-based control (0.4 ms). Similarly,
driver circuits after introducing a lockout delay of 7.5 s the result of 18 and 19(c) are with ms. It is evident
using blanking circuits. The dc-link voltage and inverter load from these figures that the waveforms of capacitor voltages and
parameters are same as considered earlier in the simulation hence output voltage of the inverter improve by reducing . In
528 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

Fig. 18. Experimental results showing the three flying-capacitor voltages and current error with the time-based capacitor voltage control and t = 0:4 ms [14
V/div, 0.15 A/div (vertical axis), 5.0 ms/div (horizontal axis)].

Fig. 19. Experimental results showing inverter output voltage and current error trajectories (a) without time-based capacitor voltage control, (b) with time-based
control and t = 1:6 ms, and (c) with time-based control and t = 0:4 ms [18 V/div, 0.15 A/div (vertical axis), 2.5 ms/div (horizontal axis)].

Fig. 19(b), is elapsed after till to correspondingly se-

lect a new switching state, which improves the voltages quality.
Similar analysis can be made between and in Fig. 19(c).
This is followed by the same conclusions as made from Figs. 14
and 15. It is therefore clear that the capacitor voltages can be
more reliably controlled and inverter output voltage quality can
be improved by using the control scheme of Fig. 13, without,
in general, increasing the switching frequency. By comparing
Fig. 20. Experimental results showing inverter output current under steady
the experimental results with the simulation results presented in state conditions with larger and smaller hysteresis band sizes [1.0 A/div
Section IV, it can be said that the experimental and simulation (vertical axis), 2.5 ms/div (horizontal axis)].
results match closely as expected.
The hysteresis current controller performance can also be
judged from the results shown in Figs. 16–21. In Fig. 16(a),
the voltage appearing at was not sufficient enough to force
the current error in opposite direction. It then crosses and
the “next” voltage level is applied at (at from the lower
boundary of ) to finally force the error back. The load cur-
rent waveform is plotted in Fig. 20(a) with A and
A. Fig. 20(b) shows the load current with
A and A. It should also be noted that since in all
the conditions, the current error is bounded between the allotted Fig. 21. Experimental transient performance of the inverter (a) reference and
limits, the controlled current waveform in all the cases resem- measured load current [0.5 A/div (vertical axis) and (b) output voltage and cur-
bles with the one presented in Fig. 20(a). Further, the tracking rent error (18 V/div, 0.3 A/div (vertical axis), 2.5 ms/div (horizontal axis)].
of the reference load current in all the cases can be confirmed
by looking the current errors for all the cases presented in the
paper. in Fig. 21(b). The charging time of the capacitors, however, de-
Fig. 21 shows the transient performance of the implemented pends on their capacitances, load current, hysteresis band sizes
five-level system under a step change from no load to full load. It and . The fast transient performance of the proposed regulator
is evident that extreme voltage level appears at the in- can be appreciated from the results shown. The experimental re-
verter output to rapidly force the current error back within band sults confirm the correctness of simulation and validate the sim-
. It should be noted that as the inverter is switched from no load ilar behaviors described previously in the simulated cases. The
to full load, the capacitor voltages were zero at start. However, methods of Figs. 3 and 5 has also been verified experimentally
they charge up to their corresponding reference values within a but their results have not been presented in this paper due to the
cycle, as is evident from the waveform of inverter output voltage space limitations.
SHUKLA et al.: IMPROVED MULTILEVEL HYSTERESIS CURRENT REGULATION 529

VI. CONCLUSION [14] R. H. Wilkinson, T. A. Meynard, and H. D. T. Mouton, “Natural bal-

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