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    COA Assignment 2

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    satwikshukla2004

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    © All Rights Reserved
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    COA Assignment 2

    Uploaded by

    satwikshukla2004
    4 views2 pages

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    4 views2 pages

    COA Assignment 2

    Uploaded by

    satwikshukla2004

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    COA Assignment-2 Deadline:22/4/24

    Q1. Define Secondary/Auxiliary Memory and discuss the significance of emerging in-situ
    memory technologies such as ReRAM(Resistive RAM), PCM(Phase Change
    Memory),STTRAM (Spin-Transfer Torque RAM )and SSD(Solid state Drive). How do these
    technologies improve memory performance and efficiency compared to traditional memory
    technologies?

    Q2. Discuss the various cache mapping techniques, including direct-mapped, set-
    associative, and fully associative mapping. Compare and contrast these techniques in terms
    of their complexity, cache hit rate, and implementation overhead.

    Q3. Explain the modes of data transfer: Programmed, Interrupt-initiated, and Direct Memory
    Access (DMA).

    Q4. Differentiate between Multiprogramming, Multiprocessing, Single Instruction Single


    Data Stream (SISD), Single Instruction Multiple Data Stream (SIMD), Multiple Instruction
    Single Data Stream (MISD), and Multiple Instruction Multiple Data Stream (MIMD).

    Q4. Discuss the concepts of Shared memory and distributed memory in Multiprocessors.
    Explain the principles of Parallel processing, including Pipeline processing, Vector
    processing, and Array processors.

    Q5. A pipelined processor has a clock cycle time of 2 nanoseconds and consists of 5 stages.
    Calculate the throughput of the processor in instructions per second. Show your
    calculations.

    Q6. Define the term "pipeline stall" and discuss how it affects processor performance.

    Q7.A five-stage pipeline has stage delays of 100,110,132,155 and 142 nanoseconds. The
    registers that are used between the pipeline stages have a delay of 2 nanoseconds each.
    what will be the total time (in nanoseconds) to execute 50 independent instructions on this
    pipeline, assuming there are no pipeline stalls.

    Q8. Consider a direct mapped cache of size 32KB with block size 32 bytes .The CPU
    generates 32 bit address .find the no of bits required for cache indexing and tag bits.

    Given: a) Cache size: 32 KB b) Block size: 64 bytes

    c) Associativity: 4-way set associative d) Main memory size: 512 KB

    Calculate: 1. The number of sets in the cache. 2. The number of blocks per set. 3. The
    number of bits required for the cache index.

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