Suggestion On Computer Organization & Architecture (CS401)
Suggestion On Computer Organization & Architecture (CS401)
Suggestion On Computer Organization & Architecture (CS401)
28. Write down the difference between RISC and CISC architecture.
29. Differentiate between CISC and RISC architectures. What are their typical
characteristics? Give some examples(s) of processors of each category.
30. What is Amdahl’s law?
Module 5
Module 3
1. What is meant by pipeline architecture? How does it improve the speed of execution of
processor?
2. Explain data hazards with examples.
3. Explain control hazards with examples.
4. Explain structural hazards with examples.
5. Explain the techniques for Increasing ILP.
6. Explain arithmetic and instruction pipeline with proper diagram.
7. What is instruction-level parallelism? How do processors exploit it to improve the
performance?
8. What do you mean by latency, simple cycles, greedy cycles and MAL.
9. What is dynamic pipeline? Distinguish static pipeline from dynamic pipeline.
10. Briefly describe the super-pipeline, super-scalar pipeline and VLIW processor
architecture. What are the limitations of the above architectures?
11. What do you mean by strip mining and vector stride?
12. What is ILP? Explain ILP with example.
13. Short note on
Vector processor (diagram must)
Array processor (diagram must)
VLIW (diagram must)
Super-pipelining (diagram must)
Super scalar (diagram must)
Speed up ratio
Module 4
1. How many 128 X 16 RAM chips are needed to construct a memory capacity of 4096
words (16 bits are one word)? How many lines of address must be used to access a
memory of 4096 words? For chip select, how many lines must be decoded?
2. Explain three types of cache memory mapping techniques.
3. What is locality of reference? What is memory mapping? Why is it needed?
4. What are ‘write through’ and ‘write back’ policies in cache?
5. Illustrate the characteristics of some common memory technologies.
6. Describe in detail about associative memory.
7. Discuss the different mapping techniques used in cache memories and their relative
merits and demerits.
8. Comparing paging and segmentation mechanisms for implementing the virtual memory.
9. Explain the organization of magnetic disk and magnetic tape in detail.
10. What is virtual memory? Why is it called virtual? Write the advantages of virtual
memory?
11. What is locality of reference? What is memory mapping? Why is it needed?
12. What is demand paging? What is segmentation?
13. What is cache memory? Define global miss and local miss with an example.
14. Describe different technique to reduce Miss Rate.
15. Describe different technique to reduce Miss Penalty.
16. Explain how a RAM of capacity 2K bytes can be mapped into the address space (1000) H
to (17FF) H of a CPU having a 16 bits address lines. Show how the address lines are
decoded to generate the chip select condition for the RAM.
17. Given the following, determine size of the sub-fields (in bits) in the address for direct
mapping, associative mapping and set associative mapping cache schemes: We have 256
MB main memory and 1MB cache memory. The address space of this processor is 256
MB. The block size is 128 bytes. There are 8 blocks in a cache set.
18. A hierarchical cache-main memory system has the following specifications:
Cache access time of 160 ns. Main memory access time of 960 ns. Hit ratio of cache
memory is 0.9.
Calculate the following:
i. Average access time of the memory system
ii. Efficiency of the memory system.
19. A three-level memory system having cache access time of 15 ns and disk access time of
80 ns has a cache hit ratio of 0.96 and main memory hit ratio of 0.9. What should be the
main memory access time to achieve effective access time of 25 ns?
20. Explain how cache memory increases the performance of a computer system.
21. Why is the memory system of a computer organized as a hierarchy?
22. A certain program generates the following sequence of word addresses:
i. 5, 6, 10, 8, 14, 24, 4, 12
23. A page has four words; the number of page frames in main memory is 3. How many
page faults are generated if optimum page replacement policy is used?
24. Write short note on RAM and different types of ROM.