SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

D Dual Versions of Highly Stable SN54121 SN54221, SN54LS221 . . . J PACKAGE

and SN74121 One Shots SN74221 . . . N PACKAGE
SN74LS221 . . . D, DB, N, OR NS PACKAGE
D SN54221 and SN74221 Demonstrate (TOP VIEW)
Electrical and Switching Characteristics
That Are Virtually Identical to the SN54121 1A 1 16 VCC
and SN74121 One Shots 1B 2 15 1Rext/Cext
D Pinout Is Identical to the SN54123, 1CLR 3 14 1Cext
SN74123, SN54LS123, and SN74LS123 1Q 4 13 1Q
D Overriding Clear Terminates Output Pulse 2Q 5 12 2Q
2Cext 6 11 2CLR
MAXIMUM 2Rext/Cext 7 10 2B
OUTPUT
GND 8 9 2A
PULSE
TYPE LENGTH(S)
SN54221 21 SN54LS221 . . . FK PACKAGE
SN74221 28 (TOP VIEW)

1R ext /Cext
SN54LS221 49
SN74LS221 70

VCC
NC
1B
1A
description/ordering information
3 2 1 20 19
The ’221 and ’LS221 devices are dual 1CLR 4 18 1Cext
multivibrators with performance characteristics 1Q 5 17 1Q
virtually identical to those of the ’121 devices. NC 6 16 NC
Each multivibrator features a negative-transition- 2Q 7 15 2Q
triggered input and a positive-transition-triggered 2Cext 8 14 2CLR
9 10 11 12 13
input, either of which can be used as an inhibit
input.

2A
2B
GND
NC
2R ext/Cext

NC − No internal connection

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
SN74221N SN74221N
PDIP − N Tube
SN74LS221N SN74LS221N
Tube SN74LS221D
0°C to 70°C SOIC − D LS221
Tape and reel SN74LS221DR
SOP − NS Tape and reel SN74LS221NSR 74LS221
SSOP − DB Tape and reel SN74LS221DBR LS221
SNJ54221J SNJ54221J
CDIP − J Tube
−55°C
−55 C to 125
125°C
C SNJ54LS221J SNJ54LS221J
LCCC − FK Tube SNJ54LS221FK SNJ54LS221FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

   !"# $ %&'# "$  (&)*%"# +"#', Copyright  2004, Texas Instruments Incorporated
+&%#$ %! # $('%%"#$ (' #-' #'!$  '."$ $#&!'#$  (+&%#$ %!(*"# # 2343 "** (""!'#'$ "' #'$#'+
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+' &*'$$ #-'/$' #'+,  "** #-' (+&%#$ (+&%#
#'$#1  "** (""!'#'$, (%'$$1 +'$ # '%'$$"*0 %*&+' #'$#1  "** (""!'#'$,

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

description/ordering information (continued)

Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. Schmitt-trigger input circuitry (TTL hysteresis) for B input allows jitter-free triggering from inputs with
transition at rates as slow as 1 V/s, providing the circuit with excellent noise immunity, typically of 1.2 V. A high
immunity to VCC noise, typically of 1.5 V, also is provided by internal latching circuitry.
Once fired, the outputs are independent of further transitions of the A and B inputs and are a function of the timing
components, or the output pulses can be terminated by the overriding clear. Input pulses can be of any duration
relative to the output pulse. Output pulse length can be varied from 35 ns to the maximum by choosing
appropriate timing components. With Rext = 2 kΩ and Cext = 0, an output pulse typically of 30 ns is achieved
that can be used as a dc-triggered reset signal. Output rise and fall times are TTL compatible and independent
of pulse length. Typical triggering and clearing sequences are shown as a part of the switching characteristics
waveforms.
Pulse-width stability is achieved through internal compensation and is virtually independent of VCC and
temperature. In most applications, pulse stability is limited only by the accuracy of external timing components.
Jitter-free operation is maintained over the full temperature and VCC ranges for more than six decades of timing
capacitance (10 pF to 10 µF) and more than one decade of timing resistance (2 kΩ to 30 kΩ for the SN54221,
2 kΩ to 40 kΩ for the SN74221, 2 kΩ to 70 kΩ for the SN54LS221, and 2 kΩ to 100 kΩ for the SN74LS221).
Throughout these ranges, pulse width is defined by the relationship: tw(out) = CextRext In2 ≈ 0.7 CextRext. In
circuits where pulse cutoff is not critical, timing capacitance up to 1000 µF and timing resistance as low as 1.4 kΩ
can be used. Also, the range of jitter-free output pulse widths is extended if VCC is held to 5 V and free-air
temperature is 25°C. Duty cycles as high as 90% are achieved when using maximum recommended RT. Higher
duty cycles are available if a certain amount of pulse-width jitter is allowed.
The variance in output pulse width from device to device typically is less than ±0.5% for given external timing
components. An example of this distribution for the ’221 is shown in Figure 3. Variations in output pulse width
versus supply voltage and temperature for the ’221 are shown in Figures 4 and 5, respectively.
Pin assignments for these devices are identical to those of the SN54123/SN74123 or SN54LS123/SN74LS123
so that the ’221 or ’LS221 devices can be substituted for those products in systems not using the retrigger by
merely changing the value of Rext and/or Cext; however, the polarity of the capacitor must be changed.

FUNCTION TABLE
(each monostable multivibrator)
INPUTS OUTPUTS
CLR A B Q Q
L X X L H
X H X L H
X X L L H
H L ↑ † †
H ↓ H † †
↑‡ L H † †
† Pulsed-output patterns are tested during
AC switching at 25°C with Rext = 2 kΩ, and
Cext = 80 pF.
‡ This condition is true only if the output of
the latch formed by the two NAND gates
has been conditioned to the logic 1 state
prior to CLR going high. This latch is
conditioned by taking either A high or
B low while CLR is inactive (high).

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

timing component connections

VCC

Rext

To Cext To Rext/Cext
Terminal Terminal

NOTE: Due to the internal circuit, the Rext/Cext terminal never is more positive than the Cext terminal.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

schematics of inputs and outputs

SN54/74221

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC VCC
Req 100 Ω NOM

Input

Output

A Input: Req = 4 kΩ NOM

B, CLR Input: Req = 2 kΩ NOM

SN54/74LS221

EQUIVALENT OF EACH INPUT TYPICAL OF ALL OUTPUTS

VCC VCC
Req 120 Ω NOM

Input

Output

A Input: Req = 25 kΩ NOM

B Input: Req = 15.4 kΩ NOM
CLR: Req = 12.5 kΩ NOM

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, VI (see Note 1): ’LS221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
’221 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN54221 SN74221
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −800 −800 µA
IOL Low-level output current 16 16 mA
B input 1* 1 V/s
∆v/∆t Rise or fall of input pulse rate
A input 1* 1 V/µs
TA Operating free-air temperature −55 125 0 70 °C
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54221 SN74221
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
Positive-going threshold voltage,
VT+ VCC = MIN 1.55 2* 1.55 2 V
B input
Negative-going threshold voltage,
VT− VCC = MIN 0.8* 1.35 0.8 1.35 V
B input
VIK VCC = MIN, II = −12 mA −1.5 −1.5 V
VOH VCC = MIN, IOH = −800 µA 2.4 3.4 2.4 3.4 V
VOL VCC = MIN, IOL = 16 mA 0.2 0.4 0.2 0.4 V
II VCC = MAX, VI = 5.5 V 1 1 mA
A input 40 40
IIH VCC = MAX, VI = 2.4 V µA
A
CLR, B input 80 80
A input −1.6 −1.6
IIL VCC = MAX, VI = 0.4 V mA
CLR, B input −3.2 −3.2
IOS§ VCC = MAX −20 −55 −18 −55 mA
Quiescent 26 50* 26 50
ICC VCC = MAX mA
Triggered 46 80* 46 80
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54221 SN74221
UNIT
MIN MAX MIN MAX
A or B input 50 50
tw Pulse duration ns
CLR 20 20
tsu Setup time, inactive-state¶ CLR 15 15 ns
Rext External timing resistance 1.4* 30* 1.4 40 kΩ
Cext External timing capacitance 0* 1000* 0 1000 µF
Rext = 2 kΩ 67% 67%
Output duty cycle
Rext = MAX Rext 90% 90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶ Inactive-state setup time also is referred to as recovery time.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

switching characteristics VCC = 5 V, RL = 400 Ω, TA = 25_C (see Figures 1 and 2)

FROM TO SN54221 SN74221
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
A 45 70 45 70
tPLH Q
B 35 55 35 55
Cext = 80 pF, Rext = 2 kΩ ns
A 50 80 50 80
tPHL Q
B 40 65 40 65
tPHL Q 27 27
CLR Cext = 80 pF, Rext = 2 kΩ ns
tPLH Q 40 40
Cext = 80 pF, Rext = 2 kΩ 70 110 150 70 110 150
Cext = 0, Rext = 2 kΩ 17 30 50 17 30 50 ns
tw A or B Q or Q
Cext = 100 pF, Rext = 10 kΩ 650 700 750 650 700 750
Cext = 1 µF, Rext = 10 kΩ 6.5* 7 7.5* 6.5 7 7.5 ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.

recommended operating conditions (see Note 4)

SN54LS221 SN74LS221
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.75 5 5.25 V
IOH High-level output current −400 −400 µA
IOL Low-level output current 4 8 mA
B input 1* 1 V/s
∆v/∆t Rise or fall of input pulse rate
A input 1* 1 V/µs
TA Operating free-air temperature −55 125 0 70 °C
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)
SN54LS221 SN74LS221
PARAMETER TEST CONDITIONS† UNIT
MIN TYP‡ MAX MIN TYP‡ MAX
Positive-going threshold voltage,
VT+ VCC = MIN 1 2* 1 2 V
B input
Negative-going threshold voltage,
VT− VCC = MIN 0.7* 0.9 0.8 0.9 V
B input
VIK VCC = MIN, II = −18 mA −1.5 −1.5 V
VOH VCC = MIN, IOH = −400 µA 2.5 3.4 2.7 3.4 V
IOL = 4 mA 0.25 0.4 0.25 0.4
VOL VCC = MIN V
IOL = 8 mA 0.35 0.5
II VCC = MAX, VI = 7 V 0.1 0.1 mA
IIH VCC = MAX, VI = 2.7 V 20 20 µA
A input −0.4 −0.4
IIL VCC = MAX, VI = 0.4 V mA
CLR, B input −0.8 −0.8
IOS§ VCC = MAX −20 −100 −20 −100 mA
Quiescent 4.7 11 4.7 11
ICC VCC = MAX mA
Triggered 19 27* 19 27
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
† For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
‡ All typical values are at VCC = 5 V, TA = 25°C.
§ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature
SN54LS221 SN74LS221
UNIT
MIN MAX MIN MAX
A or B 50 50
tw Pulse duration ns
CLR 40 40
tsu Setup time, inactive state¶ CLR 15 15 ns
Rext External timing resistance 1.4* 70* 1.4 100 kΩ
Cext External timing capacitance 0* 1000* 0 1000 µF
RT = 2 kΩ 50% 50%
Output duty cycle
RT = MAX Rext 90% 90%
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
¶ Inactive-state setup time also is referred to as recovery time.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

switching characteristics VCC = 5 V, RL = 2 kΩ, TA = 25_C (see Figures 1 and 2)

FROM TO SN54LS221 SN74LS221
PARAMETER TEST CONDITIONS UNIT
(INPUT) (OUTPUT) MIN TYP MAX MIN TYP MAX
A 45 70 45 70
tPLH Q
B 35 55 35 55
Cext = 80 pF, Rext = 2 kΩ ns
A 50 80 50 80
tPHL Q
B 40 65 40 65
tPHL Q 35 55 35 55
CLR Cext = 80 pF, Rext = 2 kΩ ns
tPLH Q 44 65 44 65
Cext = 80 pF, Rext = 2 kΩ 70 120 150 70 120 150
Cext = 0, Rext = 2 kΩ 20 47 70 20 47 70 ns
tw A or B Q or Q
Cext = 100 pF, Rext = 10 kΩ 670 740 810 670 740 810
Cext = 1 µF, Rext = 10 kΩ 6* 6.9 7.5* 6 6.9 7.5 ms
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

PARAMETER MEASUREMENT INFORMATION

tw
3V
B†
0V
≥ 60 ns
3V
CLR
0V
tPLH tPHL
VOH
Q
VOL
tPHL tPLH
VOH
Q
VOL

CONDITION 1: TRIGGER FROM B, THEN CLR

3V
B†
0V
≥ 60 ns
3V
CLR
0V

VOH
Q
VOL

CONDITION 2: TRIGGER FROM B, THEN CLR

3V
B†
0V
≥ 50 ns tsu
≥0
3V
CLR
0V
tw
Triggered
VOH
Q
VOL
Not Triggered
CONDITION 3: CLR OVERRIDING B, THEN TRIGGER FROM B

† A is low.

Figure 1. Switching Characteristics

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

PARAMETER MEASUREMENT INFORMATION

3V
B†
0V
≥ 50 ns ≥ 50 ns
3V
CLR
0V

VOH
Q
VOL

CONDITION 4: TRIGGERING FROM POSITIVE TRANSITION OF CLR

tw
3V
A‡
0V
≥ 60 ns
3V
CLR
0V
tPLH tPHL
VOH
Q
VOL
tPHL tPLH
VOH
Q
VOL

CONDITION 5: TRIGGER FROM A, THEN CLR

3V
A‡
0V
tw
VOH
Q
VOL

tw
VOH
Q
VOL

CONDITION 6: TRIGGER FROM A

† A is low.
‡ B and CLR are high.
NOTES: A. Input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50Ω; for SN54/74221, tr ≤ 7 ns,
tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns.
B. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.

Figure 1. Switching Characteristics (Continued)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

PARAMETER MEASUREMENT INFORMATION

VCC
Test
Point

RL

From Output
(see Note B)
Under Test High-Level
CL = 15 pF
Pulse
(see Note A)

tw

Low-Level
Pulse
LOAD CIRCUIT FOR
BI-STATE VOLTAGE WAVEFORMS
TOTEM-POLE OUTPUTS PULSE DURATIONS

3V
Input
0V
tPLH tPHL

Timing 3V In-Phase VOH

Input Output
0V VOL
th tPLH
tsu tPHL
3V VOH
Data
Out-of-Phase
Input
Output
0V VOL
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES PROPAGATION DELAY TIMES

NOTES: A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. In the examples above, the phase relationships between inputs and outputs have been chosen arbitrarily.
D. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω and, for SN54/74221,
tr ≤ 7 ns, tf ≤ 7 ns, for SN54/74LS221, tr ≤ 15 ns, tf ≤ 6 ns.
E. All measurements are made between the 1.5-V points of the indicated transitions for the SN54/74221 or between the 1.3-V points
for the SN54/74LS221.

Figure 2. Load Circuits and Voltage Waveforms

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265





 
 

 
   


   

SDLS213B − DECEMBER 1983 − REVISED NOVEMBER 2004

TYPICAL CHARACTERISTICS (SN54/74221 ONLY)†

VARIATION IN OUTPUT PULSE

DISTRIBUTION OF UNITS
vs
FOR
SUPPLY VOLTAGE
OUTPUT PULSE
1
Cext = 60 pF
VCC = 5 V
Rext = 10 kΩ
TA = 25°C
TA = 25°C

∆ t w − Variation in Output Pulse − %

Relative Frequency of Occurrence

0.5

tw ≈ 420 ns
0 at VCC = 5 V

− 0.5

Median Median
+0.5% +0.5%
−1
4.5 4.75 5 5.25 5.5
Median
VCC − Supply Voltage − V
tw − Output Pulse
Figure 3 Figure 4

VARIATION IN OUTPUT PULSE OUTPUT PULSE

vs vs
FREE-AIR TEMPERATURE TIMING RESISTOR VALUE
1 10 ms
VCC = 5 V Cext = 1 µ F
Cext = 60 pF
Rext = 10 kΩ 1 ms
∆ t w − Variation in Output Pulse − %

Cext = 0.1 µ F
0.5

100 µs
t w − Output Pulse

Cext = 0.01 µ F
tw ≈ 420 ns
0 at TA = 25°C 10 µs
Cext = 1000 pF

1 µs
− 0.5 Cext = 100 pF

100 ns Cext = 10 pF
VCC = 5 V See Note A
TA = 25°C
−1 10 ns
−75 −50 −25 0 25 50 75 100 125 1 2 4 7 10 20 40 70 100
TA − Free-Air Temperature − °C Rext − Timing Resistor Value − kΩ

Figure 5 Figure 6
† Data for temperatures below 0°C and above 70°C, and for supply voltages below 4.75 V and above 5.25 V are applicable for the SN54221 only.
NOTE A: These values of resistance exceed the maximum recommended for use over the full military temperature range of the SN54221.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13

 PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8771101EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8771101EA Samples
& Green SNJ54221J
76042012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 76042012A Samples
& Green SNJ54LS
221FK
7604201EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7604201EA Samples
& Green SNJ54LS221J
7604201FA ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7604201FA Samples
& Green SNJ54LS221W
JM38510/31402B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402B2A
JM38510/31402BEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402BEA
JM38510/31402BFA ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402BFA
M38510/31402B2A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402B2A
M38510/31402BEA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402BEA
M38510/31402BFA ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31402BFA
SN54221J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54221J Samples
& Green
SN54LS221J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54LS221J Samples
& Green
SN74221N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74221N Samples

SN74221NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74221N Samples

SN74LS221DBR ACTIVE SSOP DB 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS221 Samples

SN74LS221DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS221 Samples

SN74LS221N ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LS221NE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS221N Samples

SN74LS221NSR ACTIVE SO NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS221 Samples

SNJ54221J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8771101EA Samples
& Green SNJ54221J
SNJ54LS221FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 76042012A Samples
& Green SNJ54LS
221FK
SNJ54LS221J ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7604201EA Samples
& Green SNJ54LS221J
SNJ54LS221W ACTIVE CFP W 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7604201FA Samples
& Green SNJ54LS221W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 16-Apr-2024

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54221, SN54LS221, SN74221, SN74LS221 :

• Catalog : SN74221, SN74LS221

• Military : SN54221, SN54LS221

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LS221DBR SSOP DB 16 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LS221DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74LS221NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74LS221DBR SSOP DB 16 2000 356.0 356.0 35.0
SN74LS221DR SOIC D 16 2500 340.5 336.1 32.0
SN74LS221NSR SO NS 16 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
76042012A FK LCCC 20 55 506.98 12.06 2030 NA
7604201FA W CFP 16 25 506.98 26.16 6220 NA
JM38510/31402B2A FK LCCC 20 55 506.98 12.06 2030 NA
JM38510/31402BFA W CFP 16 25 506.98 26.16 6220 NA
M38510/31402B2A FK LCCC 20 55 506.98 12.06 2030 NA
M38510/31402BFA W CFP 16 25 506.98 26.16 6220 NA
SN74221N N PDIP 16 25 506 13.97 11230 4.32
SN74221N N PDIP 16 25 506 13.97 11230 4.32
SN74221NE4 N PDIP 16 25 506 13.97 11230 4.32
SN74221NE4 N PDIP 16 25 506 13.97 11230 4.32
SN74LS221N N PDIP 16 25 506 13.97 11230 4.32
SN74LS221N N PDIP 16 25 506 13.97 11230 4.32
SN74LS221NE4 N PDIP 16 25 506 13.97 11230 4.32
SN74LS221NE4 N PDIP 16 25 506 13.97 11230 4.32
SNJ54LS221FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54LS221W W CFP 16 25 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DB0016A SCALE 1.500
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C SEATING
PIN 1 INDEX AREA
PLANE
14X 0.65
16
1

2X
6.5
4.55
5.9
NOTE 3

8
9
0.38
16X
0.22
5.6
B 0.1 C A B
5.0
NOTE 4

0.25
0.09

SEE DETAIL A
2 MAX
0.25
GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4220763/A 05/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-150.

www.ti.com
 EXAMPLE BOARD LAYOUT
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

1 (R0.05) TYP

16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4220763/A 05/2022
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DB0016A SSOP - 2 mm max height
SMALL OUTLINE PACKAGE

16X (1.85) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220763/A 05/2022
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated